Validation of a Verilog-A BJT Model · 2018. 6. 11. · 11-June-2018 VA_model_validation...

June 11, 2018 © ams AG

Validation of a Verilog-A BJT Model

Zoltan Huszka

18th HICUM Workshop 2018 at Rohde&Schwarz, München, Germany

June 19, 2018

Letter Session

11-June-2018 VA_model_validation

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1

Validation of a Verilog-A BJT model

1. Introduction One of the targets of a current CMC [1] project „HICUM/L0 Compact Model Standardization” is to improve the speed performance compared to other existing bipolar (hetero-) junction transistor (BJT/HBT) models. The generally accepted primary reference in a speed ranking list is the BJT in the Berkeley Spice3f5 which is implemented in practically all device simulators typically under Level=1. Therefore the comparision to the optimized C-code based EDA tools is apparently seamless. Issues:

1. the implemented Spice BJT models even in their simplest forms include extensions which may vary in different EDA tools. It can not be verified if the extensions have no effect when the related parameters are left undefined.

2. the speed performance depends on the code optimization which is also tool dependent 3. due to the implementation period and tests the model development may suffer

significant time delay using only EDA tools For the reasons above a need emerged for a Spice BJT model in Verilog-A form. The only such published code could be found in [2]. The excess phase is implemented by a pure exponential time delay by the absdelay(continuous waveform, td) function which is not implemented in all Verilog-A compilers e.g. in ADMS. Moreover the use of the code is subject to the Copywrite of Tiburon Design Automation. For preserving the open source nature of the activities an alternative code is proposed below.

2. The Verilog-A BJT model The model description and the used model card is found in APPENDIX I. The critical issue at the construction of the code was the modeling of the NQS effect. In the EDA implementations the Weil-McNamee [4] approach is used exclusively at transient (TR) simulations. The empirical Bessel filter delay network implemented in the integration code by a few lines practically does not affect the simulation speeed. At AC simulation a simple exponential time delay is adopted which neither implies any appreciable speed degradation. The time domain integration needs the values of previous time steps whose can not be accessed in Verilog-A. The same delay can be realized by an adjunct network [5] which however adds additional nodes to the BJT equivalent. The extra nodes increase the rank of the circuit matrix leading to an extended solution time. Hence, adopting the adjunct network technique would distort the speed comparision to the original Spice3f5. The partitioned charge based (PCB) NQS approach [6] has been adopted as a compromise. This theory is well established and was shown to realize excellent approximation to device simulation (TCAD) data [7]. It can be regarded the generic NQS apporach. Since it involves only a repartitioning of the existing base charge between the internal bi-ei and bi-ci branches it does not require additional effort from the simulators. Consequently it is expected to produce close runtimes to the EDA implementations discussed above. As the input charge delay is absent in the standard BJT it is not dealt with any further here. Additional features of the realization are listed in the header of the code. One thing to notice is that the code compiles in ADMS as well as in EDA compilers without any modifications. This is achieved by the repeated use of the insideADMS compiler directive which is set by ADMS but is missing (unset) in all other Verilog-A compilers. The distinction is needed for some unhandled SPICE features in ADMS. E.g. it does not observe the .OPTIONS TEMP =


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2

... instruction for setting the environmental temperature. Instead temp must be added as a model parameter.

3. Validation It was a primary aim to select the tools which can reliably confirm the correctness of the Verilog-A model. To meet this requirement several simulators were involved in the investigations ranging from educational support University tools to highly professional products. During the comparisions the Verilog-A model was chosen the reference. The „turn-key” feature of QucsStudio [8] was found the simplest for transforming the VA description to a binary engine. It consists of calling the VA code to the workspace and running a „simulation”. A save operation creates a „default” rectangular symbol representing the executable VA model which can be placed in the required circuit. The same process in QUCS [9] is also available but in a more complicated way. The recent QUCS-S simulator [10] appeared to be an attractive shell for invoking SpiceOpus [11], ngspice [12] and Xyce [13] from the QUCS-S domain using its schematic editor and visualization features. The link to the ngspice backend is well elaborated and several circuits could be simulated with the outputs passed back internally to QUCS-S for evaluation. This is not the case with SpiceOpus and Xyce where the netlist transformation appears to be incomplete at the moment. For consistence it was decided to run all involved simulators from command line or from their own interface framework if such exists. Though all – but Xyce - are claimed to basically follow the Spice3f5 conventions no two identical netlists could be adopted.

4. FT Following the DC tests, misalignments were found in the AC characteristics. Therefore the benchmark has been started with one of the most important AC FOMs of high frequency transistors namely with the transit frequency. It is computed as

[ ] )/(/91 2111 yyimagfspotefGHz

T ⋅−= (1) The spot frequency is set to a typical value used for 100GHz plus devices

GHzfspot 2= (2) The DC evaluations have been left to the end when the most suitable simulators could be identified on the basis of their AC performance. In all comparision plots the VA simulated reference results are drawn by solid lines. Data obtained from alternative simulators were converted to *.csv format which could be imported by QucsStudio. The results are shown by star or circle symbols on the same QucsStudio plots that include the Verilog-A originated data. The schematics and ciruit files are detailed for each simulator in APPENDIX II.


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0.7 0.75 0.8 0.85 0.9 0.95 10

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Vbe [V]

FT

[G

Hz]

ft: VerilogA BJTft: QucsStudio LIB BJT

ft: VerilogA BJTft: QucsStudio LIB BJT

Vcb=-0.5V; 0V; 0.5V

1. QucsStudio

0.7 0.75 0.8 0.85 0.9 0.95 10

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Vbe [V]

FT

[G

Hz]

ft: VerilogA BJTft: Qucs LIB BJT

ft: VerilogA BJTft: Qucs LIB BJT

Vcb=-0.5V; 0V; 0.5V

2. QUCS

0.7 0.75 0.8 0.85 0.9 0.95 10

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Vbe [V]

FT

[G

Hz]

ft: VerilogA BJTft: SpiceOpus BJT

ft: VerilogA BJTft: SpiceOpus BJT

Vcb=-0.5V; 0V; 0.5V

3. SpiceOpus

0.7 0.75 0.8 0.85 0.9 0.95 10

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Vbe [V]

FT

[G

Hz]

ft: VerilogA BJTft: NGspice BJT

ft: VerilogA BJTft: NGspice BJT

Vcb=-0.5V; 0V; 0.5V

4. NGspice

0.7 0.75 0.8 0.85 0.9 0.95 10

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Vbe [V]

FT

[G

Hz]

ft: VerilogA BJTft: Xyce BJT

ft: VerilogA BJTft: Xyce BJT

Vcb=-0.5V; 0V; 0.5V

5. Xyce

0.7 0.75 0.8 0.85 0.9 0.95 10

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Vbe [V]

FT

[G

Hz]

ft: VerilogA BJTft: LTspice BJT

ft: VerilogA BJTft: LTspice BJT

Vcb=-0.5V; 0V; 0.5V

6. LTspiceXVII, LTspiceIV


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0.7 0.75 0.8 0.85 0.9 0.95 10

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Vbe [V]

FT

[G

Hz]

ft: VerilogA BJTft: Winspice3 BJT

ft: VerilogA BJTft: Winspice3 BJT

Vcb=-0.5V; 0V; 0.5V

7. Winspice3

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Vbe [V]

FT

[G

Hz]

ft: VerilogA BJTft: DUspice BJT

ft: VerilogA BJTft: DUspice BJT

Vcb=-0.5V; 0V; 0.5V

8. DUspice

Fig. 1 Simulation results overlaid on the Verilog-A BJT model Out of the 8 cases 4 plots display deviations observable by the naked eye. The origin of the problem with QucsStudio and Qucs could be identified. It was discovered in the open source codes that the bias dependence of the transit time (tff) was incorrectly implemented in these tools. QUCS developer Guilherme Torri created a ticket for the fix. The deviations seen with Xyce and DUspice are of unknown origin. The rest of the simulators exhibit visually proper agreements. For a closer look the mismatch has been demonstrated on bar plots. It turns out from Fig. 2 that LTspice provides the best agreement with the QucsStudio simulated Verilog-A model. The other three tools offer approximately the same performance. It does not follow that QucsStudio and LTspice were the most accurate simulators. Other products should also be involved in the investigations though the ranking process would still remain empirical. Anyway, it can be definitely stated that the QucsStudio compiled and run bjt.va code is in compliance to the investigated set of simulators within deviations of max. ~0.3%. Consequently the code is not expected to include systematic and/or theoretical (Spice3f5 violation) bugs from FT determination aspect.

0.7 0.75 0.8 0.85 0.9 0.95 10

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Devia

tion [%

]

Vbe [V]

Deviation of selected simulators to bjt.va (Vcb=0V)

SpiceOpusNGspiceLTspiceWinspice3

Fig. 2 FT simulation mismatch to bjt.va compiled in QucsStudio (reference) using selected

simulators


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5

5. Junction capacitances The capacitances are computed from the admittance parameters

[ ]

[ ]

[ ]ω

ω

ω

/)(151

/)(151

/)(151

1222

12

1211

yyimagecjs

yimagecjc

yyimagecje

fF

fF

fF

+⋅=

⋅−=

+⋅=

(3)

The simulations are made in cold mode that is, using a bias of [ ]V5.0:1.0:2− . For 11y the FT simulation setup is used. 12y and 22y are obtained from a similar setup with the active ac source and DC biasing relocated to the output as seen Fig. 3. For the convenience of the available schematic editor LTspice was used first for the benchmarks. LTspice with bias-T directly compute the two-port parameters by the .net... command. In the bottom schematics the admittance parameters are equal to the source currents.

vcapi (cje)

vcapo (cjs, cjc)

vcapi_nobiasT (cje)

vcapo_nobiasT (cjs, cjc)

Fig. 3 LTspice (varicap) schematics for the junction capacitances top: bias-T drive, bottom: direct combined DC-AC source drive

-2 -1.75 -1.5 -1.25 -1 -0.75 -0.5 -0.25 0 0.25 0.5

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cje

[fF

]

cje: QucsStudiocje: LTspice-biasTcje: LTspice-nobiasTcje: NGspice-biasT

cje: QucsStudiocje: LTspice-biasTcje: LTspice-nobiasTcje: NGspice-biasT

cje

-2 -1.75 -1.5 -1.25 -1 -0.75 -0.5 -0.25 0 0.25 0.5

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Vce [V]

cjs

, cjc

[fF

]

cjs: QucsStudiocjs: LTspice-biasTcjs: LTspice-nobiasTcjc: QucsStudiocjc: LTspice-biasTcjc: LTspice-nobiasT

cjs: QucsStudiocjs: LTspice-biasTcjs: LTspice-nobiasTcjc: QucsStudiocjc: LTspice-biasTcjc: LTspice-nobiasT

cjs, cjc

Fig. 4 Benchmarking QucsStudio results to LTspice and Ngspice Ngspice w/o bias-T for cjs and cjc agrees with QucsStudio, not shown for clarity


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-2 -1.75 -1.5 -1.25 -1 -0.75 -0.5 -0.25 0 0.25 0.5

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7.5

8

8.5

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9.5

Vbe [V]

cje

[fF

]

cje: QucsStudiocje: SpiceOpuscje: Winspice3

cje: QucsStudiocje: SpiceOpuscje: Winspice3

cje

-2 -1.75 -1.5 -1.25 -1 -0.75 -0.5 -0.25 0 0.25 0.5

4

5

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Vce [V]

cjs

, cjc

[fF

]

cjs: QucsStudiocjs: SpiceOpuscjs: Winspice3cjc: QucsStudiocjc: SpiceOpuscjc: Winspice3

cjs: QucsStudiocjs: SpiceOpuscjs: Winspice3cjc: QucsStudiocjc: SpiceOpuscjc: Winspice3

cjs, cjc

Fig. 5 Benchmarking QucsStudio results to SpiceOpus and Winspice3 with bias-T feed (see schematics on Fig. 3 top)

The QucsStudio simulations were performed with the bias-T supply seen on Fig. A1. The C and L elements were of unity (F and H) values. The bias-T fed circuit performing well at FT simulation gave noisy results for the emitter capacitance on Fig. 4. LTspice specialist Helmut Sennewald < [email protected]> confirmed this phenomenon. He proposed a quickfix to „resolve” the issue. Particularly he advised to insert a loss resistance of 1mohm in the bias-T capacitances which can be done in the LTspice properties dialog box of the component. The fix works but obviously it can not be a general solution. A same problem exists in Ngspice roughly with equal intent. Reducing the bias-T capacitances from 1F to 0.1F and the inductances from 1H to 0.1H drastically shrinked the deviation both in Ngspice and LTspice. Omitting the bias-T removed the issue. The output part i.e. cjc and cjs were not affected by the bias-T in these simulators. The noisy SpiceOpus and Winspice3 bias-T fed results are quite close to each other on Fig. 5. As opposed to LTspice and Ngspice the cjs curves are also noisy with these simulators. Reducing the bias-T component values to 0.1 the noise diminished at both simulators. Complete elimination however was only possible by discarding the bias-T circuitry.

5.1 Temperature dependence QUCS and QucsStudio implements the junction capacitance temperature update functions selected by TLEV=2 and TLEVC=0 in ELDO. Using this function results in the plots of Fig. 6. The crude deviation of cjs is due to an implementation bug in QUCS/QucsStudio. In the formula

of the tools’ document technical.pdf Vcs should be replaced by Vsc. The bug has been reported to QUCS developer Guilherme Torri [email protected].


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-2 -1.75 -1.5 -1.25 -1 -0.75 -0.5 -0.25 0 0.25 0.5

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Vbias [V]

cje

[fF

]cje: VerilogAcje: QucsStudio

cje: VerilogAcje: QucsStudio

top-down: -40C, 25C, 125C

cje

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0

10

20

30

40

50

Vbias [V]

cjc

[fF

]

cjc: VerilogAcjc: QucsStudio

cjc: VerilogAcjc: QucsStudio


cjc

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Vbias [V]

cjs

QucsS

tud

io[fF

] cjs

Ve

rilog

A [fF

]

cjs: VerilogAcjs: QucsStudio

cjs: VerilogAcjs: QucsStudio


cjs

Fig. 6 Temperature dependence vs. QucsStudio Verilog-A code includes the ELDO capacitance function at TLEV=2 and TLEVC=0

The QucsStudio outliers of cje and cjc at the highest biases along the -40C0 curves are caused by the incorrectly implemented tff variable discussed at the ft curves. The bug implies different minority charges tff*itf. Apart from the identified implementation failures the temperature dependence of the capacitances agree. Really it could be checked from the open source that the temperature function of the built-in voltages is identical to the referred ELDO function. For a true Spice3f5 compatibilty the capacitance temperature scaling was frozen to the original functions. The following plots display the comparisions to other Spice3f5 derivative tools.

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Vbias [V]

cje

[fF

]

cje: VerilogAcje: LTspice

cje: VerilogAcje: LTspice


cje

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6

8

10

Vbias [V]

cjc

[fF

]

cjc: VerilogAcjc: LTspice

cjc: VerilogAcjc: LTspice


cjc


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-2 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.45

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Vbias [V]

cjs

[fF

]

cjs: VerilogAcjs: LTspice

cjs: VerilogAcjs: LTspice


cjs

Fig. 7 Temperature dependence vs. LTspice

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8

9

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Vbias [V]

cje

[fF

]

cje: VerilogAcje: NGspice

cje: VerilogAcje: NGspice


cje

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8

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Vbias [V]

cjc

[fF

]

cjc: VerilogAcjc: NGspice

cjc: VerilogAcjc: NGspice


cjc

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Vbias [V]

cjs

[fF

]

cjs: VerilogAcjs: NGspice

cjs: VerilogAcjs: NGspice


cjs

Fig. 8 Temperature dependence vs. NGspice

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Vbias [V]

cje

[fF

]

cje: VerilogAcje: SpiceOpus

cje: VerilogAcje: SpiceOpus


cje

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Vbias [V]

cjc

[fF

]

cjc: VerilogAcjc: SpiceOpus

cjc: VerilogAcjc: SpiceOpus


cjc


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-2 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.44

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Vbias [V]

cjs

[fF

]

cjs: VerilogAcjs: SpiceOpus

cjs: VerilogAcjs: SpiceOpus


cjs

Fig. 9 Temperature dependence vs. SpiceOpus and Winspice3

The WinSpice3 environment behaves identical to LTspice and SpiceOpus therefore it is not demonstrated here. cje and cjc are identical in LTspice, Ngspice, SpiceOpus and WinSpice3 while cjs is not temperature scaled in LTspice, SpiceOpus and WinsSpice3.

5.2 Temperature dependence of FT

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Vbe [V]

FT

[G

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ft(Vcb=-0.5V): VerilogAft(Vcb=-0.5V): NGspice

ft(Vcb=-0.5V): VerilogAft(Vcb=-0.5V): NGspice

Vbe: 0.85tmp: 25ft(Vcb=-0.5V): VerilogA: 227




Vbe: 0.935tmp: -40ft(Vcb=-0.5V): VerilogA: 224

Vbe: 0.935tmp: -40ft(Vcb=-0.5V): VerilogA: 224

Vcb=-0.5V, temp=-40C, 25C, 125C

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FT

[G

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ft(Vcb=0V): VerilogAft(Vcb=0V): NGspice

ft(Vcb=0V): VerilogAft(Vcb=0V): NGspice

Vbe: 0.965tmp: -40ft(Vcb=0V): VerilogA: 321

Vbe: 0.965tmp: -40ft(Vcb=0V): VerilogA: 321

Vbe: 0.76tmp: 125ft(Vcb=0V): VerilogA: 326




Vcb=0V, temp=-40C, 25C, 125C

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FT

[G

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ft(Vcb=0.5V): VerilogAft(Vcb=0.5V): NGspice

ft(Vcb=0.5V): VerilogAft(Vcb=0.5V): NGspice

Vbe: 0.815tmp: 125ft(Vcb=0.5V): VerilogA: 369




Vbe: 1tmp: -40ft(Vcb=0.5V): VerilogA: 367

Vbe: 1tmp: -40ft(Vcb=0.5V): VerilogA: 367

Vcb=0.5V, temp=-40C, 25C, 125C

Fig. 10 Temperature dependence of FT vs. NGspice Ngspice was selected for the benchmark as the single tool adopting T-scaling for cjs. The deviation at the Vcb=-0.5V, temp=125C curves is due to the misfit of the cje curves at the last forward bias points on Fig. 8 under the same conditions.


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6. The NQS effect

1e9 1e10 1e11 5e11-120

-100

-80

-60

-40

-20

0

frequency [Hz]

phase(y21) [deg]

py21zf: QucsStudiopy21zf: LTspicepy21zf: NGspicepy21xf: QucsStudiopy21xf: LTspicepy21xf: NGspice

py21zf: QucsStudiopy21zf: LTspicepy21zf: NGspicepy21xf: QucsStudiopy21xf: LTspicepy21xf: NGspice

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phase of y21

1e9 1e10 1e11 5e110.01

0.1

1

frequency [Hz]

mag(y21) [S]

my21zf: QucsStudiomy21zf: LTspicemy21zf: NGspicemy21xf: QucsStudiomy21xf: LTspicemy21xf: NGspice

my21zf: QucsStudiomy21zf: LTspicemy21zf: NGspicemy21xf: QucsStudiomy21xf: LTspicemy21xf: NGspice

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magnitude of y21

Fig. 11 AC simulation with ptf=30 at Vbe=0.95V, Vcb=0V The quasistatic (zf, ptf=0) phase is represented by black, the NQS (xf, ptf=30) phase is represented by blue colour. All the QucsStudio, LTspice and Ngspice results agree. The latter two is the same w/o and with the bias-T circuitry using L = 0.1, C = 0.1. Note that the PCB appoach in the Verilog-A model and the exponential phase delay in Spice3f5 provide the same results.

0 1e-10 2e-10 3e-10 4e-10 5e-10 6e-10 7e-10 8e-10 9e-10 1e-9 1.1e-91.2e-91.3e-90.91

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Ic [A

]

Vb

e [V

]VbeIc-zf: Verilog-A, QucsStudioIc-zf: LTspice

VbeIc-zf: Verilog-A, QucsStudioIc-zf: LTspice

Transient analysis at ptf=0 (zf)

0 1e-10 2e-10 3e-10 4e-10 5e-10 6e-10 7e-10 8e-10 9e-10 1e-9 1.1e-91.2e-91.3e-90.91

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time [s]

Ic [A

]

Vb

e [V

]VbeIc-xf: Verilog-A, QucsStudioIc-xf: LTspice

VbeIc-xf: Verilog-A, QucsStudioIc-xf: LTspice

Transient analysis at ptf=60 (xf)

Fig. 12 Transient simulation with a pulse superimposed to Vbe=0.92V, Vcb=0V Transient simulations are also in full agreement between Verilog-A (QucStudio) and LTspice.

7. Noise The noise behaviour was simulated in the test circuits of Fig. A9_1 (bjt.va in QucsStudio) and Fig. A9_2 (LTspice) in APPENDIX II. The match of the two results is shown on Fig. 13.


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11

0.75 0.8 0.85 0.9 0.95 10

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Vbe [V]

Vn(o

ut)

[nV

/sq

rt(H

z)]

Vnout: Verilog-AVnout: LTspice

Vnout: Verilog-AVnout: LTspice

Fig. 13 Output noise voltage at Vcb=0V, f=10GHz, 50 ohms terminations

8. DC

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0

500

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1e-15

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1e-10

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1e-8

1e-7

1e-6

1e-5

1e-4

1e-3

0.01

Vbe [V]

Ic, Ib

[A

]

Ic/Ib

Ic: QucsStudioIb: QucsStudioIc/Ib: QucsStudioIc: LTspiceIb: LTspiceIc/Ib: LTspice


.options GMIN=0 temp=-40 tnom=25

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0

500

1e3

1.5e3

2e3

1e-13

1e-12

1e-11

1e-10

1e-9

1e-8

1e-7

1e-6

1e-5

1e-4

1e-3

0.01

Vbe [V]

Ic, Ib

[A

]

Ic/Ib



.options GMIN=1e-12 temp=-40 tnom=25

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0

500

1e3

1.5e3

2e3

1e-14

1e-13

1e-12

1e-11

1e-10

1e-9

1e-8

1e-7

1e-6

1e-5

1e-4

1e-3

0.01

0.1

Vbe [V]

Ic, Ib

[A

]

Ic/Ib



.options GMIN=0 temp=25 tnom=25

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0

500

1e3

1.5e3

2e3

1e-13

1e-12

1e-11

1e-10

1e-9

1e-8

1e-7

1e-6

1e-5

1e-4

1e-3

0.01

0.1

Vbe [V]

Ic, Ib

[A

]

Ic/Ib



.options GMIN=1e-12 temp=25 tnom=25


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0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0

500

1e3

1.5e3

2e3

2.5e3

1e-12

1e-11

1e-10

1e-9

1e-8

1e-7

1e-6

1e-5

1e-4

1e-3

0.01

0.1

Vbe [V]

Ic, Ib

[A

]

Ic/Ib



.options GMIN=0 temp=125 tnom=25

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0

500

1e3

1.5e3

2e3

2.5e3

1e-12

1e-11

1e-10

1e-9

1e-8

1e-7

1e-6

1e-5

1e-4

1e-3

0.01

0.1

Vbe [V]

Ic, Ib

[A

]



.options GMIN=1e-12 temp=125 tnom=25

Fig. 14 Forward Gummel at Vcb=0V with Gmin=0 (left) and Gmin=1e-12 (right) Fig. 14 displays the fg characteristics for bjt.va in QucsStudio and in LTspice. On the left pane Gmin=0, on the right one Gmin=1e-12 was set in both simulators (in the model code for QucsStudio) at three temperatures. The perfect fits show the validity of the Verilog-A model moreover that the location of the Gmin branches are correctly selected in the code.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8-0.02

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

Vce [V]

Ic [A

]

fo: Verilog-A bjtfo: LTspice

fo: Verilog-A bjtfo: LTspice

Vbe=0.95V; 1.0V; 1.05V; 1.10V; 1.15V

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

Vce [V]

Ic [A

]

foi:Verilog-A bjtfoi: LTspice

foi:Verilog-A bjtfoi: LTspice

Ib= 10.004uA 50uA 100.4uA 200.8uA 502uA

1.004mA

Fig. 15 Voltage (left) and current (right) controlled forward output curves at t=250 The output charcteristics are displayed on Fig. 15 comparing the Verilog-A coded bjt in QucsStudio and the Spice3f5 bjt in LTspice. Full agreement was found. The missing points on the top line of the output curves are likely the blunder of the rawfile reader. Though not shown on the plots the Ngspice results were in agreement with LTspice. The latter tool was preferred for its convenient built-in schematic editor.


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Summary

Table I.

Match to Verilog-A BJT FT FT_temp caps caps_temp NQS Noise DC&Gmin&temp

QucsStudio no no yes follows ELDO nt nt yes Qucs no no yes follows ELDO nt nt yes LTspice yes nt yes cjs not T-scaled yes yes yes Ngspice yes yes yes yes yes nt yes SpiceOpus yes nt (yes) cjs not T-scaled nt nt nt Xyce no no nt nt nt nt nt Winspice3 yes nt (yes) cjs not T-scaled nt nt nt DUspice no no nt nt nt nt nt

Comments: nt: not tested (yes): bias-T to replace by direct combined AC-DC sources all comparisions were made to the QucsStudio compiled Verilog-A bjt.va engine All the features could be tested and validated by Ngspice. An exception is the RF noise which could not be properly netlisted. This however does not mean that the noise simulation were wrong in the tool: it rather reflects a lack of routine. All in all the proposed bjt.va code can be regarded validated and it can be proposed for using a reference for speed comparisions of unoptimized Verilog-A coded models. Acknowledgment

Thank is due to Didier Celi (STM) for his contributions and advices to these investigations.

REFERENCES

[1] Available: http://www.si2.org/cmc/ [2] Available: http://read.pudn.com/downloads151/sourcecode/others/659709/bjt.va__.htm [3] Didier Celi (STM), ”HICUM/L0 Standardization Towards Phase III: Model Cards for Runtime

Evaluation,” Q4 CMC Meeting, Mountain View, CA December 7-8, 2017 [4] P. Weil and L. McNamee, “Simulation of Excess Phase in Bipolar Transistors,” IEEE Trans. Circ. Syst.,

vol. CAS-25, pp. S.114–116, 1978. [5] C. C. McAndrew, Z. Huszka, and G. Coram, “Bipolar Excess Phase Modeling in Verilog-A,” IEEE

Journal of Solid State circuits, vol. 44, no. 9, pp. 2267–2275, September 2009. [6] H. Klose and A. W. Wieder, “The Transient Integral Charge Control Relation - A Novel Formulation of

the Currents in a Bipolar Transistor,” IEEE Trans. Electron Devices, vol. ED-34, pp. 1090–1099, May 1987. [7] Zoltan Huszka and Anjan Chakravorty, “Implementation of Delay-Time-Based Nonquasi-Static

Bipolar Transistor Models in Circuit Simulators,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 8, AUGUST 2014

[8] Available: http://dd6um.darc.de/QucsStudio/download.html [9] Available: https://sourceforge.net/projects/qucs/files/qucs-binary/0.0.19-snapshots/ [10] Available: https://ra3xdh.github.io/ [11] Available: http://fides.fe.uni-lj.si/spice/download/ [12] Available: http://ngspice.org/ [13] Available: https://xyce.sandia.gov [14] Available: http://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html [15] Available: http://cmosedu.com/cmos1/winspice/winspice.htm [16] Available: https://www.uni-due.de/ebs/toolstipps.php [17] Available: http://aboutme.samexent.com/classes/spring09/ee4111/2001.4_models.pdf


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14

APPENDIX I.

The Verilog-A code of a SPICE3f5 BJT clone //11-June-2018, [email protected]

// SPICE Gummel-Poon bipolar transistor model: A Verilog-A Description of SPICE3f5

// 3-terminal version, substrate capacitance (charge) connected bw. (ci,s)

// simulator specific physical constants selectable by compiler flag

// zero resistance protection performed by specifying MIN_R

// Klose-Wieder PCB w/o extra nodes, ptf=0 implies QS mode...

// "type" model parameter is included but npn/pnp symbol change is simulator dependent

// no limitation is adopted for Vj0.0) begin\

pwq = exp((-1.0-M)*ln(1.0-FC));\

qlo = P*(1.0-pwq*(1.0-FC)*(1.0-FC))/(1.0-M);\

qhi = dvh*(1.0-FC+0.5*M*dvh/P)*pwq;\

end else begin\

qlo = P*(1.0-exp((1.0-M)*ln(1.0-V/P)))/(1.0-M);\

qhi = 0.0;\

end\

qjj = cj0*(qlo+qhi);

// Junction charge with no linearization factor (FC=0, substrate)

`define QJZ(qjj,cj0,V,P,M)\

if (V 0.0) begin\


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if (arg > `Dexp_lim) begin\

le = (1.0 + (arg - `Dexp_lim));\

arg = `Dexp_lim;\

end else begin\

le = 1.0;\

end\

le = le*exp(arg);\

id = isat*(le-1.0);\

end else begin\

id = 0.0;\

end

// Temperature update of junction capacitance parameters

`define TEMPCJ(cj,vj,mj,cj_t,vj_t)\

begin : capT_3f5\

real fact1,fact2,egfet,arg0,pbfact,pbo,gmaold,gmanew,cjt;\

fact1 = Tnom/`REFTEMP;\

fact2 = Tdev/`REFTEMP;\

egfet = Èg0-ègta*Tdev*Tdev/(ègtb+Tdev);\

arg0 = -egfet/(`KB*(Tdev+Tdev))+Èg300/(`KB*(`REFTEMP+`REFTEMP));\

pbfact = -(Vt+Vt)*(1.5*ln(fact2)+`QQ*arg0);\

pbo = (vj-pbfact)/fact1;\

gmaold = (vj-pbo)/pbo;\

cjt = cj/(1+mj*(4e-4*(Tnom-`REFTEMP)-gmaold));\

vj_t = fact2*pbo+pbfact;\

gmanew = (vj_t-pbo)/pbo;\

cj_t = cjt*(1+mj*(4e-4*(Tdev-`REFTEMP)-gmanew));\

end

// borrowed from R3_CMC

`define MAX(x,y) ((x)>(y)?(x):(y))

`define MIN(x,y) ((x)


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//Macros

//IDIO

real arg,le;

//QJ

real dv0,dvh,pwq,qlo,qhi;

//Model

real ttype,Tdev,Tnom,Tamb,tj,rT,dT,lnrT,Vt,Vtnom;

real bf_t,br_t,tbeta,is_t,ise_t,isc_t,cje_t,cjc_t,cjs_t,vje_t,vjc_t,vjs_t;

real ifwd,ibe2,Ibe,ibwd,ibc2,Ibc,Ib,iKq1,Kq2,iKqb,Ifwd,Itzf,Itr;

real Rb,itdep,tff,Qde,Qdc,Qjs,Qje,qjcx,Qjcx,qjci,Qjci;

real opipi,hib,z1,zed,tanz,ftan;

real Qxf1;

real ovaf,ovar,oikf,oikr,argt,fourkt,twoq,flicker_Pwr,noipwr_Rb,noipwr_re,noipwr_rc;

real Vbbi,Veei,Vcci,Veci,Vciei,Vbiei,Vbici,Vbci;

analog begin

`MODEL begin : Model_initialization

// Temperature mappings (code independent of bias)

ìfdef insideADMS

Tamb = temp+`P_CELSIUS0;

èlse

Tamb = $temperature;

èndif

Tdev = `CLAMP((Tamb),(`TMIN+`P_CELSIUS0),(`TMAX+`P_CELSIUS0));

Tnom = tnom+`P_CELSIUS0;

Vt = `KBoQ*Tdev;

Vtnom = `KBoQ*Tnom;

rT = Tdev/Tnom;

lnrT = ln(rT);

dT = Tdev-Tnom;

tbeta = exp(xtb*lnrT);

bf_t = bf*tbeta;

br_t = br*tbeta;

ovaf = ((vaf)>(0)?(1/vaf):(0));

ovar = ((var)>(0)?(1/var):(0));

oikf = ((ikf)>(0)?(1/ikf):(0));

oikr = ((ikr)>(0)?(1/ikr):(0));

argt = xti*lnrT+eg*(rT-1)/Vt;

is_t = is*exp(argt);

ise_t = ise*exp(argt/ne)/tbeta;

isc_t = isc*exp(argt/nc)/tbeta;

`TEMPCJ(cje,vje,mje,cje_t,vje_t);

`TEMPCJ(cjc,vjc,mjc,cjc_t,vjc_t);

`TEMPCJ(cjs,vjs,mjs,cjs_t,vjs_t);

end //of Model_initialization

ttype = type;

Vbbi = ttype*V(br_bbi);

Veei = ttype*V(br_eei);

Vcci = ttype*V(br_cci);

Veci = ttype*V(br_eci);

Vciei = ttype*V(br_ciei);

Vbiei = ttype*V(br_biei);

Vbici = ttype*V(br_bici);

Vbci = ttype*V(br_bci);

begin : Model_evaluation

//currents

ÌDIO(is_t,nf,Vbiei,ifwd);

ÌDIO(ise_t,ne,Vbiei,ibe2);

ÌDIO(is_t,nr,Vbici,ibwd);

ÌDIO(isc_t,nc,Vbici,ibc2);

Ibe = ifwd/bf_t+ibe2;

Ibc = ibwd/br_t+ibc2;

Ib = Ibe+Ibc;

Kq2 = ifwd*oikf+ibwd*oikr;

iKq1 = 1.0-Vbiei*ovar-Vbici*ovaf;

iKqb = 2*iKq1/(1.0+sqrt(1.0+4.0*Kq2));

Itr = ibwd*iKqb;

Itzf = ifwd*iKqb;

//bias dependent base resistance

if (irb == 0) begin

Rb = rbm+(rb-rbm)*iKqb;

end else begin

hib = Ib/irb;

z1 = sqrt(1+144*hib*(ÒPI2))-1;

zed = z1/(24*sqrt(hib)*(ÒPI2));

tanz = tan(zed);

ftan = 3*(tanz-zed)/(zed*tanz*tanz);

Rb = rbm+(rb-rbm)*ftan;

end

//effective transit time

itdep = ifwd/(ifwd+itf);

if (vtf > 0) begin

tff = tf*(1+xtf*exp(Vbici/(1.44*vtf))*itdep*itdep);

end else begin

tff = tf*(1+xtf*itdep*itdep);

end

//diffusion charges

Qde = tff*Itzf;

Qdc = tr*Itr;


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//junction charges

`QJZ(Qjs,cjs_t,Veci,vjs_t,mjs); //fc=0 is assumed in SPICE

`QJ(Qje,cje_t,Vbiei,vje_t,mje,fc);

`QJ(qjcx,cjc_t,Vbci,vjc_t,mjc,fc);

Qjcx = (1-xcjc)*qjcx;

`QJ(qjci,cjc_t,Vbici,vjc_t,mjc,fc);

Qjci = xcjc*qjci;

// Excess Phase calculation (Klose-Wieder charge partitioning)

if (ptf != 0 && tf != 0) begin

Qxf1 = ttype*ptf*`M_PI/180*tf*Itzf;

end else begin

Qxf1 = 0;

end

end //of Model_evaluation

begin : Load_sources

I(br_biei)


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APPENDIX II Simulation details

A1-A2. QucsStudio-QUCS [8][9]

The QucsStudio simulator is used for simulating the reference Verilog-A BJT model shown in APPENDIX I. The results from other simulators transformed to *.csv format are imported by the Project => Import Data feature for representation on the plots showing the VA model result.

P1Num=1Z=50freq=fspot

P2Num=2Z=50freq=fspot

equation

Eqn1den=(1+S[1,1])*(1+S[2,2])-S[1,2]*S[2,1]ny11=(1-S[1,1])*(1+S[2,2])+S[1,2]*S[2,1]y11=ny11/den/r0y21=-2*S[2,1]/den/r0ih21=y11/y21fspot=2e9FT=1e-9*fspot/imag(ih21)r0=50

S parametersimulation

SP1Type=listPoints=fspotoutput=dc

V1U=Vbe

V2U=Vcb+Vbe

C++

cb

e

File=bjt.vatemp=2.5000e+01

Parametersweep

SW1Sim=SP1Param=VbeType=linStart=0.70Stop=1.0Points=61

Parametersweep

SW2Sim=SW1Param=VcbType=listPoints=-0.5; 0; 0.5

BJT_LIBTemp=25

Fig. A1-A2 QucsStudio simulation of the reference Verilog-A BJT model

The rectangular symbol incorporates the Verilog-A executable compiled by the „turn key” feature of QucsStudio. The deactivated (crossed) device is the QucsStudio library BJT filled by the same parameters as the VA file. For benchmarking to QucsStudio the two parts are interchanged. QUCS is used for benchmark, i.e. replacing the bjt.va rectangular part by its library BJT.

A3. SpiceOpus [11]

Fig. A3 Test circuit

proposal of Árpád Buermen SpiceOpus originator, [email protected] (a similar Ngspice netlist was advised formerly by Didier Celi STM as well)


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19

* Comparision of FT with QUCS

.OPTIONS GMIN = 1e-12 TEMP = 25

vb _net1 0 DC 0 AC 1

vc _net0 0 DC 0 AC 0

QT1 _net0 _net1 0 QMOD_T1 AREA=1 TEMP=25

.MODEL QMOD_T1 npn (Is=2.943e-17 Nf=1 Nr=1 Ikf=0.02619 Ikr=0.0003546 Vaf=179.2 Var=1.866 Ise=2.169e-16 Ne=2.001 Isc=0 Nc=1.5

Bf=3169 Br=7.858 Rbm=19 Irb=0 Rc=4.345 Re=0.9333 Rb=40.5 Cje=8.247e-15 Vje=0.7653 Mje=0.1356 Cjc=5.792e-15 Vjc=0.5722

Mjc=0.1835 Xcjc=0.22 Cjs=7.609e-15 Vjs=0.5178 Mjs=0.2143 Fc=0.8271 Tf=3.531e-13 Xtf=83750 Vtf=0.08626 Itf=62.58 Tr=8.666e-11

Kf=0 Af=1 Ptf=0 Xtb=0 Xti=3 Eg=1.17 Tnom=25 )

.control

destroy all

setplot new

nameplot ctl

let z0 = 50

let start_vcb = 0.5

let stop_vcb = 0.5

let vcb_act=start_vcb

let delta_vcb = 0.5

while ctl.vcb_act le ctl.stop_vcb

let start_vbe = 0.7

let stop_vbe = 1.005

let vbe_act=start_vbe

let delta_vbe = 0.005

while ctl.vbe_act le ctl.stop_vbe

let @vb[dc]=ctl.vbe_act

let @vc[dc]=ctl.vcb_act+ctl.vbe_act

ac lin 1 2g 2g

let y11 = -i(vb)

let y21 = -i(vc)

let ih21 = y11/y21

let ft =1e-9*2e9/imag(ih21)

print ctl.vbe_act ctl.vcb_act ft >> ft.data

let ctl.vbe_act = ctl.vbe_act + ctl.delta_vbe

let ctl.number_vbe = ctl.number_vbe +1

end

let ctl.vcb_act = ctl.vcb_act + ctl.delta_vcb

end

destroy all

reset

.endc

.END

Result file: ft_spiceopus.data ctl.ctl.vbe_act = 7.000000e-001

ctl.ctl.vcb_act = -5.00000e-001

ac1.ft = 3.999145e+000

...............................

ctl.ctl.vbe_act = 7.000000e-001

ctl.ctl.vcb_act = 0.000000e+000

ac1.ft = 4.515712e+000

...............................

ctl.ctl.vbe_act = 1.000000e+000

ctl.ctl.vcb_act = 5.000000e-001

ac61.ft = 1.382242e+002

This has been converted to ft_spiceopus.csv by a Matlab program "Vbe";"Vcb";"ft"

0.7;-0.5; 3.999145

0.705;-0.5; 4.739292

....................

0.995; 0.5; 165.6325

1; 0.5; 138.2242

Fig. 3 utilizes the advantage of a combined DC-AC independent voltage source in that its current can be measured in practically all simulators. The (negative) current through vb is 11y , the current of vc provides 21y . It was advised to replace the alter command in sweeps by the let @vb[DC]=value construct (similar to Ngspice). For some reasons though only the first step of the outer loop was recorded in the result.


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20

A4. NGspice [12]




Vb _net1 0 DC 0 AC 1

Vc _net0 0 DC 0 AC 0

QT1 _net0 _net1 0 QMOD_T1 AREA=1 TEMP=25





.control

let z0 = 50

let start_Vcb = -0.5

let stop_Vcb = 0.5

let Vcb_act=start_Vcb

let delta_Vcb = 0.5

echo ""Vbe" "Vcb" "ft"" > ft_ngspice.csv

while Vcb_act le stop_Vcb

let start_Vbe = 0.7

let stop_Vbe = 1.005

let Vbe_act=start_Vbe

let delta_Vbe = 0.005

while Vbe_act le stop_Vbe

alter @Vb[dc] = Vbe_act

alter @Vc[dc] = Vcb_act+Vbe_act

ac lin 1 2g 2g

let y11 = -i(Vb)

let y21 = -i(Vc)

let ih21 = y11/y21

let ft = real(1e-9*frequency/imag(ih21))

echo "$&Vbe_act" , "$&Vcb_act" , "$&ft" >> ft_ngspice.csv

let Vbe_act = Vbe_act + delta_Vbe

end

let Vcb_act = Vcb_act + delta_Vcb

end

destroy all

reset

.endc

.END

Result file: ft_ngspice.csv "Vbe" "Vcb" "ft"

0.7 , -0.5 , 3.99819

0.705 , -0.5 , 4.73801

......................

0.995 , 0.5 , 165.639

1 , 0.5 , 138.233

This can be directly imported by QucsStudio. The s-parameter setup offered by Ngspice was dropped since it biases the transistor through the system resistance R0.

A5. Xyce [13]



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21

*BJT FT Xyce

.OPTIONS DEVICE GMIN = 1e-12 TEMP = 25

QT1 net0 net1 0 QMOD_T1 AREA=1 TEMP=26.85





vbe net1 0 dc {vdc_be} ac 1

vcb net0 net2 dc {vdc_cb} ac 0

eb net2 0 net1 0 1

c1 net2 0 1

.GLOBAL_PARAM vdc_be=0.7

.GLOBAL_PARAM vdc_cb=-0.5

.step vdc_be 0.7 1.0 0.005

.step vdc_cb -0.5 0.5 0.5

.AC LIN 1 2GHz 2GHz

.PRINT AC FORMAT=CSV vdc_be vdc_cb -i(vbe) -i(vcb)

.END

Result file: ft_xyce.cir.FD.csv FREQ,VDC_BE,VDC_CB,Re(I(VBE)),Im(I(VBE)),Re(I(VCB)),Im(I(VCB))

2.00000000e+09,7.00000000e-01,-5.00000000e-01,-9.94940840e-07,-1.42756047e-04,-4.72926304e-04,-8.65116136e-05

2.00000000e+09,7.05000000e-01,-5.00000000e-01,-1.05829221e-06,-1.43899208e-04,-5.71708232e-04,-8.58109939e-05

.............................................................................................................

2.00000000e+09,9.95000000e-01, 5.00000000e-01,-2.95046995e-03,-4.79940214e-03,-4.53859034e-01,5.12339927e-02

2.00000000e+09,1.00000000e+00, 5.00000000e-01,-3.40488852e-03,-5.77020750e-03,-4.60735446e-01,6.30485428e-02

This has been converted to ft_xyce.csv by a Matlab program "Vbe";"Vcb";"ft"

0.7;-0.5;6.856111

0.705;-0.5;8.133945

....................

0.995; 0.5;179.1118

1; 0.5; 150.53

A6. LTspiceXVII, LTspiceIV [14]


The bias-T version has been adopted here since LTspice offers built-in s-parameter setups providing s, y, z and h parameters at a time. * D:\Schematics\LTspice\ft_LTspice\ft.asc

C1 N004 N003 1 Rser=1m

C2 N002 N001 1

R2 N002 0 50

L1 N005 N004 1

L2 N001 N006 1

Q1 N001 N004 0 0 QMOD_T1

V1 N005 0 {vbe}

V2 N003 0 SINE(0 1 {freq}) AC 1 Rser=50

V3 N006 N005 {vcb}


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22

.model NPN NPN

.model PNP PNP

.lib C:\PROGRA~1\LTC\LTSPIC~1\lib\cmp\standard.bjt

.net I(R2) V2

.MODEL QMOD_T1 npn (Is=2.943e-17 Nf=1 Nr=1 Ikf=0.02619 Ikr=0.0003546 Vaf=179.2

+Var=1.866 Ise=2.169e-16 Ne=2.001 Isc=0 Nc=1.5 Bf=3169 Br=7.858 Rbm=19 Irb=0

+Rc=4.345 Re=0.9333 Rb=40.5 Cje=8.247e-15 Vje=0.7653 Mje=0.1356 Cjc=5.792e-15

+Vjc=0.5722 Mjc=0.1835 Xcjc=0.22 Cjs=7.609e-15 Vjs=0.5178 Mjs=0.2143 Fc=0.8271

+Tf=3.531e-13 Xtf=83750 Vtf=0.08626 Itf=62.58 Tr=8.666e-11 Kf=0 Af=1 Ptf=0

+Xtb=0 Xti=3 Eg=1.17 Tnom=25 )

.step param vbe 0.7 1.0 0.005

.ac list {freq}

.param freq=2e9

.step param vcb -0.5 0.5 0.5

.options temp=25 tnom=25

.backanno

.end

Result file: ft.dat #Title: * D:\Schematics\LTspice\ft.asc

#Date: Fri Apr 20 09:56:10 2018

#Plotname: AC Analysis

#Variables(rc): vbe H21(v2)

#Ltsputil: -xorc

#DataColumns: 2

#InfoLines: 14

#DataRows: 183

#SimSteps: 183

#Sweeps: 3

#SweepDef: 1 61

#SweepDef: 2 61

#SweepDef: 3 61

#Values:

7.000000e-001 -4.281190e-001 -1.901200e+000

7.050000e-001 -4.262128e-001 -2.287770e+000

............................................

9.950000e-001 2.987569e+001 -7.016040e+001

1.000000e+000 2.270502e+001 -6.067722e+001

This has been converted to ft_LTspice.csv by a Matlab program "Vbe";"Vcb";"ft"

0.7;-0.5; 3.995211

0.705;-0.5; 4.734347

....................

0.995; 0.5; 165.7641

1; 0.5; 138.3466

LTspiceXVII.exe (64bit) and LTspiceIV.exe (32bit) provided very close results. Only the 32bit simulations are presented here. Thank for Helmut Sennewald < [email protected]> for passing his LTspiceÍV rawfile reader ltsputil.exe and his rawfile converter ltsputil17raw4.exe which transforms the 64bit simulation results to 32bit ones making them acceptable by ltsputil.exe. A7. Winspice3 [15]



* result fills in ft_winspice.log




QT1 _net0 _net1 0 QMOD_T1





.control


let stop_Vcb = 0.5


[email protected]

23


let delta_Vcb = 0.5

let number_Vcb = 0

echo ""vbe" "vcb" "ft"" > ft_winspice.csv


let start_Vbe = 0.7




let number_Vbe = 0


alter vb = Vbe_act

alter vc = Vcb_act+Vbe_act

ac lin 1 2g 2g

let y11 = -i(Vb)

let y21 = -i(Vc)

let ih21 = y11/y21

let ft = real(1e-9*frequency/imag(ih21))

echo "$&vbe_act","$&vcb_act","$&ft" >> ft_winspice.csv


let number_Vbe = number_Vbe +1

end


let number_Vcb = number_Vcb +1

end

destroy all

reset

.endc

.END

Result file: ft_winspice.csv "vbe" "vcb" "ft"

0.7 , -0.5 , 3.99819

0.705 , -0.5 , 4.73801

..................

0.995 , 0.5 , 165.639

1 , 0.5 , 138.233

This can be directly imported by QucsStudio for plotting. A8. DUspice [16]






QT1 _net0 _net1 0 QMOD_T1





.control


let stop_Vcb = 0.5


let delta_Vcb = 0.5

let number_Vcb = 0


let start_Vbe = 0.7




let number_Vbe = 0


alter vb = Vbe_act

alter vc = Vcb_act+Vbe_act

ac lin 1 2g 2g

let y11r = -real(i(vb))

let y11i = -imag(i(vb))

let y21r = -real(i(vc))

let y21i = -imag(i(vc))

print Vbe_act Vcb_act

print y11r y11i y21r y21i


let number_Vbe = number_Vbe +1

end


let number_Vcb = number_Vcb +1


[email protected]

24

end

destroy all

reset

.endc

.END

Result file: ft.log vbe_act = 7.000000e-001

vcb_act = -5.00000e-001

y11r = 1.290702e-006

y11i = 2.474621e-004

y21r = 5.405266e-004

y21i = -1.08550e-004

....................

vbe_act = 1.000000e+000

vcb_act = 5.000000e-001

y11r = 3.689091e-003

y11i = 6.772499e-003

y21r = 4.604388e-001

y21i = -7.40937e-002

ASCII raw file

This has been converted to ft_DUspice.csv by a Matlab program "Vbe";"Vcb";"ft"

0.7;-0.5; 4.539988

0.705;-0.5; 5.391292

....................

0.995; 0.5; 154.6707

1; 0.5; 128.2521

A9. Noise

Fig. A9_1 Noise simulation in QucsStudio

Fig. A9_2 Noise simulation in LTspice

Validation of a Verilog-A BJT Model · 2018. 6. 11. · 11-June-2018 VA_model_validation...

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