Revised Inspiral Rates for Double Neutron Star Systems Chunglee Kim (Northwestern)
Validation and Performance Analysis of Embedded Systems · 2013-09-05 · Model-based Verification,...
Transcript of Validation and Performance Analysis of Embedded Systems · 2013-09-05 · Model-based Verification,...
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Model-based
Verification, Optimization, Synthesis and
Performance Evaluation
of Real-Time Systems
Kim G. Larsen
Aalborg University, DENMARK
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Timed Automata .. and Prices, Games, Probabilities
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Kim G. Larsen
Aalborg University, DENMARK
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Aalborg
Aalborg University leading Danish ICT University in terms of
public investments (33%)
Aalborg
Aarhus
Copenhagen
Jomfru Ane Gade
Verification Theory, Systems and Applications Summer School. September 2013
Kim Larsen [3]
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CISS - Center For Embedded Software Systems
Regional ICT Center (2003- )
3 research groups
Computer Science
Control Theory
HW/SW- codesign
20 Employed
25 Associated
20 PhD Students
50 Industrial projects
10 Elite-students
65 MDKK
ARTIST Design
ARTEMIS
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ES are Pervasive
Characteristica:
Dedicated function Complex environment SW/HW/Mechanics Autonomous Ressource constrained : Energy : Bandwidth : Memory : … Timing constraints
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ES are often Safety Critical
300 horse power
100 processors
How to achieve ES that are: • correct • predicable • dependable • fault tolerant • ressource minial • cheap
.. Model-Based Development
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•8 •8 Sept. 2010 •© MBAT Consortium
Model Based Analysis & Test / ARTEMIS Project (Nov 1, 2011)
•MBAT will provide Europe with a new leading-edge Reference Technology Platform for effective and cost-reducing Validation and
Verification of Embedded Systems
•MBAT will enable the production of high-quality and short-time-to-market transportation products at reduced development costs
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•9 •8 Sept. 2010 •© MBAT Consortium
MBAT Partners
•AVL
•Daimler
•EADS-IW
•Thales
•Alstom
•CEA
•PikeTec
•FH IESE
•Ricardo
•MDH
•Aalborg University
•Elvior
•AIT
•Verified
•Absint
•Airbus
•ENS
•OFFIS
•MBtech
•BTC-ES
•KTH
•Volvo
•Selex Sistemi Integrati
•AleniaSIA
•Prover
•Rockwell Colins •TUM
•EADS-DE
•Siemens
•TU Graz
•AMET
•GeenSoft
•ALES
•Ansaldo STS
•VIF
•Infineon Austria
•All4Tec
•IBM
•Large Company, technology user
•SME, technology provider
•Large Tool Provider
•Researcher, technology provider
•National Co-ordinator
•ENEA
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•10 •8 Sept. 2010 •© MBAT Consortium
Early Testing at Daimler
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•11 •8 Sept. 2010 •© MBAT Consortium
MBAT combined methodological approach
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Model Checking
TOOL
System Description
Requirement
Yes Prototypes
Executable Code Test sequences
No! Debugging Information
A( req ) A} grant)
A( req ) A}t<30s grant)
A( req ) A}t<30s , p>0.90 grant)
A( req ) A}t<30s,c<5$ grant)
Time Cost Probability
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TOOL
System Description
Requirement
Yes Control Strategy
No! Debugging Information
A( req ) A} grant)
A( req ) A}t<30s grant)
A( req ) A}t<30s,c<5$ grant)
Synthesis
Time Cost Probability ?
A( req ) A}t<30s , p>0.90 grant)
Verification Theory, Systems and Applications Summer School. September 2013
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Overview
Timed Automata & UPPAAL Symbolic Verification &
UPPAAL Engine, Options
Priced Timed Automata and Timed Games
Stochastic Timed Automata
Statistical Model Checking
(Lecture + Exercise)4
TRON
CLASSIC
TIGA
CORA
ECDAR
SMC
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www.cs.aau.dk/~kgl/Shanghai2013
www.uppaal.org
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Timed Automata
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UPPAAL (1995- )
@UPPsala Wang Yi
Paul Pettersson
John Håkansson
Anders Hessel
Pavel Krcal
Leonid Mokrushin
Shi Xiaochun
@AALborg Kim G Larsen Alexandre David Gerd Behrman Marius Mikucionis Jacob I. Rasmussen Arne Skou Brian Nielsen Shuhao Li
y = 3,4322x2 - 28,247x + 749,99
0
5000
10000
15000
20000
25000
30000
35000
40000
To
tal D
ow
nlo
ad
s
YYMM
UPPAAL Downloads
@Elsewhere Emmanuel Fleury, Didier Lime, Johan Bengtsson,
Fredrik Larsson, Kåre J Kristoffersen, Tobias Amnell,
Thomas Hune, Oliver Möller, Elena Fersman, Carsten
Weise, David Griffioen, Ansgar Fehnker, Jan Tretmans,
Frits Vandraager, Theo Ruys, Pedro D’Argenio, J-P
Katoen,, Judi Romijn, Ed Brinksma, Martijn Hendriks,
Klaus Havelund, Franck Cassez, Magnus Lindahl,
Francois Laroussinie, Patricia Bouyer, Augusto
Burgueno, H. Bowmann, D. Latella, M. Massink, G.
Faconti, Kristina Lundqvist, Lars Asplund, Justin
Pearson.....
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Real Time Systems
Plant Continuous
Controller Program Discrete
Eg.: Realtime Protocols Pump Control Air Bags Robots Cruise Control ABS CD Players
Production Lines
Real Time System A system where correctness not only depends on the logical order of events but also on their timing!!
sensors
actuators
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A Dumb Light Controller
Verification Theory, Systems and Applications Summer School. September 2013
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Timed Automata
ADD a clock x
Synchronizing
action
Clock Guard
Conjunctions of
x~n
x: real-valued
clock
Reset
[Alur & Dill’89]
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A Timed Automata (Semantics)
States:
( location , x=v) where v2R
Transitions:
( Off , x=0 )
delay 4.32 ( Off , x=4.32 )
press? ( Light , x=0 )
delay 2.51 ( Light , x=2.51 )
press? ( Bright , x=2.51 )
Verification Theory, Systems and Applications Summer School. September 2013
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Intelligent Light Controller
Invariant
(Henzinger)
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Intelligent Light Controller
Transitions:
( Off , x=0 )
delay 4.32 ( Off , x=4.32 )
press? ( Light , x=0 )
delay 4.51 ( Light , x=4.51 )
press? ( Light , x=0 )
delay 100 ( Light , x=100)
( Off , x=0)
Note:
( Light , x=0 ) delay 103
X
Invariants ensures progress
Verification Theory, Systems and Applications Summer School. September 2013
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Timed Automata (formally)
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Timed Automata (formally)
Verification Theory, Systems and Applications Summer School. September 2013
Kim Larsen [25]
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Timed Automata (formally)
Verification Theory, Systems and Applications Summer School. September 2013
Kim Larsen [26]
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Timed Automata (formally)
Verification Theory, Systems and Applications Summer School. September 2013
Kim Larsen [27]
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Timed Automata: Example
guard
reset
synchronization
Verification Theory, Systems and Applications Summer School. September 2013
Kim Larsen [28]
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Timed Automata: Example
guard
invariant
Verification Theory, Systems and Applications Summer School. September 2013
Kim Larsen [29]
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Example
a b
c
Is L1 reachable ?
Verification Theory, Systems and Applications Summer School. September 2013
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Example
x
y
a b
c
Verification Theory, Systems and Applications Summer School. September 2013
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Example
x
y
a b
c
Verification Theory, Systems and Applications Summer School. September 2013
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Example
x
y
a
a b
c
Verification Theory, Systems and Applications Summer School. September 2013
Kim Larsen [33]
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Example
x
y
a a
a b
c
Verification Theory, Systems and Applications Summer School. September 2013
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Networks Light Controller & User
Off Light Bright press? press?
press?
x:=0
x·3
x>3
x·100
x=100 x:=0
x·100
x=100 x:=0
x:=0
press? x:=0
Rest Busy
y¸10 y:=0
y·10
press!
press! y:=0
Transition
( Off, Rest, x=0, y=0 )
delay 20 ( Off, Rest, x=20, y=20 )
press?! ( Light, Busy, x=0, y=0 )
delay 2 ( Light, Busy, x=2, y=2)
press?! ( Bright, Rest, x=0, y=0)
Synchronization
x:=0
Verification Theory, Systems and Applications Summer School. September 2013
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Network Semantics
A X)s s ,,SS(T T 20
102121
X X
X X 2121
111
s ´ss s
´ss
X X ´s ss s
´ss
2121
222
X X ´s ´ss s
´ss ´ss aa
2121
222111
X X ´s ´ss s
´ss ´ss)d(e
)d(e)d(e
2121
222111
! ?
where
Verification Theory, Systems and Applications Summer School. September 2013
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Network Semantics (URGENT synchronization)
A X)s s ,,SS(T T 20
102121
X X
X X 2121
111
s ´ss s
´ss
X X ´s ss s
´ss
2121
222
X X ´s ´ss s
´ss ´ss aa
2121
222111
X X ´s ´ss s
´ss ´ss)d(e
)d(e)d(e
2121
222111
! ?
where
d’ < d, u UAct:
( s1 s2 ) e(d’) u! e(d’) u?
Verification Theory, Systems and Applications Summer School. September 2013
Kim Larsen [37]
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Light Control Interface
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Info
rmationste
knolo
gi
Light Control Interface
Control
Program
User
Interface
Light
endhold!
touch!
starthold!
press?
release?
press? d release? touch! 0.5·d· 1 press? 1 starthold! press? d release? endhold! d >1
press? 0.2 release? … press? 0.7 release? … press? 1.0 2.4 release? …
Ø touch! starthold! endhold!
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Info
rmationste
knolo
gi
Light Control Interface
Control Program
User
endhold!
touch!
starthold! press?
release?
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Info
rmationste
knolo
gi
Control Program
Light Control Network
endhold!
touch!
starthold! press?
release?
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Info
rmationste
knolo
gi
Full Light Controller
Dim
Dim
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Brick Sorting
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Info
rmationste
knolo
gi
LEGO Mindstorms/RCX
Sensors: temperature,
light, rotation, pressure.
Actuators: motors, lamps,
Virtual machine:
10 tasks, 4 timers, 16 integers.
Several Programming Languages:
NotQuiteC, Mindstorm, Robotics, legOS, etc.
3 input ports
3 output
ports
1 infra-red port
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Info
rmationste
knolo
gi
A Real Real Timed System
Controller Program
LEGO MINDSTORM
The Plant Conveyor Belt
& Bricks
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Info
rmationste
knolo
gi
First UPPAAL model Sorting of Lego Boxes
Conveyer Belt
Exercise: Design Controller so that black boxes are being pushed out
Boxes
Piston
Black
Red 9 18 81 90
99
Blck Yel
remove
eject
Controller
Ken Tindell
MAIN PUSH
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Info
rmationste
knolo
gi
NQC programs
task PUSH{
while(true){
wait(Timer(1)>DELAY && active==1);
active=0;
Rev(OUT_C,1);
Sleep(8);
Fwd(OUT_C,1);
Sleep(12);
Off(OUT_C);
}
}
int active;
int DELAY;
int LIGHT_LEVEL;
task MAIN{
DELAY=75;
LIGHT_LEVEL=35;
active=0;
Sensor(IN_1, IN_LIGHT);
Fwd(OUT_A,1);
Display(1);
start PUSH;
while(true){
wait(IN_1<=LIGHT_LEVEL);
ClearTimer(1);
active=1;
PlaySound(1);
wait(IN_1>LIGHT_LEVEL);
}
}
Verification Theory, Systems and
Applications Summer School. September 2013
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Info
rmationste
knolo
gi
A Black Brick
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Info
rmationste
knolo
gi
Control Tasks & Piston
GLOBAL DECLARATIONS:
const int ctime = 75;
int[0,1] active;
clock x, time;
chan eject, ok;
urgent chan blck, red, remove, go;
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Info
rmationste
knolo
gi
From RCX to UPPAAL – and back
Model includes Round-Robin Scheduler.
Compilation of RCX tasks into TA models.
Presented at ECRTS 2000 in Stockholm.
From UPPAAL to RCX: Martijn Hendriks.
Task MAIN
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Info
rmationste
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The Production Cell in LEGO
Course at DTU, Copenhagen
Production Cell Rasmus Crüger Lund
Simon Tune Riemanni
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UPPAAL
Modeling & Specification
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Train Crossing
River
Crossing
Gate
Stopable Area
[10,20]
[7,15]
[3,5]
list
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Train Crossing
River
Crossing
Gate
Stopable Area
[10,20]
[7,15]
list
[3,5] appr stop
leave
go
enqueue() dequeue() front()
id-”parameter”
Communication via channels!
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Declarations
Constants
Bounded integers
Channels
Clocks
Arrays
Types
Functions
Templates
Processes
Systems
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UPPAAL Help
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Logical Specifications
Validation Properties
Possibly: E<> P
Safety Properties
Invariant: A[] P
Pos. Inv.: E[] P
Liveness Properties
Eventually: A<> P
Leadsto: P Q
Bounded Liveness
Leads to within: P · t Q
The expressions P and Q must be type safe, side effect free, and evaluate to a boolean.
Only references to integer variables, constants, clocks,
and locations are allowed (and arrays of these).
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Case Studies: Controllers
Gearbox Controller [TACAS’98]
Bang & Olufsen Power Controller [RTPS’99,FTRTFT’2k]
SIDMAR Steel Production Plant [RTCSA’99, DSVV’2k]
Real-Time RCX Control-Programs [ECRTS’2k]
Terma, Verification of Memory Management for Radar (2001)
Scheduling Lacquer Production (2005)
Memory Arbiter Synthesis and Verification for a Radar Memory Interface Card [NJC’05]
Adapting the UPPAAL Model of a Distributed Lift System, 2007
Analyzing a χ model of a turntable system using Spin, CADP and Uppaal, 2006
Designing, Modelling and Verifying a Container Terminal System Using UPPAAL, 2008
Model-based system analysis using Chi and Uppaal: An industrial case study, 2008
Climate Controller for Pig Stables, 2008
Optimal and Robust Controller for Hydralic Pump, 2009
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Case Studies: Protocols
Philips Audio Protocol [HS’95, CAV’95, RTSS’95, CAV’96] Bounded Retransmission Protocol [TACAS’97] Bang & Olufsen Audio/Video Protocol [RTSS’97] TDMA Protocol [PRFTS’97] Lip-Synchronization Protocol [FMICS’97] ATM ABR Protocol [CAV’99] ABB Fieldbus Protocol [ECRTS’2k] IEEE 1394 Firewire Root Contention (2000) Distributed Agreement Protocol [Formats05] Leader Election for Mobile Ad Hoc Networks [Charme05]
Analysis of a protocol for dynamic configuration of IPv4 link local addresses using Uppaal, 2006
Formalizing SHIM6, a Proposed Internet Standard in UPPAAL, 2007
Verifying the distributed real-time network protocol RTnet using Uppaal, 2007
Analysis of the Zeroconf protocol using UPPAAL, 2009
Analysis of a Clock Synchronization Protocol for Wireless Sensor Networks, 2009
Model Checking the FlexRay Physical Layer Protocol, 2010
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Using UPPAAL as Back-end
Vooduu: verification of object-oriented designs using Uppaal, 2004
Moby/RT: A Tool for Specification and Verification of Real-Time Systems, 2000
Formalising the ARTS MPSOC Model in UPPAAL, 2007
Timed automata translator for Uppaal to PVS Component-Based Design and Analysis of Embedded
Systems with UPPAAL PORT, 2008 Verification of COMDES-II Systems Using UPPAAL with
Model Transformation, 2008 METAMOC: Modular WCET Analysis Using UPPAAL,
2010.
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www.uppaal.org
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LAB-Exercises www.cs.aau.dk/~kgl/Shanghai2013/exercises
Exercise 1 (Brick Sorter)
Excercise 19 (Train Crossing)
Exercise 2 (Coffee Machine)
Exercise 28 (Jobshop Scheduling)