VADC:Versatile Analog to Digital Converter

VADC:Versatile Analogto Digital ConverterXMC™ microcontrollersSeptember 2016

Agenda

Service request generation

Safety features

1

2

2Copyright © Infineon Technologies AG 2016. All rights reserved.

Agenda


Safety features

1

2


VADCVersatile Analog to Digital Converter

Highlights

The VADC is comprised of 4*independent analog to digitalconverters. Each, capable of convertingwith a resolution of 12-bits at 2MSamples/sec. This enables highlyaccurate signal measurement forcurrents, voltages, temperature signals.

*: depends on the specific device

Customer benefitsKey feature

› 3 flexible request sources (Queue,Scan, Background) for optimizedsequence

› Filtering, accumulation without CPUload. 8/10/12-bits results

› External triggering and gating ofconversions

› Flexible sequencing scheme

› Result post-processing

› Triggering and gating conversions


Group 3Group 2

Group 1Group 0

8:1

ch7

ch6

ch5

ch4

ch3

ch2

ch1

ch0

A/DSample

ARBITRATION

RESULTHANDLING

EVEN

TG

EN

ERATIO

N

SCANSOURCE

QUEUESOURCE

BCKGNDSOURCE

TRIG

GER

AN

DG

ATIN

G

VADCFlexible sequencing (1/2)

› 3 request sources allows a sophisticated sequencing

– Queue source up to 8 channels in 8 stages FIFO with anychannel combination possible

– Refill, source event generation and trigger can be configuredindividually for any entry in the queue


ReFill

Queue source

Trigger

ch3

ch5

ch0

ch1

none

none

ch1

none

InterruptChannelselection

VADCFlexible sequencing (2/2)

› Scan source up to 8channels. Convertsfrom higher numberselected until lowestchannel numberselected

› Background source ascan source that is ableto request conversionsin all channels in themicrocontroller. It istypically the lowestpriority source


Trigger

Scan

Backgroundsource

Channelselection

ch4

ch3

ch2

ch1

ch0

ch15

ch14

ch13

ch12

ch

ch

ch

ch

ch

ch

ch

ch

Scan

Scan source

Interrupt

Trigger

Channelselection

idle idlech7 ch4 ch3 ch2 ch1 ch1 ch2 ch1 ch5 ch4

Cancel-inject repeat

ch6ch7 ch3

TriggerScan

Trigger

scanTriggerqueue

Triggerbackground source

ch4

7

6

5

4

3

2

1

0

Interrupt

Trigger

VADCResult post-processing

› Up to 16 result registers per group (8 channels)

› Additional global result register accessible from any group in themicrocontroller

› A post-processing mechanism can execute filtering (FIRs, IIRs),differentiation, or accumulation without CPU interaction

› Wait for read mode blocks new writes in a result register beforethe content has been read by CPU or DMA for example, to avoidloss of data

› Result events signalize the existence of a new result to othermodules or the CPU


VADCTriggering and gating

› Conversion can be triggered by external events, continuously orby software events

› Full connectivity to other modules for application relevanttriggering-gating

› One signal can trigger different groups to allow simultaneoussampling

› A gating mechanism hinders the triggering of a conversion aslong as the gating signal is not released


VADCSystem integration

› Target applications

– Motor control

– Automation

– Power conversion

– General purpose

› The VADC is intelligently connected toother peripherals in the microcontroller,such as CCU8, DMA or NVIC fortriggering-gating on the input side andevent generation such as interruptevents on the output side

› This provides a perfect starting point forreal time applications where thehardware triggering of conversions orsignalization of events (i.e. overcurrent)have to happen in a deterministic waywith minimum time jitter

XMC™4200 XMC™4400XMC™4100

2 groups 2 groups 4 groups

XMC™4500

4 groups


CCU8

VADC

Trigger

Gating

Eventgeneration

CCU4

POSIF

DAC

LEDTS

VADC

ERUCCU8

CCU4

DMA

LEDTS

VADCERU

NVIC

GPIO

POSIF

Application exampleFast compare

Fast comparison of an analog voltagewith a threshold.

Fast compare mode generates a fastresult of a single bit. This bit indicates ifthe result is above or below a certainpre-programmed reference value. Somehysteresis (delta*) can be built aroundthis threshold in order to avoidoscillations.

*: availability of hysteresis feature in fastcompare depends on the specific device.

Overview

In brief

Fast Compare Mode


Application exampleLimit checker

Place some boundaries to create 3bands in the analog range in order tocontrol the result limits.

The limit checker permits the control ofan analog signal so that when the signalincreases or decreases above or belowsome configurable value, an event canbe triggered and an action can beexecuted.

As an example, a limit checker candetect an overvoltage and generate astop signal to a timer to avoid damageon the hardware.

Overview

In brief


Application exampleExternal multiplexers

VADC includes an external multiplexercontroller.

The EMUX controller is able to providethe selecting signals for an externalmultiplexer. This is synchronized tochannel conversion so when the EMUXchannel (CH3 in picture) is converted,the EMUX controller detects this andexecutes a configurable sequencing ofthe selected signals.

Overview

In brief


Application exampleBlanking time in real time applications

Gate a continuous running conversionwhen the information is not relevantfor the application.

Some signals might present oscillationsafter stepping to a different value.During this oscillation, the valuesampled by a continuous convertingVADC is not relevant and can be gatedthrough a timer (for example with astatus signal –ST) until the signal issettled.

Overview

In brief


Application exampleFIFO on high sampling rate applications

Use a FIFO structure to store results ina safe way.

Some applications require extreme fastconversions. On the other hand, the CPUload (control loop, for example) mightload the CPU in a way that can limit howfast the results of the VADC conversionsare read. In this cases, the VADC FIFOresult structure will help to conserveresults safely, avoiding overwriting,without having to force the CPU to reador slow down the converting rate.

Up to a 16 stages FIFO can be built bymeans of concatenating result registers.Data reduction mechanisms (filtering,accumulation) as well as eventgeneration is still valid and applicable.

Overview

In brief


Application exampleSynchronous conversions (1/2)

Sample several signals synchronously.

In many occasions, algorithms requestthe usage of several analog values thatare measured at the same time.

As an example, one could compute thepower, for example at a load, bymultiplying the current and voltage on it.This calculation would only make sensein case both signals were measured atthe exact same point in time.

XMC™4000 allows to measure 2 signalsin parallel. The master will request aconversion in its groups. This willautomatically lead the request of thesame channel number in the slave group.The rest of the VADC features can beused such as result handling, eventgeneration, limit check, etc.

Overview

In brief


Application exampleSynchronous conversions (2/2)

Synchronous conversions: possible sequencing


Slave groupQueue sourceMaster group

Rf Channel 3

Rf

Rf Channel 0Tr

Channel 3

Channel 4Channel 4

CCU8x

timer

VADCconversionsequence





TriggerTr

Tr

CR 2

CR 1


TrTr

TrTrigger


Channel 0

VADCService request generation (1/2)

› 3 different types of service requests can be generated:

– Request source event: channel converted in queue sourceor sequence finished in a scan source

– Channel event: indicates a channel conversion has finishedor in case of limit checker, indicates the corresponding event

– Result event: a new result is available

› The events can be linked to a NVIC node for code execution or toa signal for connectivity to other peripherals


VADCService request generation (2/2)

› 2 different kind ofrequest lines areavailable:

– Group specific are onlyaccessible from the groupwhere the event isgenerated. Backgroundsource events are notincluded here

– Common request lines.Can be accessed from anygroup and even from thebackground source events


VADC_G3VADC_G2

VADC_G1VADC_G0

SOURCEEVENTS

CHANNELEVENTS

RESULTEVENTS

Result 0

Result 1

Result 2

VADC_GLOBALGLOBALRESULTEVENT

GLOBRES

GLOBALSOURCEEVENT

VADC…

G0SR[0...3]

G3SR[0...3]

G1SR[0...3]

C0SR[0...3]

0

1

Channel 7

Queue Req.Source

Scan Req.Source

…

To

oth

er

peri

ph

era

lsChannel

Channel

Agenda


Safety features

1

2


VADCSafety features

› VADC offers a set of safety functionalities including:

– Broken wire detection for detecting the malfunction of a trace-wire

– Multiplexer diagnostics can test the existing connectionbetween pins and the internal converter input


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The information given in this training materials is given as a hint forthe implementation of the Infineon Technologies component only andshall not be regarded as any description or warranty of a certainfunctionality, condition or quality of the Infineon Technologiescomponent.

Infineon Technologies hereby disclaims any and all warranties andliabilities of any kind (including without limitation warranties of non-infringement of intellectual property rights of any third party) withrespect to any and all information given in this training material.

Disclaimer

VADC:Versatile Analog to Digital Converter

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