V2 - Advanced VHDL for FPGA - AC6- · PDF filemethodology with the best of VHDL for simulation...

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Formation Advanced VHDL for FPGA: Acquire a strong design methodology with the best of VHDL for simulation and synthesis - Programmation: Logique Programmable V2 - Advanced VHDL for FPGA Acquire a strong design methodology with the best of VHDL for simulation and synthesis Objectives Take the best of VHDL language for logical synthesis and simulation Implementing combinational and sequential logic Developing Finite State Machines Organizing the code developing package and libraries Reusing components Learning how to write efficient test benches for simulation Knowing the different writing style and their impact on the quality of synthesis results Checking Timings Synthesis and Place & Route results parameterizing Course environment A PC in pairs Xilinx ISE Design Suite v.14.7 IDE / Xilinx Vivado v.2013.4 IDE Nexys-3 (Xilinx Spartan6-based) board / Nexys-4 (Xilinx Artix7-based) board Prerequisites Knowledge of digital technology Basic knowledge of the VHDL language Plan First day Reminders Entity, architecture and process, Library use (IEEE) Elaboration Constants, signals Scalar Types Predefined operators Type conversion, conversion functions Qualified Expressions

Transcript of V2 - Advanced VHDL for FPGA - AC6- · PDF filemethodology with the best of VHDL for simulation...

Page 1: V2 - Advanced VHDL for FPGA - AC6- · PDF filemethodology with the best of VHDL for simulation and synthesis - ... V2 - Advanced VHDL for FPGA ... Procedures Functions

Formation Advanced VHDL for FPGA: Acquire a strong designmethodology with the best of VHDL for simulation and synthesis -

Programmation: Logique Programmable

V2 - Advanced VHDL for FPGA

Acquire a strong design methodology with the best of VHDL for simulationand synthesis

Objectives

Take the best of VHDL language for logical synthesis and simulationImplementing combinational and sequential logicDeveloping Finite State MachinesOrganizing the code developing package and librariesReusing componentsLearning how to write efficient test benches for simulationKnowing the different writing style and their impact on the quality of synthesis resultsChecking TimingsSynthesis and Place & Route results parameterizing

Course environment

A PC in pairsXilinx ISE Design Suite v.14.7 IDE / Xilinx Vivado v.2013.4 IDENexys-3 (Xilinx Spartan6-based) board / Nexys-4 (Xilinx Artix7-based) board

Prerequisites

Knowledge of digital technologyBasic knowledge of the VHDL language

Plan

First day

Reminders

Entity, architecture and process, Library use (IEEE)ElaborationConstants, signalsScalar TypesPredefined operatorsType conversion, conversion functionsQualified Expressions

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V2 - Advanced VHDL for FPGA 04/20/18

AggregatesSequential Statements

If, Case, Loop StatementsBest practices of efficient coding

Exercice :  Designing a 4-bit adder

Hardware design methodology for logical synthesis

Synthesizing combinational and sequential logicComposite Data types and Operations

ArraysUnconstrained Array typesArray operations and ReferencingRecords

AliasesPredefined and Standard PackagesDrivers and resolution functionsMultiple Drivers and TristatesHandling 'X' on the inputsAttributes

Attributes of Scalar Types and Array TypesAttributes of Signals

Guard and BlocksSynchronous designs

Use of variables in clocked processesEdge detectionSynchronizing reset signalsModeling Memories

Exercice :  Designing a BCD-counter/decounter

Second day

Asynchronous design

Asynchronous designs and classic tricksMetastability and operational hazardsWhy avoid asynchronous sequential processes

InputsTiming ConstraintsFeedbacks: Transparent Latch, Combinational loopCoping with latency and Out-of-Order completionGenerating random numbers

Synchronization and communication between clock domainsExercice :  Metastability and clock domains

Configuring, checking and Improving Synthesis results

Checking SSOSynthesis, Map and Place & Route results Analysis

FPGA utilizationTiming Analysis, Critical path

Synthesis and Place & Route parameterizingTiming optimizationArea optimization

Pipeline notion and implementationUseful predefined attributes in logical synthesis

Exercice :  Improving possible frequency for a simple design

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V2 - Advanced VHDL for FPGA 04/20/18

The state machines

Mealy and Moore machinesGraphic representationsImplementationVHDL translation

Design principles of an FSM with two processesReset of a state machine

Exercice :  Designing a burstable RAM controller

Third day

Testbenches and simulation

Functional and behavioral simulation (with delays)The VITAL Library

VHDL instructions specific to simulation“Wait” and its various formsDelay insertion, “after”“Now”“Simulation Loop”Test vector generationStrings, to_string() operatorAssertionsReportsTiming verification, Measuring Delay

Potential incoherencies between logical synthesis and simulation : how to avoid itIntegration of « pseudo logic » to facilitate the analysis of simulation results

Exercice :  Designing and testing a logical address decoderResolved signalsExternal Names, Monitoring internal signalsForce and Release AssignmentsSubprograms

ProceduresFunctionsOverloadingVisibility of Declarations

Access TypesLinked Data structuresShared Variable and Protected types

Exercice :  Developing subprograms to simulateFile accesses

Files declarationsOpen/Close operationsTEXTIO packageWriting and reading of ASCII filesAllocation of a data flow from a file / Test vector generationStorage of the simulation results in a file

Exercice :  Enhancing the test bench to read the test vectors in a file and to save the results in another

Fourth day

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V2 - Advanced VHDL for FPGA 04/20/18

Advanced VHDL features for optimization and code reuse in logical synthesis

Hierarchical divisionPackage and Use Clause

Package DeclarationsPackage BodiesUse ClausesContext Declarations and Use

LibrariesExercice :  Creating Package and Libraries and working with them

Genericity and automatic configuration of re-usable modulesGeneric Constants, Generic Types, Generic ListsGeneric Subprograms, Generic Packages

Exercice :  Enhancing a 4-bit BCD-counter/decounter to create a generic oneComponents and Configurations

ComponentsConfiguring components instancesDirect instantiationBasic configurationsMultiple levels Configuration

Exercice :  Working with configurationsGenerate statements

Generating Iterative StructuresConditionally Generating StructuresConfiguration of Generate statement

Concurrent instructions “for generate “Exercice :  Designing a n digits BCD-counter/decounter and displaying it on a 7-segment display

Renseignements pratiques

Durée : 4 joursPrix : 1950 € HT

Prochaines sessions : du 5 au 8 juin 2018

SARL au capital de 138600 € - SIRET 449 597 103 00026 - RCS Nanterre - NAF 722C - Centre de Formation : 19, rue Pierre Curie - 92400 Courbevoie

Siège social et administration : 21, rue Pierre Curie - 92400 Courbevoie - Tél. 01 41 16 80 10 - Fax. 01 41 16 07 78

Dernière mise à jour du site: Fri Apr 20 10:16:31 2018http://www.ac6-formation.com/

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