Register Layer Modeling

AgendaWhy RALFeatures/AdvantagesRAL ComponentsTypes of PredictionProperties of uvm_reg_field

Why RAL?Generic DUTRole of a verification Engineer:Check for controllability and observability ofAccess PathAccess policyReset values

The usual Process (Not the UVM way)Example:Write Transaction:Write CommandRegister AddressData

Read Transaction:Read CommandRegister Address

AXI IntAXI UVCInterface LayerRegister LayerAbstract Register Tests and Sequences(Independent of Protocol)ConversionExample:Write in Register0Data

Read from Register0AXI Sequence Items

Features/Advantages No implementation details requiredProtocol independent (Deals only with registers)Register sequences stay abstract and same irrespective of interfaces (AXI, APB, AHB etc..)Address independent

Another ExampleRegister LayerInterface LayerWrite Register0Data yyy;AXI TransactionAddress X; Data yyyDirection AXI_write

RAL componentsAdapter: Converts register transactions to bus transactions and vice-versa.PredictorRegister Model: Mimic of DUT registers

Adapter exampleclass reg2bus extends uvm_reg_adapter; virtual function uvm_sequence_item r2b (const ref uvm_reg_bus_op rw); write_xtn ramtr; ramtr = write_xtn::type_id::create (ramtr, this); ramtr.write = (rw == UVM_WRITE) ? 1 : 0; ramtr.address = rw.address; return ramtr; endfunction endclass

Reg Map ExampleClass reg_block extends uvm_reg_block; `uvm_object_utils(reg_block) Rand reg1 R1;... uvm_reg_map reg_map; Function void build(); ... reg_map = create_map( .name("reg_map"), .base_addr('h100), .n_bytes(8), // BUS WIDTH .endian(UVM_LITTLE_ENDIAN), .byte_addressing(1) ); endfunctionendclass

Register ModelRegister FieldMemoryRegister MapNOTE: Register Block Contains all the above components

Register Model AutomationIPXACT (xml)UVM Register PackageRegister Model Generation Tool

Predictor Gets information from the monitorConverts bus transaction to register transaction using the adapterAdapterRegister MapBus transactionPredictorAddrdataregregister_transaction

Types of PredictionControlled in the connect phase of the environment.Auto Prediction Predictor is absent. Register model is updated at the end of frontdoor read and write operation.Fails to update the register models for non-register transactionsExplicit PredictionThe predictor receives bus transactions at the end of the front door read and write cyclesAdvantage: Can keep track of register changes even for sequences other than register sequences

Properties of uvm_reg_fieldm_reset - Stores the reset valuem_mirrored Stores a copy of the DUT register valuem_desired Stores the value that needs to be written into the DUT registerNOTE: All the above properties are local.

Methodsreset() - resets the values of all register fieldsset() - sets the desired value of a register field (in the m_desired field)get() - get the value of m_desired propertyget_mirrored_value() - retrieves the value of m_mirrored propertywrite() - writes a value to the DUTread() - reads a DUT register

update() - Internally calls write method when m_mirrored and m_desired are unequal. Argument to write method is m_desired value mirror() - Only returns the value of the DUT register to m_mirrored propertyAlso compares the read value against the desired value if the check argument is UVM_CHECK.

Connection: RAL and Sequencer class ram_tb extends uvm_env; //Handles for register block, adapter and predictor function void build_phase (uvm_phase phase); //Create register block, adapter and predictor endfunction Contd...

function void connect_phase(uvm_phase phase); block.map.set_sequencer(path of physical sequencer); predictor.map = path_of_map; Predictor.adapter = path_of_adapter;endfunction endclass

Backdoor and Frontdoor AccessBackdoor access: Register model uses hdl paths which are used by simulator database to peek and poke the hardware signals corresponding to registers0 simulation time

Memory Sequence Exampleclass ram_manual_seq extends uvm_reg_seq; //Instantiate Register Model task body(); reg_model.reg.write(status, 'hff, .path(UVM_FRONTDOOR), .parent(this)); reg_model.reg.read(status, data); endtaskendclass