Using Victory Process to Create Realistic Structures for ... · PDF fileduring realistic...

13
Volume 26, Number 3, July, August, September 2016 Engineered Excellence A Journal for Process and Device Engineers Using Victory Process to Create Realistic Structures for Capacitance Extraction in Clever 1. Introduction Silvaco offers many alternatives for creating simple 3D structures, the optimum choice depending on what the user needs to simulate. Many of the choices for creating simple 3D structures are for user convenience, so that just a single tool can both create the simple 3D structure and simulate the required physics. This gives the user an enhanced feeling of a tightly integrated product. However, when realistic and curved 3D shapes are necessary, the complexity of the code required for their creation and subsequent meshing, necessitates that for efficiency sake, there is only one structure building interface. The idea being that there is only one complex 3D structure creator for realistic process simulation, and that this complex structure is then imported into the appropriate tool for device or back end simulations. To this end, when realistic process simulation is required to create a complex 3D structure, Victory Process will be used as the universal interface tool. In this article, we demonstrate how to interface realistic 3D structures created using Victory Process, with the back end parasitic extraction tool, called Clever. Clever uses a field solver operating on 3D structures to calculate both the parasitic resistance and capacitance of the interconnect lines within the structure. If the 3D structure is “Manhattan” in nature (all features within the 3D structure are “square sided”), then Clever’s internal 3D builder is sufficient. However, when realistic processing features are required, then the enhanced capability of Victory Process becomes necessary. 2. Complex Structure Creation Options within Victory Process Within Victory Process, there are two methodologies for creating realistic structures, namely “Cell” mode and “Process” mode. In technical terms, “Cell” mode utilizes an explicit structure mesh at all stages of structure creation, whereas “Process” mode uses a level set methodology, which separately tracks the location of moving boundaries during realistic etching and oxidation steps. The advantage of the level set method (Process Mode) is greatly enhanced numerical stability when tracking moving interfaces during realistic etch and oxidation process steps. The disadvantage of Process Mode is primarily simulation speed and structure file sizes. In practical terms, use “Process” Mode if realistic and complex etching or oxidation is required to create the structure, but use “Cell” Mode for any other structure where geometric etching or oxidation steps will suffice. 3. An Example Using Victory Process in “Cell” Mode Since both Process Mode and Cell Mode have realistic photolithography modules, and angled etches are covered under the geometric etching module, it is possible to make surprisingly realistic structures using the Cell mode 3D Process Simulator. As an example, we shall create an SRAM cell, using the physics based photolithography simulator to create realistic photoresist development INSIDE Simulation of Device Degradation Due to Bias Temperature Stress ........................................... 5 Hints and Tips ........................................................... 9 Continued on page 2 ...

Transcript of Using Victory Process to Create Realistic Structures for ... · PDF fileduring realistic...

Page 1: Using Victory Process to Create Realistic Structures for ... · PDF fileduring realistic etching and oxidation steps. The advantage ... The lo- cal spacial ... To briefly review the

July, August, September 2016 Page 1 The Simulation StandardVolume 26, Number 3, July, August, September 2016

Engineered Excellence A Journal for Process and Device Engineers

Using Victory Process to Create Realistic Structures for Capacitance Extraction in Clever

1. IntroductionSilvaco offers many alternatives for creating simple 3D structures, the optimum choice depending on what the user needs to simulate. Many of the choices for creating simple 3D structures are for user convenience, so that just a single tool can both create the simple 3D structure and simulate the required physics. This gives the user an enhanced feeling of a tightly integrated product.

However, when realistic and curved 3D shapes are necessary, the complexity of the code required for their creation and subsequent meshing, necessitates that for efficiency sake, there is only one structure building interface. The idea being that there is only one complex 3D structure creator for realistic process simulation, and that this complex structure is then imported into the appropriate tool for device or back end simulations.

To this end, when realistic process simulation is required to create a complex 3D structure, Victory Process will be used as the universal interface tool.

In this article, we demonstrate how to interface realistic 3D structures created using Victory Process, with the back end parasitic extraction tool, called Clever. Clever uses a field solver operating on 3D structures to calculate both the parasitic resistance and capacitance of the interconnect lines within the structure. If the 3D structure is “Manhattan” in nature (all features within the 3D structure are “square sided”), then Clever’s internal 3D builder is sufficient. However, when realistic processing features are required, then the enhanced capability of Victory Process becomes necessary.

2. Complex Structure Creation Options within Victory ProcessWithin Victory Process, there are two methodologies for creating realistic structures, namely “Cell” mode and “Process” mode.

In technical terms, “Cell” mode utilizes an explicit structure mesh at all stages of structure creation, whereas “Process” mode uses a level set methodology, which separately tracks the location of moving boundaries during realistic etching and oxidation steps. The advantage of the level set method (Process Mode) is greatly enhanced numerical stability when tracking moving interfaces during realistic etch and oxidation process steps. The disadvantage of Process Mode is primarily simulation speed and structure file sizes.

In practical terms, use “Process” Mode if realistic and complex etching or oxidation is required to create the structure, but use “Cell” Mode for any other structure where geometric etching or oxidation steps will suffice.

3. An Example Using Victory Process in “Cell” ModeSince both Process Mode and Cell Mode have realistic photolithography modules, and angled etches are covered under the geometric etching module, it is possible to make surprisingly realistic structures using the Cell mode 3D Process Simulator. As an example, we shall create an SRAM cell, using the physics based photolithography simulator to create realistic photoresist development

INSIDE

Simulation of Device Degradation Due to Bias Temperature Stress ...........................................5Hints and Tips ........................................................... 9

Continued on page 2 ...

Page 2: Using Victory Process to Create Realistic Structures for ... · PDF fileduring realistic etching and oxidation steps. The advantage ... The lo- cal spacial ... To briefly review the

The Simulation Standard Page 2 July, August, September 2016

mask patterns, together with the geometrical angled etch engine to emulate the sloped sides of a dry etch machine. The final structure is shown in Figure 1.

The photolithography steps are carried out in 3 stages. Firstly the optical properties of the mask aligner or stepper are defined, in terms of the wavelength of the optical source, the effective aperture of the focussing lens and the elevation of the focused image in reference to the top level of the photoresist.

Once the optical properties of the stepper have been de-fined, a physics based optical solver is invoked to cal-culate local photoresist exposure intensities. When the mask is exposed to the light source, an optical intensity pattern is created. The spacial optical intensity pattern will approximately vary between full intensity exposure

in the middle of large clear areas of the mask, and near zero intensity in large opaque areas of the mask. The lo-cal spacial intensity is represented by a coefficient that varies between zero and unity to represent these two ex-tremes of photoresist exposure intensity. Near the edges of mask patterns, a contoured map of the spacial variance in intensity coefficient is formed as a result of diffraction and interference patterns. An example of a spacial inten-sity coefficient pattern is shown in Figure 2, in this case it is the spacial intensity pattern resulting from exposure to the gate mask, shown on the left.

After the photoresist exposure stage, the third stage is pattern development. In order to emulate variances in photoresist development conditions, e.g. over or under exposure time, bake times, development solution con-centration etc., the user can choose the level of exposure which will define the final photoresist contour. Figure 3 shows the final etch shape after development of the pho-toresist at a development threshold of a 40% (0.4) reduc-tion relative to maximum exposure.

Figure 1. An SRAM cell created using realistic photolithography and angle etched side walls, in Victory Process “Cell” Mode operation.

Figure 2. A gate mask and it’s resulting intensity coefficient map during photoresist exposure in the stepper.

Figure 3. Final photoresist mask shape after photolithography simulation.

Page 3: Using Victory Process to Create Realistic Structures for ... · PDF fileduring realistic etching and oxidation steps. The advantage ... The lo- cal spacial ... To briefly review the

July, August, September 2016 Page 3 The Simulation Standard

Now the new mask shape after photolithography simulation has been defined, the angled etch of the polysilicon gate layer can proceed. A typical etch angle of 87 degrees from horizontal was used to produce the final polysilicon gate layer shown in Figure 4.

Using the process steps described above, a realistic and complex cell can be created, as shown back in Figure 1. Once we have the structure, it can be loaded back into Clever for interconnect resistance and capacitance field solving to obtain the resistance and capacitance parasit-ics, which are then back annotated onto the extracted ac-tive Spice netlist, also extracted by Clever. The few and simple syntax lines required for the complete RC parasit-ic calculations and automated back annotation are shown in Figure 5.

To briefly review the extraction and back annotation syn-tax, the active netlist is extracted in the “init” statement, by loading of the layout and rule files (clex17_0.lay and clex17.lmp respectively) and the Victory Process created structure (clex17.str) is also loaded. The two “Material” statement lines define some properties of the materials in the structure, which can be changed from their default

values. The “GateOx” material is assigned an un-phys-ically low value of relative permittivity (0.01) in order to remove this gate capacitance from the net list, since this capacitance is already taken care of in the Spice model card of the active devices. Finally, all parasitic RC calculations and automated back annotation onto the active Spice net list, are taken care of by the “Intercon-nect” statement, which requests 5% accuracy for both resistance and capacitance calculations. The new netlist (active with parasitics) is saved into a Spice file called “clex17_1.net”.

In summary, therefore, the steps are as follows:

1. Start Clever to create additional virtual masks required for process simulation

2. Create the structure using Victory Process

3. Load the structure back into Clever to perform interconnect parasitic resistance and capacitance calculations which are automatically back annotated onto the active Spice net list also extracted by Clever.

4. An Example Using Victory Process in “Process” ModeThe preceding example showed that complex and realistic looking structures can be constructed using just the geometric features of “Cell” mode operation in the Victory Process 3D simulator. In cases where geometric operations are not sufficient for structure creation, such as where physical oxidation or reactive ion etching (RIE) are necessary, then the “Process Mode” operation of the Victory Process simulator has to be used.

The following example will show how to simulate a common processing issue, usually described as the “Mi-cro-loading Effect” which is an annoying reality when etching small but varying feature sizes. To summarize, the effect describes an apparent etch rate dependence on the feature size of the masked layer being etched. Small-er apertures having a lower etch rate than slightly larger features. For this and other reasons, it is common for the size of via holes for example, to be fixed for each layer. In other words, the etch has only been optimized for this one size of hole for each layer. The results are not guar-anteed for any other size. If you need a via for a higher current device, one simply has to use more of these fixed sized vias, in order to guarantee that the etch will yield for that layer.

Basically the procedure involves defining the type of etch machine, using the “TopographyModel” statement, and if it is a dry etch machine, as it is in this case, we then define the angular dependent properties of the plasma etch machine using the “Flux” definition statement.

Figure 4. Polysilicon gate layer after photolithography simulation and an angled etch of 87 degrees.

Figure 5. Syntax for RC Parasitic extraction and automatic back annotation.

Page 4: Using Victory Process to Create Realistic Structures for ... · PDF fileduring realistic etching and oxidation steps. The advantage ... The lo- cal spacial ... To briefly review the

The Simulation Standard Page 4 July, August, September 2016

In this example, the angular dependence of flux was described as having a Gaussian form. For a given angular distribution of flux, there can be different etch rates for each material exposed to the plasma, so the maximum vertical etch rates for each material are then defined on the EtchDepoProperties” statement.

Now the plasma etch machine has been fully described, all that remains to be done, is to expose our masked wafer to the virtual etch machine for a fixed period of time. This is performed by the “Etch” statement.

To demonstrate the micro-loading effect, three trenches of differing sizes were defined by creating a hard etch mask and simple geometric etches. The width of the “L” shaped trench patterns was 1um, 0.5um and 0.25um, as shown in Figure 6.

After exposure to the etch machine for 4 minutes, effective width dependent etch rates were observed. These trenches were then filled with aluminum to make observation of the trench depth dependence on trench width, easier to visualize. The final structure is shown in Figure 7 with the surrounding material made transparent so that the internal shape of the etched trenches becomes apparent.

To make the etch depth dependence on trench width even clearer, a 2D cutline through the structure shown in figure 7 is shown in figure 8. In exactly the same way as in the “Cell” mode example, this structure can be loaded into Clever and the full capacitance matrix between the metal lines extracted.

The details of the etch machine syntax will not be gone into here, as the structure above is now one of Silvaco’s standard Clever examples, and can be examined on our web page, or through the DeckBuild interface.

5. ConclusionsWe have shown that any structure that can be created in Silvaco’s 3D Victory Process simulator can be loaded into Clever for capacitance and resistance extraction, either with or without active net list extraction. This feature greatly adds to the versatility of this already versatile tool.

Figure 6. The hard mask pattern before exposure to the etch machine.

Figure 7. 3D trenches modeled with a dry etch machine, clearly showing etch depth dependence on mask trench width.

Figure 8. A 2D cut line through the structure shown in Figure 7, showing a clear etch depth dependence on trench width.

Page 5: Using Victory Process to Create Realistic Structures for ... · PDF fileduring realistic etching and oxidation steps. The advantage ... The lo- cal spacial ... To briefly review the

July, August, September 2016 Page 5 The Simulation Standard

IntroductionBias Temperature Instability (BTI) [1] ranks among the most serious reliability issues in present-day semiconductor devices. In pMOSFETs, for instance, it is observed when large negative biases are applied to the gate at elevated temperatures. These operation conditions cause a shift of the threshold voltage, resulting in an unwanted change of the device characteristics. With the continuous miniaturization of MOS devices, this phenomenon has become increasingly pronounced and has reached a level, at which it can even lead to device failure in the worst case.

In the past, BTI was associated with various different physical mechanisms, including the prominent reaction-diffusion model [2]. During the last couple of years however, experimental evidence has accumulated which confirms that charge trapping is responsible for the recoverable component of BTI. This trapping mechanism cannot be described by some kind of elastic tunneling, which is inherently temperature independent as opposed to BTI. However, hole trapping could be traced back to a temperature dependent process called multiphonon field-assisted tunneling (MPFAT). During such a process, the defect must be thermally excited first so that it can capture or emit a charge carrier followed by structural relaxation. The MPFAT process can explain the temperature and gate bias dependence of BTI and is the key component of the two-stage degradation model, implemented in the Silvaco TCAD tool Atlas. This model is a powerful tool for analyzing BTI on large-area devices, in which numerous defects are present. During the last couple of years however, a new measurement technique called time-dependent defect spectroscopy (TDDS) has provided insight into the detailed physics of the charge capture and emission processes of a single defect [3]. Using this method, the BTI trapping mechanism has been identified as a nonradiative multiphonon (NMP) process, which also forms the basis of the four-state NMP model. This new model can explain the single-defect measurements of TDDS but also the degradation data of large-area devices [4]. While the model was first developed for negative BTI in pMOSFETs, it has recently been shown to explain all four degradation modes, i.e. negative BTI and positive BTI in n-channel and p-channel MOS transistors [5].

The Four-State NMP ModelAs mentioned before, the key component of this model are the NMP processes, illustrated in Figure 1. The energy of the neutral and the positive defect are shown as a function of the defect configuration q and have parabolic shapes in the harmonic approximation. During an NMP process, the defect must be first thermally excited up to the intersection point (IP) at the top of the NMP barrier. There, the defect can capture or emit a charge carrier since the defect energy is conserved while the charge is transferred. The NMP barrier is the cause for a marked temperature dependence, also observed in BTI experiments for example.

The above NMP processes are incorporated in the four-state NMP model, as depicted in the state diagram of Figure 2. The model is based on a set of four states, denoted as 1, 1’, 2, and 2’. The defect is assumed to be neutral in the states 1 and 1’ and positively charged in the states 2 and 2’. The states 1 and 2 are stable while the other states are metastable and marked by a prime (1’, 2’). The transitions 1 2’ and 1’ 2 represent NMP processes, the actual hole capture or emission events in the four-state NMP model. Since they involve metastable states, these NMP processes are always preceded or followed by defect deformations. The latter are independent of the local electric field and correspond to the transitions 1 1’ and 2 2’.

Simulation of Device Degradation Due to Bias Temperature Stress

Figure 1. Schematic illustration of an NMP process. Two defect energy curves are plotted for the case that the charge carrier to be trapped is either still located in the substrate or already captured in the defect. E1 (neutral, blue line) at q1 and E2 (positive, red line) at q2 denote the minima of the curves. During an NMP process, the defect has to thermally overcome the energy barrier over the intersection point. It is also mentioned that a change of the gate bias can lead to a upwards shift of the curve E1(q) and a lowering of the transition barrier (see dashed curve). This results in an increase of the hole capture rates, giving rise to a strong gate bias dependence, which is typical for BTI.

Page 6: Using Victory Process to Create Realistic Structures for ... · PDF fileduring realistic etching and oxidation steps. The advantage ... The lo- cal spacial ... To briefly review the

The Simulation Standard Page 6 July, August, September 2016

Even though several different transition pathways are possible in the state diagram of Figure 2, the whole charge capture or emission processes occur between the stable states 1 and 2 as two-step transitions. For instance, the whole hole capture process is usually described by a transition that starts from state 1, proceeds over state 2’, and ends up in state 2. During hole emission, the defect goes from state 2 to state 1 via either of metastable states 1’ or 2’. The different transition pathways can explain the behavior of the switching and the fixed oxide traps, respectively: The former are characterized by gate-bias dependent emission times and are described by a transition over the metastable state 1’ in the state diagram. By contrast, the fixed oxide traps take the pathway over the metastable state 2’ and have emission times that are insensitive to the gate bias. The aforementioned four states describe the recoverable

component of the BTI phenomenon and therefore build the core of the four-state NMP model. However, the experimental data also suggest the existence of a permanent (or slowly recovering) component. It has been linked to the generation of interface charges. However, the involved reactants have not been specified within this model. As such, the reaction can also be ascribed to the depassivation of Pb centers, which leaves behind a positively charged Si dangling bond. In contrast to the RD model, the degradation of the permanent component is not dominated by the dynamics of the hydrogen diffusion but by the kinetics of the interface reaction. This interface reaction is modeled by a double-well model with two stable states A and B (see Figure 3). The state A corresponds to a neutral interface defect and is energetically favorable compared to the positive interface defect in state B (in the absence of a large oxide field). However, an increase in the local electric field F lowers the energy barrier towards state B and thereby initiates a transition into state B.

Figure 2. State diagram of the multi-state model. The defects are stable in a neutral (1) and a positive (2) charge.state, where each of them has a metastable counterpart marked by a prime (1’,2’). The NMP transitions 1 2’ and 1’ 2 take place between different charge states. By contrast, the defect deformations 1 1’ and 2 2’ occur between same charge states. It is stressed that the metastable states (1’,2’) are of particular importance as they strongly affect the gate-bias and temperature dependence of the overall transitions 1 2.

Figure 3. Schematic illustration of the interface reaction. If a bias is applied to the gate, the oxide field lowers the energy barrier, thereby initiating a transition from the state A to state B.

Figure 4. Measured (symbols) and simulated (lines) capture and emission times of the fixed (top) and the switching (bottom) oxide trap. The good agreement with the experimental data show that the four-state NMP model captures the essential physics behind the charge capture/emission in BTI. Quite impressively, it can also give an explanation for both the fixed and the switching oxide traps.

Page 7: Using Victory Process to Create Realistic Structures for ... · PDF fileduring realistic etching and oxidation steps. The advantage ... The lo- cal spacial ... To briefly review the

July, August, September 2016 Page 7 The Simulation Standard

The recoverable and the permanent component are both caused by traps, whose properties vary from defect to defect in amorphous gate oxides, such as a-SiO2 and SiON. These variations lead to a wide range of transition times for the charge capture/emission processes and the interface reactions. A multitude of such traps allows for the long-lasting degradation and recovery curves seen in BTI experiments. It is emphasized that the degradation behavior of a device is therefore caused by the distributions of the defects properties.

Capture and Emission Time PlotsSince the four-state NMP model has to be consistent with the single-defect data of TDDS, the ATLAS implementa-tion has first been evaluated against the data extracted from Ref. [3]. The simulated device was a simple planar p-channel MOS transistor with a plasma-nitrided oxide (EOT = 2.2 nm). As the defect parameters are assumed to be distributed in the four-state NMP model, they had to be calibrated against the experimental data. The calibra-tion procedure was carried out for the data of the fixed and the switching oxide hole traps, depicted in Figure 4. It has been found that the simulation results agree well with the experimental capture and emission time con-stants for different gate biases and temperatures. This implies that the temperature dependence of the capture and emission time constants are well described by the thermal activation of the NMP processes. The model can also account for the different behavior of the fixed and the switching oxide traps (cf. Figure 4) – a fact that has only been achieved by the four-state NMP model so far. On the whole, the above evaluation against the TDDS data confirms that the four-state NMP model covers the essential physics of the hole capture and emission pro-cesses involved in the BTI degradation.

Degradation DataIn this section the four-state NMP model is evaluated against the experimental long-term relaxation data, extracted from Ref. [4]. The measurements therein were carried out on of a p-channel MOS transistor with a 2.2 nm thick SiON gate oxide. For the following simulation study, the corresponding device structure was created using the Silvaco TCAD tool Victory Process (see Figure 5). It is mentioned that the generated mesh of the simulated device was highly refined in the oxide region between the substrate and the gate using the Silvaco TCAD tool DevEdit. The high resolution was required in order to account for the strong depth dependence of the charge trapping, which is inherent to every oxide trap model.

The device simulations included the last of several subsequent stress/relaxation cycles with the stress times of about 104 s and relaxation times of about 105. The selected dataset covers the three different stress biases (VG = −1.7/ − 2.7/ − 3.2 V) and two different temperatures (T = 125/170oC). This combination is suited to validate the four-state NMP model and in particular its oxide field and temperature dependence. For the given operation conditions, the relaxation curves were obtained by using transient simulations that cover the stress and the subsequent relaxation phase. In each of these simulations, the initial time step was set to a small value of 10−10 s in order to capture the fast degradation, which can even extend below the microsecond regime. At several times during the relaxation phase, structure files were stored using the SAVE statement. These files were later used to read in the trapped charges for calculation of the transfer characteristics and the extraction of the threshold voltages. This procedure was also used to determine the threshold voltage of the unstressed device, which is required for the calculation of the shift of threshold voltage.

Due to the computational costs, the numerous traps present in a large-area devices must be represented by a small number of stimulated traps. The parameters of the latter were assumed to follow a Gaussian distribution, however, the parameters of a single trap are still random values. Therefore, the number of representative traps was chosen sufficiently large so that their single contributions averaged out. In this study, the number of traps simulated was set to be 30 at each node.

The values of the trap parameters were specified using the syntax of the following TRAP statement:

1 TRAP material=SiO2 \ 2 subcontact=Silicon gatecontact=Aluminum \ 3 x.min=-0.05 x.max=+0.05 \ 4 y.min=-0.0015 y.max=-0.000 \ 5 nmp4.sto nmp4.samples=30 \ 6 density=6.379e+19 \

Figure 5. The device structure used for the calibration of the four-state NMP model.

Page 8: Using Victory Process to Create Realistic Structures for ... · PDF fileduring realistic etching and oxidation steps. The advantage ... The lo- cal spacial ... To briefly review the

The Simulation Standard Page 8 July, August, September 2016

7 sign=3.684e-13 sigp=3.684e-13 \ 8 nmp4.et1=3.760 nmp4.et1.sd=-0.257 \ 9 nmp4.s12s=2.431 nmp4.s12s.sd=-1.033 \10 nmp4.r12s=1.960 nmp4.r12s.sd=0.394 \11 nmp4.et2=5.263 nmp4.et2.sd=0.150 \12 nmp4.s1s2=2.250 nmp4.s1s2.sd=1.001 \13 nmp4.r1s2=1.175 nmp4.r1s2.sd=0.144 \14 nmp4.nu=1e13 \13 nmp4.epsT2s=0.319 nmp4.epsT2s.sd=-0.494 \14 nmp4.eps2s2=0.209 nmp4.eps2s2.sd=-0.178 \15 nmp4.eps1s1=3.000 nmp4.eps1s1.sd=0.000 \16 nmp4.nit=9.494e+09 nmp4.nup=1e+13 \17 nmp4.Ea=1.906 nmp4.Ea.sd=0.132 \18 nmp4.Ed=0.277 nmp4.Ed.sd=0.000 \19 nmp4.gamma=4.988e-08

The four-state NMP model was enabled by the flag nmp4.sto. The density of the oxide and interface traps were set by the parameter density and nmp4.nit, respectively. Furthermore, the oxide traps were placed within the insulator region that is defined by the material material=SiO2 and surrounded by the lines x.min, s.max, y.min, and s.max. The parameters subcontact and gatecontact specify the regions with which the oxide traps can exchange charge carriers via electron or hole trapping. The lines 6-15 of the above TRAP statement specify the parameters of the oxide traps while the parameters of the interface reaction are given in the lines 16-19. Most of these parameters are assumed to follow either a uniform or a Gaussian distribution and are therefore specified by their mean values and distribution widths. The latter has the ending .sd and must be set to a positive or negative value for a uniform or a normal distribution, respectively. Regarding the meaning of the parameter set, the reader is referred to the Atlas manual [7].

For the calibration of the model parameters, the Silvaco TCAD tool Virtual Wafer Fab (VWF) was chosen. It provides the Levenberg-Marquardt algorithm, which is a robust and established method to solve non-linear least square problems. As shown in Figure 6, the obtained simulation results agree well with the experimental data for all operation conditions. This demonstrates that the four-state NMP model explains the gate bias as well as the temperature dependence of the experimental data and is therefore suited to investigate the BTI degradation.

SummaryThe Atlas package of Silvaco provides several degradation models, including the reaction-diffusion model and the two-stage model. This list of models has been extended now by the four-state NMP model, which was developed based on the physical insights from TDDS measurements and tested against the degradation data of several different device technologies. The TDDS simulations have demonstrated that the four-state NMP model covers the essential physics of the charge capture and emission process involved in BTI. Furthermore, the model has been validated by a fit to an experimental dataset including different gate biases and operation temperatures. Since the model accurately has reproduced the important characteristics of BTI, in particular the gate bias and the temperature dependence, it provides a good alternative to the existing degradation models implemented in the Silvaco TCAD tool Atlas.

References[1] Schroder, D. et al., “Negative Bias Temperature Instability:

Road to Cross in Deep Submicron Silicon Semiconductor Manufacturing”, J.Appl.Phys., vol. 94, no. 1, 1-8, (2003).

[2] Alam, M. et al., “A Comprehensive Model of pMOS NBTI Degradation”, Microelectronics Reliability, vol. 45, no. 1, 71-81, (2005).

[3] Grasser, T. et al., “The Time-Dependent Defect Spectroscopy (TDDS) for the Characterization of Bias Temperature Instability”, Proceedings of the International Reliability Physics Symposium (IRPS), 2A.2.1-2A.2.10, (2010).

[4] Rzepa, G. et al., “Physical Modeling of NBTI: From Individual Defects to Devices”, Proceedings of the 20th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 81-84, (2014).

[5] Rzepa, G. et al., “Complete Extraction of Defect Bands Responsible for Instabilities in n and pFinFETs”, 2016 Symposium on VLSI Technology Digest of Technical Papers, 208-209, (2016).

[6] Waltl, M. et al., “A Single-Trap Study of PBTI in SiON nMOS Transistors: Similarities and Differences to the NBTI/pMOS Case”, Proceedings of the International Reliability Physics Symposium (IRPS), XT.18.1-XT.18.5, (2014).

[7] Atlas User’s Manual, Device Simulation Software, SIlvaco, Inc., Santa Clara, CA 95054.

Figure 6. The simulated (lines) and measured (symbols)relaxation data for four different operation conditions. The good match with the experimental data shows that the four-state NMP model is a good choice for investigating the BTI degradation. It is noted that the simulations do not only account for charge trapping with the substrate but also with the gate contact.

Page 9: Using Victory Process to Create Realistic Structures for ... · PDF fileduring realistic etching and oxidation steps. The advantage ... The lo- cal spacial ... To briefly review the

July, August, September 2016 Page 9 The Simulation Standard

Hints, Tips and SolutionsQ: How to examine the scattering mechanisms that are contributing to the reduced channel mobility in 4H-SiC MOSFETs?

In a MOSFET structure, silicon carbide, 4H-SiC in particular, is known to exhibit lower channel mobility than Si, mainly due to Coulomb scattering at trapped charge at the SiO2/4H-SiC interface, where a high interface trap density exists. Atlas provides an alternative inversion layer mobility model specifically intended for 4H-SiC. The model enabled by specifying the ALTCVT.N parameter for electrons or the ALTCVT.P parameter for holes on the MOBILITY statement takes into account four scattering mechanisms. These comprise the ionized impurity scattering in the bulk semiconductor, the surface roughness scattering, the acoustic surface phonon scattering, and the Coulomb scattering at trapped charge at the SiO2/4H-SiC interface. Using Matthiessen’s rule, the ALTCVT.N and ALTCVT.P model combines four mobility components related to their respective carrier scattering to form the total inversion layer mobility in 4H-SiC.

The bulk mobility component cannot be explicitly excluded from the ALTCVT.N and ALTCVT.P model, but a judicious choice of parameters will force it to be constant.

The surface roughness contribution is enabled by default, and can be disabled by clearing the flags ALT.SR.N or ALT.SR.P on the MOBILITY statement, e.g., MOBILITY ALTCVT.N ^ALT.SR.N

The surface phonon contribution is enabled by default, and can be disabled by clearing the flags ALT.SP.N or ALT.SP.P on the MOBILITY statement, e.g., MOBILITY ALTCVT.N ^ALT.SP.N

The Coulomb scattering mobility is automatically enabled for the ALTCVT.N and ALTCVT.P model. It can be disabled for electrons by setting the flag COULOMB.N on the MOBILITY statement or for holes by setting the flag COULOMB.P on the MOBILITY statement, e.g., MOBILITY ALTCVT.N ^COULOMB.N

The contributions of each of the four mobility components to the total channel mobility can be examined by simulating drain current (ID) versus gate voltage (VG) at a fixed drain voltage (VD).

Figure 1 shows a simple n-channel 4H-SiC MOSFET, along with acceptor and donor state density distributions in the band gap at the SiO2/4H-SiC interface as a function of energy referenced from the valence band edge. Based on this MOSFET structure, while VG is being swept from 0 to 10V at VD=0.1V, the electron mobility and the perpendicular electric field are extracted at the SiO2/4H-SiC interface in the middle of the channel region with

Figure 1. A 4H-SiC n-channel MOSFET (left) with density of interface traps at the interface between 4HSiC and SiO2 (right).

Page 10: Using Victory Process to Create Realistic Structures for ... · PDF fileduring realistic etching and oxidation steps. The advantage ... The lo- cal spacial ... To briefly review the

The Simulation Standard Page 10 July, August, September 2016

Call for QuestionsIf you have hints, tips, solutions or questions to contribute,

please contact our Applications and Support Department Phone: +1 (408) 567-1000 Fax: +1 (408) 496-6080

e-mail: [email protected]

Hints, Tips and Solutions ArchiveCheck out our Web Page to see more details of this example

plus an archive of previous Hints, Tips, and Solutions www.silvaco.com

Figure 3. Variation of electron mobility profile across the device (left) and along the channel depth (right) in the high electric field regime (VG=10V and VD=0.1V).

Figure 2. Electron mobility in an n-channel MOSFET as a function of perpendicular electric field.

the help of PROBE statements. Figure 2 illustrates the electron mobility mechanisms in the channel as a function of electric field perpendicular to the SiO2/4H-SiC interface. From this it follows that at low electric fields the total inversion layer mobility is substantially dominated by Coulomb scattering at interface charges and at moderate electric fields by surface phonon scattering. Surface roughness scattering becomes dominant only at high electric fields, which can also be seen clearly from a schematic plot of the channel depth dependence of electron mobility at VG=10V and VD=0.1V (Figure 3).

Page 11: Using Victory Process to Create Realistic Structures for ... · PDF fileduring realistic etching and oxidation steps. The advantage ... The lo- cal spacial ... To briefly review the

July, August, September 2016 Page 11 The Simulation Standard

Hints, Tips and Solutions

Figure 1. Traditional way of showing vectors in a 2D model: the arrows are plotted for every grid point.

Figure 2. The TonyPlot windows allowing to control the display of vector arrows.

(a)

(b)

Figure 3. Vectors in TonyPlot with the ‘Use Linear Interpolation’ option and ‘Grid’ set to 20 by 20.

Q: How to better visualize vectors and field lines in TonyPlot?

Traditionally, visualizing vectors by means of arrows in TonyPlot was a challenge, especially in the areas where the computational grid was dense. The vector arrows were plotted for every grid point, making them in many cases very hard to discern. One such example is illustrat-ed in Figure 1.

A new, improved capability: since April 2016 (TonyPlot version 3.10.6.R or later) a new capability has been available which gives user much more control over the number, density and size of the vector arrows being displayed in TonyPlot. Here is how you can make the vectors sparser for easier viewing:

- in the ‘Tonyplot: Display’ window, select ‘Define > Vectors...’ (Figure 2a);

- in the ‘TonyPlot: Vectors’ window, check ‘Use Linear Interpolation’, then set Grid: ... Apply (Figure 2b).

An example of such improved display of vector arrows in TonyPlot, with the ‘Use Linear Interpolation’ option activated and the ‘Grid’ set to 20 by 20, is shown in Figure 3.

Page 12: Using Victory Process to Create Realistic Structures for ... · PDF fileduring realistic etching and oxidation steps. The advantage ... The lo- cal spacial ... To briefly review the

The Simulation Standard Page 12 July, August, September 2016

Call for QuestionsIf you have hints, tips, solutions or questions to contribute,

please contact our Applications and Support Department Phone: +1 (408) 567-1000 Fax: +1 (408) 496-6080

e-mail: [email protected]

Hints, Tips and Solutions ArchiveCheck out our Web Page to see more details of this example

plus an archive of previous Hints, Tips, and Solutions www.silvaco.com

Figure 4. Tonyplot visualization of the electric field lines and the ionization integral values along each line.

Viewing the Electric Field Lines Within the Depletion RegionThis capability is often important when analyzing impact ionization and avalanche breakdown phenomena.

First, for such analysis, it is often useful to display the depletion region boundaries:

- in the ‘TonyPlot: Display’ window (Figure 2a) , select ‘Define > Junctions...’

- in the ‘Tonyplot: Junctions’ window, click on ‘Depletion Edges’ ... Apply.

In order to visualize the electric field lines (and ionization integral) in the depletion region:

- in your input deck, use a statement like this:

output impact e.lines iname=anode n.lines=50

- once the simulation is completed and you open the resulting .str file in Tonyplot, activate (click on) ‘Lines’ in ‘Tonyplot: Display’ window,

- you may turn off ‘Contours’ and ‘Regions’ in ‘Tony-plot: Display’ , for a clearer view of the field lines and the ionization integral values (represented by colors).

An example of electric filed lines displayed in such a manner is presented in Figure 4.

NOTE: the structure used in this article was based on the Silvaco standard example: OPTOELECTRONICS - Example 19: Cylindrical Avalanche Photodiode (optoex19.in).

Page 13: Using Victory Process to Create Realistic Structures for ... · PDF fileduring realistic etching and oxidation steps. The advantage ... The lo- cal spacial ... To briefly review the

July, August, September 2016 Page 13 The Simulation Standard

Worldwide Offices: Silvaco Japan [email protected]

Silvaco [email protected]

Silvaco [email protected]

Silvaco [email protected]

Silvaco [email protected]

USA Headquarters:

Silvaco, Inc.4701 Patrick Henry Drive, Bldg. 2Santa Clara, CA 95054 USA

Phone: 408-567-1000Fax: 408-496-6080

[email protected]