Using ADS to Ensure Signal Integrity on Multi-Gigabit ... 1 Ludwig Eichinger Agilent EEsof EDA Using...
Transcript of Using ADS to Ensure Signal Integrity on Multi-Gigabit ... 1 Ludwig Eichinger Agilent EEsof EDA Using...
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Ludwig Eichinger
Agilent EEsof EDA
Using ADS to Ensure
Signal Integrity on
Multi-Gigabit Serial Links
ADS Seminar Nov/Dec 2009
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Agenda: Signal Integrity Simulations Using
Advanced Design System
• Introduction
• Concept – System Design – Verification
• Channel Simulation Technologies and Methods
• Cannel Modeling in Frequency Domain
• Integration and Verification
• Demo and Advanced Design Techniques
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Typical SI Problem ( Ensuring Signal Quality and Timing)
Pattern
Generator
Pre-emphasis/Driver
Encoder
Decoder
Receiver
Equalizer
Physic
al C
hannel
Board Traces 2” (51mm) – 10” (254mm)
Card
Card
Package
Die
Package
Die Driver
Receiver
Card
High speed Connectors
Backplane Traces
10” (254mm) –
40” (1016mm)
Physic
al C
hannel
Channel Adaptation
Signal Recovery
IBIS or Spice model
IBIS or Spice model
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Signal Degradation• Low pass filter characteristic of transmission line (attenuates high
frequency component in a signal which results in smearing out sharp
edges)
• Radiation, dispersion, resonance, and frequency dependent losses
of transmission lines degrades wave shape
• Interference caused by cross talk ( coupling between adjacent
transmission lines) and EMI degrades wave shape
• Impedance mismatch due to transmission line discontinuities
• High frequency parasitic, delays, and asymmetric transmission path
• Through Hole Vias
Basic microwave problem
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How ADS can help to overcome SI Effects?
Better control of impedance, mismatch & discontinuities in the transmission path
• Better isolation between transmission lines reduces cross talk
• Tight control of power and ground plane impedance
Signal processing techniques to reduce signal distortion ( ISI)
• Pre-emphasis (Transmitter side)• Boost high frequency components in a digital signal to compensate for low pass filtering effects of transmission lines
• Equalization (Receive side) CTE , FFE, DFE
• Boost high frequency components in a digital signal to compensate low pass filtering effects of transmission lines and dispersion effects
• Controlled attenuation of low frequency component to make frequency domain response flat over the frequency and dispersion effects
Simulation of extremely low BER.
Account for different types of jitter: ISI, DCD, PJ & RJ
Tx and Rx equalizers
Effects of crosstalk channels
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Tx Driver BoardPackage Backplane
ADS supports all implementation domains (IC, Module, Board)
ADS can analyze the full digital channel – data-in to data-out
Integrated data models and simulation technology
High Speed Digital Channel DesignExpands SI Horizon - Simulate Complete Channel
BoardEncoder, Serializer
Decoder,
De-serializerPackage Receiver
DSP DSPAnalog Simulation Model from EM-Simulation
Measurement from NWA
Analog
High Frequency Signal
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Tx Driver
Channel Source - Differential or Single Ended
Bit Rate
Vlow/Vhigh
Rise/Fall Time
Register Length (i.e. 2^19)
Encoder (8B10B)
Preemphasis
De-Deemphasis
Jitter
DCD, RJ, PJAmplitude, PJFrequency
Fast Channel Modeling – Source Tx
Encoder, Serializer
DSP Analog
ADS Channel Source
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Fast Channel Simulation – Rx
Decoder,
De-serializerReceiver
DSPAnalog
Support three type of equalizations
Continous-time linear equalizer (CTE): pole-zero
Feed-forword equalizer (FFE)
Decison-feedback equalizer (DFE)
Optimize the initial taps automatically with innovative algorithm
Accept user specified taps through dialogue or tap file
Adapt taps with LMS, RLS or ZF algorithm during the simulation
Save the optimized taps on file
Account for RJ
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BoardPackage Backplane
Modeling of Package, Motherboard, Connectors
Analytical Models (very fast)
3D planar Models (Momentum, 3D-planar Simulator)
FEM, 3D full wave Simulator
FDTD, 3D full wave Simulator
S-Parameter form NWA or PLTS
Channel Modeling – Traces – Vias – Package –
Motherboard – Backplane - Connectors
Board Package
Simulation Model from EM-Simulation
Measurement from NWA
High Frequency Signal
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Fast Channel Channel Modeling:
Flexible Representation of Interconnects
S-parameters
Inbuilt Multilayer Interconnect library
W-element
Physical models (EM)
Measurement based
Rational Polynomials
Pole zero
Lumped representation (Broadband SPICE)
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Eye diagram
S-parameters
from VNA
FFT
HDMI cable (7 meters):
Measured (pink) and simulated
(blue) response correspond exactly
Fast Channel Modeling:
Data Based Model from a Network Analyzer
Fast Eye Measurements - User Interface
The Eye probes will be available from Transient and Channel Simulator Palette.The Eye probes is available from Transient and Channel Simulator Palette.
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Fast Eye Mask Definition
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Use Model
1. Browse for the mask file* from the Eye Probe dialog.
2. Activate the Eye Mask Viewer dialog by clicking on the
View/Edit button from the Eye Probe
3. The contents of the mask file should be plotted for
verification prior to simulation.
4. Click on the Edit button to edit the contents of the mask
file. The refresh button can be used to update the mask
plot.
1
2 4
3
Eye Mask Display
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The simulator will save the Eye
Mask for each Eye Probe.
In addition if the user requests for
mask violation checks to be
performed, the simulator will
check for violations and report
using 1 or 0 in the variable named
“MaskViolated”.
How to improve the Channel Quality?
•Channel Simulation, includes Traces, Vias, Connectors, Package, etc.
• Simulation Methods
• TDR/TDT
•Mixed Mode S-Parameters
•Cross Talk Analysis
TDR Simulation
Mixed Mode S-Parameter
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Step 1: Design of input and output Matching
NetworksSource Impedance is 100 Ohm
Impedance of the Package at input and output is 88.7 Ohm
Solution Design of a Matching Network
Smith Chart UtilityS11dd
mismatch
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Step 2: Fast Channel Optimization
Optimization of the intermediate traces (w, s) and de-emphasis in the Source
Matching Network
Matching Network
Optimizer
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Comparison before and
after Optimization
Eye Height Jrms Jpp
Before Optimization, without Matching Network
192 10.5psec 40.8psec
With matching Network before optimization
311 4.4psec 22psec
With matching, after optimization
316 3.18psec 15.9psec
Improvement Factor ofEye Height = 1.64Jrms = 3.3Jpp = 2.57
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Fast Channel Simulation - Cross Talk Analysis
Degradation Factorthrough Cross TalkEye Height = 1.05 lessJrms = 1.3 moreJpp = 1.3 moreWith Cross Talk
Without Cross Talk
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Tx Driver
Channel Verification – Source Tx
Encoder, Serializer
DSP Analog • Inbuilt transistor models
• HSPICE netlist
• Spectre netlists
• Verilog-A
• Verilog-D cosim
• Verilog-AMS cosim
• Verilog/VHDL cosim
• MATLAB cosim
• C/C++/SystemC
• IBIS buffers
• IBIS AMI
• ADS Design Kit from Altera,
Xilinx, etc.
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Design Verification: Design Flow Integration
with Other EDA Tools
Allegro®
Expedition®
ADS/Momentum
BBSPICE
HSPICE/PSPICE
Allegro® import
Expedition® import
Broadband SPICE
Import critical nets from Cadence
Allegro or Mentor Expedition
environment to ADS for Momentum
simulation
Export Momentum results to
HSPICE
Links ADS and Momentum to external tools
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Cadence Allegro or Mentor Design Flow Integration
with ADS
Allegro PCB or Expedition PCB
Design Environment Advanced Design System design
and simulation environment
Cadence or Mentor
Channel Modeling: 3D EM tools from
Agilent
• The ONLY company with ALL 3 EM technologies
• Momentum (Method of Moments) 3D Planar
• EMDS (Finite Element Method) Full 3D In ADS and EMPro
• EMPro (Finite Difference Time Domain) Full 3D
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EM Based Models:
Momentum- 3-D Planar EM SimulationFrequency domain analysis of arbitrary shaped geometry
• Via hole
• Planar Package and board
• Transitions and launch
• Connectors
• Arbitrary shaped transmission
lines and discontinuity
• SI and PI analysis
EM Based Models: EMPro 3D Full Wave EM - FEM
and FDTD
•3D Package
•High Speed Connectors
• SATA, HDMI, PCI
express, USB3,
SAS2, XAUI
•Conformal High Speed
Flex Circuits
Simulated Data
•S-Parameter
•Electric fields
•Multi-Mode Data
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Fast Channel Simulation - Layout Co-Simulation
Package Model
Package Model
Add in Card
Here we are performing EM co-simulation on the
add in card traces
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Simulation, Post Processing and Data
RepresentationAutomated measurements
• Eye diagram
• Jitter analysis
• TDR/TDT
• Mixed Mode (Diff/Com)
Links with Test and
Measurement Instruments
• Essential for measurement-
based modeling
Bathtub/BER analysis
ADS model created from
TDR response
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Equalization Rx (FFE, DFE)
Optimize the initial taps automatically with innovative algorithm
Accept user specified taps through dialogue or tap file
Adapt taps with LMS, RLS or ZF algorithm
during the simulation
Save the optimized taps on file
Support three type of equalizations
Continous-time linear equalizer (CTE): pole-zero
Feed-forword equalizer (FFE)
Decison-feedback equalizer (DFE)
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Broadband SPICE Model Generator
Input File Format
• ADS dataset
• Citifile format
• Touchstone file format
• Momentum RAT
Output Netlist Format
• ADS
• SPICE2
• SPICE3
Fast and Efficient way to convert S-parameter
models to their SPICE equivalent
PCI-Express Design Guide
Allow easy setup and simulation
of a PCI Express Channel
Provides
– Easy simulation setup
– Representative channel components
– Allow you to quickly predict the effect of your design on the system performance
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More Design Guides
PCIe
DDR2
DDR3
USB
HDMI
These Design Guides needs to be installed in
Main Window/DesignGuide/Add DesignGuide
Navigate to $HPSSOSF_DIR\examples\ KC_examples and select PCI_Express etc.
Other Examples
Signal Integrity Applications (In the Design Guide Menu)
Examples in $HPSSOSF_DIR\examples\ SignalIntegrity
http://www.agilent.com/find/eesof click on Signal Integrity and then on
Quick Start for Signal Integrity Design Using Agilent ADS
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Summary - ADS Usage
• Compute the geometry of the differential traces on and between the layers to
achieve the desired differential Impedance
• Channel Simulation, including Vias, Connectors, Package
• Simulation Methods
• TDR/TDT
• Cross Talk Analysis
• Mixed Mode S-Parameters
• Eye, Jitter, BER, Statistics, Cross Talk
• Comparison with measurement
• De-embedding techniques is ADS
• Design Improvements
• Matching Networks
• Optimization of Analog circuit
• System Simulation including Analog Cannel and DSP circuits
•Optimization of Analog and DSP circuit
• Equalization Techniques (LFE, DFE, Blind DFE, etc.)
• Pre-, De-emphasis
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– SPICE tools are not sufficient to model high speed Serial
Link Channel
– Designer requires accurate time domain simulation of S-
parameters (ADS provides far superior time-domain
simulation technology)
– Designer needs to integrate DSP components such as
SERDES, Pre-emphasis and Equalization. ( ADS provide
industry best co-simulation technology and can simulate a
channel containing a combination of Analog, DSP, MATLAB,
EM, C++, and HDL components)
– Jitter analysis is very important for success of the product
– Accurate analysis of BER is important for 1st pass success.
Summary