USER GUIDE FOR IR3898 EVALUATION BOARD 1IRDC3898-P1V2 12/8/2011 1 USER GUIDE FOR IR3898 EVALUATION...
Transcript of USER GUIDE FOR IR3898 EVALUATION BOARD 1IRDC3898-P1V2 12/8/2011 1 USER GUIDE FOR IR3898 EVALUATION...
-
IRDC3898-P1V2
12/8/20111
USER GUIDE FOR IR3898 EVALUATION BOARD1.2Vout
DESCRIPTION
The IR3898 is a synchronous buckconverter, providing a compact, highperformance and flexible solution in a small4mm X 5 mm Power QFN package.
Key features offered by the IR3898 includeinternal Digital Soft Start/Soft Stop, precision0.5Vreference voltage, Power Good,thermal protection, programmable switchingfrequency, Enable input, input under-voltagelockout for proper start-up, enhanced line/load regulation with feed forward, externalfrequency synchronization with smoothclocking, internal LDO and pre-bias start-up.
Output over-current protection function isimplemented by sensing the voltage developedacross the on-resistance of the synchronousMosfet for optimum cost and performance andthe current limit is thermally compensated.
This user guide contains the schematic and billof materials for the IR3898 evaluation board.The guide describes operation and use of theevaluation board itself. Detailed applicationinformation for IR3898 is available in theIR3898 data sheet.
BOARD FEATURES
• Vin = +12V (+ 13.2V Max)•Vout = +1.2V @ 0- 6A
• Fs=600kHz
• L= 1.0uH
• Cin= 3x10uF (ceramic 1206) + 1X330uF (electrolytic)
• Cout=4x22uF (ceramic 0805)
SupIRBuckTM
-
IRDC3898-P1V2
12/8/20112
A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum of 6A load should beconnected to VOUT+ and VOUT-. The inputs and output connections of the board are listed in Table I.
IR3898 has only one input supply and internal LDO generates Vcc from Vin. If operation with external Vccis required, then R15 can be removed and external Vcc can be applied between Vcc+ and Vcc- pins. Vin pinand Vcc/LDO_Out pins should be shorted together for external Vcc operation.
The output can track voltage at the Vp pin. For this purpose, Vref pin is to be connected to ground (use zeroohm resistor for R21). The value of R14 and R28 can be selected to provide the desired tracking ratiobetween output voltage and the tracking input.
CONNECTIONS and OPERATING INSTRUCTIONS
LAYOUT
The PCB is a 4-layer board (2.23”x2”) using FR4 material. All layers use 2 Oz. copper. The PCBthickness is 0.062”. The IR3898 and other major power components are mounted on the top side of theboard.
Power supply decoupling capacitors, the bootstrap capacitor and feedback components are locatedclose to IR3898. The feedback resistors are connected to the output at the point of regulation and arelocated close to the SupIRBuck IC. To improve efficiency, the circuit board is designed to minimize thelength of the on-board power ground current path.
Table I. Connections
Connection Signal Name
VIN+ Vin (+12V)
VIN- Ground of Vin
Vout+ Vout(+1.2V)
Vout- Ground for Vout
Vcc+ Vcc/ LDO_Out Pin
Vcc- Ground for Vcc input
Enable Enable
PGood Power Good Signal
AGnd Analog ground
-
IRDC3898-P1V2
12/8/20113
Connection Diagram Vin Gnd Gnd Vout
Enable
VDDQ
Vref
Sync
S-CtrlAGnd
PGood Vsns Vcc+ Vcc-
Top View
Bottom View
Fig. 1: Connection Diagram of IR3899/98/97 Evaluation Boards
-
IRDC3898-P1V2
12/8/20114
Fig. 2: Board Layout-Top Layer
Fig. 3: Board Layout-Bottom Layer
Single point connection between AGnd and PGnd
-
IRDC3898-P1V2
12/8/20115
Fig. 5: Board Layout-Mid Layer 2
Fig. 4: Board Layout-Mid Layer 1
-
IRDC3898-P1V2
12/8/20116
Fig.
6:Sc
hem
atic
ofth
eIR
3898
eval
uatio
nbo
ard
-
IRDC3898-P1V2
12/8/20117
Bill of Materials
Item Qty Part Reference Value Description Manufacturer Part Number
1 1 C1 330uFSMD Electrolytic F size 25V
20% Panasonic EEV-FK1E331P
2 3 C3 C4 C5 10uF1206, 25V, X5R, 20%
TDK C3216X5R1E106M
3 4 C7 C12 C14 C24 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01B
4 1 C8 2200pF 0603,50V,X7R Murata GRM188R71H222KA01B
5 1 C11 180pF0603, 50V, NP0, 5% Murata GRM1885C1H181JA01D
6 4 C15 C16 C17 C18 22uF0805, 6.3V, X5R, 20%
TDK C2012X5R0J226M
7 1 C23 2.2uF0603, 16V, X5R, 20%
TDK C1608X5R1C225M
8 1 C26 10nF0603, 25V, X7R, 10%
Murata GRM188R71E103KA01J
9 1 C32 1.0uF0603, 25V, X5R, 10%
Murata GRM188R61E105KA12D
10 1 L1 1.0uH SMD 7.1x6.5x5mm,4.7mΩ TDK SPM6550T-1R0
11 1 R1 2KThick Film, 0603,1/10W,1%
Panasonic ERJ-3EKF2001V
12 2 R2 R11 3.32KThick Film, 0603,1/10W,1%
Panasonic ERJ-3EKF3321V
13 2 R3 R12 2.37KThick Film, 0603,1/10W,1%
Panasonic ERJ-3EKF2371V
14 1 R4 100Thick Film, 0603,1/10W,1%
Panasonic ERJ-3EKF1000V
15 1 R6 20Thick Film, 0603,1/10W,1%
Panasonic ERJ-3EKF20R0V
16 1 R9 39.2KThick Film, 0603,1/10W,1%
Panasonic ERJ-3EKF3922V
17 5 R10 R13 R14 R15 R50 0Thick Film, 0603,1/10W
Panasonic ERJ-3GEY0R00V
18 2 R17 R18 49.9KThick Film, 0603,1/10W,1%
Panasonic ERJ-3EKF4992V
19 1 R19 7.5KThick Film, 0603,1/10W,1%
Panasonic ERJ-3EKF7501V
20 1 U1 IR3898 PQFN 4x5mm IR IR3898MPBF
-
IRDC3898-P1V2
12/8/20118
TYPICAL OPERATING WAVEFORMSVin=12.0V, Vo=1.2V, Io=0-6A, Room Temperature, no airflow
Fig. 10: Output Voltage Ripple, 6A load Ch2: Vout
Fig. 11: Inductor node at 6A loadCh3:LX
Fig. 8: Start up at 6A Load, Ch1:Vin, Ch2:Vo, Ch3:Vcc, Ch4:PGood
Fig. 7: Start up at 6A LoadCh1:Vin, Ch2:Vo, Ch3:PGood Ch4:Enable
Fig. 9: Start up with 1V Pre Bias , 0A Load, Ch2:Vo
Fig. 12: Short circuit (Hiccup) RecoveryCh2:Vout , Ch4:Iout
-
IRDC3898-P1V2
12/8/20119
TYPICAL OPERATING WAVEFORMSVin=12.0V, Vo=1.2V, Io=0-6A, Room Temperature, no air flow
Fig. 13: Transient Response, 3A to 6A stepCh2:Vout Ch4-Iout
-
IRDC3898-P1V2
12/8/201110
TYPICAL OPERATING WAVEFORMSVin=12.0V, Vo=1.2V, Io=0-6A, Room Temperature, no air flow
Fig. 14: Bode Plot at 6A load shows a bandwidth of 110.8KHz and phase margin of 50.5 degrees
-
IRDC3898-P1V2
12/8/201111
TYPICAL OPERATING WAVEFORMSVin=12.0V, Vo=1.2V, Io=0-6A, Room Temperature, no air flow
Fig (16) Feed Forward for Vin change from 7 to 16V and back to 7V Ch2-Vout Ch4-Vin
Fig (15) Soft start and soft stop using S_Ctrl pin
-
IRDC3898-P1V2
12/8/201112
Fig.18: Power loss versus load current
Fig.17: Efficiency versus load current
TYPICAL OPERATING WAVEFORMSVin=12.0V, Vo=1.2V, Io=0-6A, Room Temperature, no air flow
81
82
83
84
85
86
87
88
89
90
0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6Iout(A)
Effic
ienc
y(%
)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6Iout(A)
PDis
sipa
tion(
W)
-
IRDC3898-P1V2
12/8/201113
THERMAL IMAGESVin=12.0V, Vo=1.2V, Io=0-6A, Room Temperature, No Air flow
Fig. 19: Thermal Image of the board at 6A loadTest point 1 is IR3898Test point 2 is inductor
-
IRDC3898-P1V2
12/8/201114
PCB METAL AND COMPONENT PLACEMENTEvaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self-centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self-centering on specific processes. For further information, please refer to “SupIRBuck™ Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting Application Note.” (AN1132)
Figure 20: PCB Metal Pad Spacing (all dimensions in mm)
-
IRDC3898-P1V2
12/8/201115
SOLDER RESIST
IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.)However, for the smaller Signal type leads around the edge of the device, IR recommends thatthese are Non Solder Mask Defined or Copper Defined. When using NSMD pads,
the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm oneach edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer tolayer misalignment. Ensure that the solder resist in-between the smaller signal lead areas are atleast 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip.
Figure 21: Solder resist
-
IRDC3898-P1V2
12/8/201116
STENCIL DESIGN
Figure 22: Stencil Pad Spacing (all dimensions in mm)
Stencils for PQFN can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). Stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with theground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm-0.200mm
(0.005-0.008"), with suitable reductions, give the best results. Evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. This design is for a stencil thickness of 0.127mm (0.005").The reduction should be adjusted for stencils of other thicknesses.
-
IRDC3898-P1V2
12/8/201117
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105TAC Fax: (310) 252-7903
This product has been designed and qualified for the Industrial marketVisit us at www.irf.com for sales contact information
Data and specifications subject to change without notice.12/11
PACKAGE INFORMATION
Figure 23: Package Dimensions