USB PHY on FPGA - strokov.org · wire[3:0] comb_out = reg_b < 10 ? reg_b + 1 : 0; reg[3:0] reg_a;...
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USB PHY on FPGA
Transcript of USB PHY on FPGA - strokov.org · wire[3:0] comb_out = reg_b < 10 ? reg_b + 1 : 0; reg[3:0] reg_a;...
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USB PHY on FPGA
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1. Снифферыa. Логические анализаторы: Saleae, Dreamsource, etc.b. https://www.totalphase.com/products/beagle-usb12/c. http://openvizsla.org/d. MAX3421 + https://github.com/Xarlan/usbsniffe. Beaglebone +
https://beagleboard.org/p/drinkcat-myopenid-com/usb-sniffer-ba62d22. Прокси
a. Beaglebone-like usb proxy (https://github.com/dominicgs/USBProxy)b. Custom FPGA proxyc. Atmega + https://github.com/matlo/serialusb
3. Fuzzing/badUSB, etc.a. http://goodfet.sourceforge.net/hardware/facedancer21/b. Other MCU/MAX4321…
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Start Of Frame transaction
D-
D+
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IN+NAK transaction
D-
D+
1=host->device0=device->host
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IN+DATA transaction
D-
D+
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OUT/SETUP transaction
D-
D+
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module(in x1, in x2, out S, out P);
assign P = x1 & x2;assign S = (x1 | x2) & (~P);
endmodule
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wire[3:0] comb_out = reg_b < 10 ? reg_b + 1 : 0;
reg[3:0] reg_a;reg[3:0] reg_b;
always @(posedge clk) beginreg_b <= reg_a;reg_a <= comb_out;
end
reg[3:0] reg_a;reg[3:0] reg_b;
always @(posedge clk) beginif(reg_b < 10) reg_a <= reg_b + 1;else reg_a <= 0;
reg_b <= reg_a;end
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reg[3:0] reg_a;reg[3:0] reg_b;
always @(posedge clk) beginreg_b <= reg_a;reg_a <= reg_b;
end
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Ссылки● https://github.com/qanper/usbproxy● https://www.devalias.net/devalias/2018/05/13/usb-reverse-engineering-down-t
he-rabbit-hole/● https://www.beyondlogic.org/usbnutshell/usb1.shtml● http://www.cypress.com/documentation/application-notes/an57294-usb-101-in
troduction-universal-serial-bus-20
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thx
Andrew Strokov
@aanper
https://t.me/shitsch
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