USB 3.2 PHY and Link Spec€¦ · 12/02/2019 · •PHY design reuse is a high priority –both...

USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017

USB 3.2 PHY and Link SpecHoward Heck– PHY WG ChairHuimin Chen – Link WG Chair

(Sponsored by Intel Corporation)

USB Developer Days 2017

Taipei, Taiwan

October 24 – 25, 2017

1

Welcoming Slideshow 1.ppsx

Welcoming Slideshow 1.ppsx


USB 3.2 Goals – Recap • Doubling the BW with two lane bonding on Type C

• Focus on PHY/link layer with minimal impact to other layers• PHY design reuse is a high priority – both Gen1 (5Gbps) and Gen2 (10Gbps)

supported

• Just works with existing software (OS/drivers)

• Maintaining parity with regard to USB 3.1 performance• BER• Channel loss budget• Link power efficiency

• Preserving scalability for technology extensibility

• Retimer/active cable friendly


Introduction

3

Scope x2 operation

Requirements for active cables

Organization Group requirements into a new section (6.13) wherever possible.

Not Changed Data rates (Gen 1, Gen 2) Tx eye spec

Loss & jitter budgets Rx JTOL

Updates Lane numbering Data striping

Data scrambling Ordered Sets & Lane Polarity Inversion

Compliance Patterns Rx Detection

Rx loopback LFPS

Ux Exit SKP rules

Test Points

Scope x2 operation








Rx loopback LFPS

Ux Exit SKP rules

Test Points

Scope x2 operation








Rx loopback LFPS

Ux Exit SKP rules

Test Points

Scope x2 operation








Rx loopback LFPS

Ux Exit SKP rules

Test Points


Outline

• x2 Capability Determination

• Lane Numbering

•Data Striping

•Data RequirementsScramblingOrdered SetsLane Polarity Inversion

• Lane-Lane Skew

•Compliance Patterns

• Functional RequirementsRx DetectRx LoopbackLFPSUx Exit

•Clock Offset Compensation

• Test Points

4


b0 b1 b2 b3 b4 b5 b6 b7

Gen 1x1 0 0 0 0 0 0 0 0

Gen 2x1 0 0 1 0 0 0 0 0

Gen 1x2 0 0 0 0 0 0 1 0

Gen 2x2 0 0 1 0 0 0 1 0

PH

Y C

apab

ility

Dat

a ra

te

Res

erve

d

# o

f la

nes

Res

erve

d

x2 Capability Determination (6.13.2)

Uses the PHY Capability LBPM during Polling.Portmatch (7.5.4.5).

5

Polling.LFPS

Polling.LFPSPlus

SCD1.LFPS handshake

Polling.RxEQ

Polling.LFPS handshake or timeout

Polling.PortMatch

Polling.PortConfig

SCD2.LFPS handshake

PHY Capability LBPM handshake

timeout

Polling.Active

Polling.Configuration

Polling.Idle

TSEQ Ordered Sets Transmitted

TS1 handshake

TS2 Handshake

Idle Symbol Handshake

timeout

timeout

timeout

directed

PHY Ready LBPM handshake

Exit to U0

Polling

[b3:b2] = 00 : 5G= 01 : 10G

[b6] = 0 : 1 lane= 1 : 2 lanes


Capability Matching & Fallback

• Defined in 7.5.4.5.

• Match to “least common” capability.

6

USB 3.2 DFP

Gen 1x1 Gen 1x2 Gen 2x1 Gen 2x2

USB 3.2 UFP

Gen 1x1 Gen 1x1 Gen 1x1 Gen 1x1 Gen 1x1




Fallback Order

• Fallback in order shown.


Lane Numbering (6.13.3)

• Lane 0 (Plug A2/A3 + B11/B10) is the Configuration Lane.

• Single-lane operation uses Lane 0 for backward compatibility.

7

SSTX2

SSRX2

SSTX1

SSRX1

CC2

USB D+/−Host USB

CC1

CC Logic & VCONN

Switch

SSTX2

SSRX2

SSTX1

SSRX1

CC2

USB D+/−

CC1

CC wire

CC Logic

Device USB

Configuration Lane

Lane 0

Lane 1


Lane Numbering (6.13.3)

• Lane 0 (Plug A2/A3 + B11/B10) is the Configuration Lane.

• Single-lane operation uses Lane 0 for backward compatibility.

8

SSTX2

SSRX2

SSTX1

SSRX1

CC2

USB D+/−Host USB

CC1

CC Logic & VCONN

Switch

SSTX2

SSRX2

SSTX1

SSRX1

CC2

USB D+/−

CC1

CC Logic

Device USB


Data Striping (6.13.4)• Data blocks are striped & aligned to lane 0.

• Data striping starts after SDS OS.

• Block headers are duplicated on both lanes.

• Start of packets may be initiated on either lane.

9


Data Requirements• Scrambling – per lane operation (6.13.5)

• Gen 1 seeds: lane 0 = FFFFh lane 1 = 8000h

• Gen 2 seeds: lane 0 = 1DBFBCh lane 1 = 0607BBh

• Ordered Sets (6.13.6)• TS1, TS2, TSEQ, SDS, SKP, SYNC are transmitted simultaneously on all lanes.

• TS1, TS2 Tx and Rx requirements shall be satisfied for all negotiated lanes before transitioning from Polling.Active to the next state.

• Upon receiving TS1 on any negotiated lane during U0, enter recovery and begin transmitting TS1 on all negotiated lanes.

• Lane Polarity Inversion (6.13.7)• Detection and correction shall be done on per lane basis for x2 operation.

10


Lane-Lane Skew• Defined in 6.13.8

• Applies to Gen 1x2 & Gen 2x2

• Comprehends skew sources: interconnect - PCB traces, PCB vias, package traces, circuit loading,

connectors, cables re-timers on Tx and Rx boards – requires deskew active cables - up to 50m optical

11

Test Point Max Skew (ps) DescriptionTP1 1300 Tx Si OutputTP2 2000 Tx Product Output/Cable InputTP3 4600 Cable Output/Rx Product InputTP4 6400 Rx Si InputTP1Ro, TP3Ro 1300 Output from Re-timerTP1Ri, TP3Ri 4800 Input to Re-timer

Specs


Compliance Patterns (6.13.9)• No new patterns.

• Compliance patterns shall be transmitted independently on each lane.

• Transmit same pattern on each lane.

• CP0 and CP9 use the scrambler seeds defined in 6.13.5.

• Advance to next CP upon receiving Ping.LFPS on either lane (refer to section 6.4.4).

12


Functional Requirements• Rx Detect (6.13.10)

• Performed only on the configuration lane (lane 0)• Same LTSSM flow as for x1

• Rx Loopback (6.13.11)• Performed on per lane basis• All lanes exit from loopback upon receiving LFPS

• LFPS (6.13.12)• Transmit on the configuration lane• Includes: Polling.LFPS (including SCD1/SCD2), LPBM, Ping.LFPS, Warm Reset,

Loopback exit

• Ux Exit (6.13.13)• Ux exit functionality is enabled in the configuration lane Rx

13


Clock Offset Compensation• SKP Insertion/Removal (6.13.6)

• Performed on a per-lane basis

• Transmitter rules (6.4.3.2)• x1 rules remain unchanged for Gen 1 and Gen 2

• x2 rules• Gen 1: follow Gen 1x1 rules AND multiply the # of SKP OS by the # of re-timers

detected during re-timer presence announcement (E.3.4.2.1)

• Gen 2x2: follow Gen 2x1 rules

14


Test Points• Defined in (6.2.1)

• TP2 mid-point: defined to be after the mated receptacle/plug on the plug side with the plug test board with the traces de-embedded

• TP3 mid-point: defined to be after the mated receptacle/plug on the receptacle side with the USB Type-C cable test fixture

15

Test Point DescriptionTP1 Transmitter silicon padTP2 Transmitter port connector mid-pointTP3 Receiver port connector mid-pointTP4 Receiver silicon padTP1Ro, TP3Ro Re-timer transmitter silicon padTP1Ri, TP3Ri Re-timer receiver silicon pad

PCBPCB

Pkg

Mate

d

Co

nne

cto

r

Si

+-

Txp

Txn

Mate

d

Co

nne

cto

r

Pkg

Rxp

Rxn

Re

-tim

er

SiRe

-tim

er

+-

TP

1R

i

TP

3R

i

TP

1

TP

2

TP

3

TP

4

TP

1R

o


Test Points: TP1 (Tx Silicon Pad)Application:

• Informative Tx jitter budget in Table 6-16 (6.5.1)

• Informative Tx specs in Table 6-19 (6.7.1)

• Tx lane-lane skew (6.13.8)

• Rx JTOL stressed source (swing, TxEQ, jitter) in Table 6-28 (6.8.5)

• Active cable input stressed source (swing, TxEQ, jitter)

16


Test Points: TP2 (Tx Connector Mid-point)Application:

• Tx SSC (6.5.3)

• Tx RJ (6.7.3)

• LFPS & LBPM (6.9)

• Active cable input stress signal

17

• Table 6-18 parameters (6.7.1)

• TxEQ (6.7.5)

• Lane-Lane Skew (6.13.8)

Tx1nTx1p

Rx0p

Tx0n

Rx0n

Tx0p

Rx1n

Rx1p

Full

Breakout

Pkg

TP1

Si

TP2

Tx1n

Tx1p

+-

+-

+-

+-

Rx0p

Tx0n

Rx0n

Tx0n

Rx1n

Rx1p

Pkg

Mate

d

Co

nne

cto

r

TP1 TP2

Si

+-

Txp

Txn

Device

Pkg

Mate

d

Co

nne

cto

r

TP1 TP2

Si

+-

Txp

Txn

Host

compliant

cable


Test Points: TP3 (Rx Connector Mid-point)Application:

• lane-lane skew (6.13.8)

• active cable output swing, TxEQ

18

CLB

Rx1p

Rx1n

Rx0n

Rx0p

HF-1C

Rx1n

Rx1p

Rx0p

Rx0n

Pkg

TP1

Si

TP2

Tx1n

Tx1p+-

+-

+-

Rx0p

Rx1n

Rx0n

Rx1p

Tx0n

Tx0p

TP3

+-


CLB

Rx1p

Rx1n

Rx0n

Rx0p

HF-1C

Rx1p

Rx1n

Rx0n

Rx0p

Pkg

TP1

Si

TP2

Tx1p

Tx1n

+-

+-

+-

+-

Rx1p

Rx1n

Rx0n

Rx1n

Tx0p

Tx0n

TP4

Test Points: TP4 (Rx Silicon Pad)Application:

• Tx eye measurement (host, hub, active cable)• eye height

• TJ (using RJ measured @ TP2)

• In practice, signal is measured @ TP2• Cable & CLB are embedded

by Sigtest.

19

TP4

Scope

Scope

Pkg

Mate

d

Co

nne

cto

r

TP1 TP2

Si

+-

Txp

Txn

TP4

Pkg

Mate

d

Co

nne

cto

r

TP1 TP2

Si

+-

Txp

Txn

Device

Host

compliant

cable

compliant

cable


Radio Frequency Interference

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Wifi Impact Wireless Mouse Sensitivity Impact

SuperSpeed data traffic can degrade wireless data throughput & reliability.

1

2

3

4

5

6

7

8

Noise (dbm/100kHz)

Mo

use

Ran

ge (

ft)

-70

-75

-80

-85

-90

-95

-100

-105


USB-C™ System RFI Test

21

Frequency (GHz)

0.5 64 5

No

ise

Co

up

led

(d

Bm

/10

0kH

z)

-100

-102

*Noise level specified is after correction for preamplifier gain

1 2 3

Specification Compliance Test Setup

System RFI spec & compliance test ensures coexistence with wireless links.

Fixture


Design for RFICoupling

Major noise coupling path: mating interface between the receptacle & plug, cables

Resources

• Connector selection: USB Type-C™ Cable and Connector Specification, Section 3.10.1.

• System design: http://www.usb.org/developers/docs/whitepapers/327216.pdf

22

Resources are available for designing your system to meet RFI requirements.


Link Layer/Re-timer Update – What’s New

23

• PHY Capability LBPM enhanced

• Re-timer presence announcement

• Introduction to USB 3.2 Re-timer• x2 re-timer requirement

• Link delay impact to Gen 2x2 performance• Increase Rx Header Buffer Credit

• PM_LC_TIMER/PM_ENTRY_TIMER

• Polling.LFPS 60-us LFPS EI ECR

No change to LTSSM and link layer framework


PHY LBPM Definition

• Backwards compatible

• Added new functions in PHY Ready LBPM• b6: for re-timer to

determine port orientation to host DFP or device UFP

• b7: for host to determine if re-timers need to be addressed

• LBPM message is state dependent

24


Re-timer Presence Announcement

• x2 only

• Defined for re-timer to announce its presence• Port may insert SKP OS

based on the number of re-timers

• Preserve a mechanism in future revisions for host to discover and configure re-timer

• Re-timer to increment b[4:2] when forwarding LBPM

• b[4:2] of the LBPM from host will be the re-timer index for future addressing

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Re-timer 1

Re-timer 2

Re-timer 3

Re-timer 4

10000 1 10100 1 10010 1

Re-timer 1

Re-timer 2

Re-timer 3

Re-timer 4

10000 1 10100 1 10010 1 10110 1

Re-timer 1

Re-timer 2

Re-timer 3

Re-timer 4

10000 1 10100 1 10010 1 10110 1 10001 1

Re-timer 1

Re-timer 2

UFPRe-timer

3Re-timer

4DFP

PHY Ready LPBM[b7:b0]

10000 1 10100 1

DFP

DFP

DFP UFP

UFP

UFP

Time

PHY Ready LPBM[b7:b0]

10000 0 10100 0

10000 0 10100 0 10010 0

10000 0 10100 0 10010 0 10110 0

10000 0 10100 0 10010 0 10110 0 10001 0


Re-timer Presence Announcement in Polling.PortConfigCase #1: no host addressing to re-timer

• Re-timer shall get both ports ready before forwarding the LBPM

• Re-timer may delay by one LBPM before forwarding• To allow re-timer to update b[4:2]

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Four PHY Ready LBPMS sent after receiving two

PR LBPM

TSEQ

TSEQDFP

UFP

UFP completes PHY Ready LBPM handshake

PR LBPM PR LBPMPR LBPM PR LBPMPR LBPM

PR LBPM PR LBPMPR LBPM PR LBPM PR LBPM

PR LBPM

PR LBPM

PR LBPM

DFP completes PHY Ready LBPM handshake

Polling.PortMatch

Polling.PortMatch

PR LBPM

Four PHY Ready LBPMS sent after receiving two

tPollingLBPMLFPSTimeout

tPollingLBPMLFPSTimeout

Polling.PortConfig (DFP)

Polling.PortConfig (UFP)

PR LBPM PHY Ready LBPM

Bit 7 de-asserted

PR LBPM PR LBPM

PR LBPM PR LBPM

Re-timer presence announcement

Re-timer presence announcement


Re-timer Presence Announcement in Polling.PortConfigCase #2: host addressing to re-timer

• DFP enters re-timer addressing stage after first PHY Ready LBPM handshake• Timeout handled by upper layer• USB 3.2 re-timer passes LBPM as is

• Upon completing re-timer addressing, DFP initiates PHY Ready LBPM and proceeds to exit

27

PR LBPM

TSEQ

TSEQDFP

UFP


PR LBPMPR LBPM

PR LBPM PR LBPMPR LBPM

PR LBPM PR LBPM


Polling.PortMatch

Polling.PortMatch PR LBPM

tPollingLBPMLFPSTimeout continue

tPollingLBPMLFPSTimeout continue

Polling.PortConfig (DFP)

Polling.PortConfig (UFP)

Bit 7 asserted

tPollingLBPMLFPSTimeout reset

Bit 7 de-asserted

tPollingLBPMLFPSTimeout Re-start


(tPollingLBPMLFPSTimeout reset)

PR LBPM

UFP detects bit 7 de-asserted from DFP PR LBPM


PR LBPM PHY Ready LBPM

Minimum implementation required to allow USB 3.2 re-timer forward compatible

PHYReady LBPM handshake for re-timer addressing


Scenario analysis of re-timer addressing RT1

• Host/device achieve PHY_Ready LBPM handshake with bit-7 in host PHY_Ready LBPM asserted• all host/device/re-timers remain in Polling.PortConfig

• Host is not aware of RT’s capability, and starts addressing RT1• RT1 passes thru RTConfig LBPM (to be defined in future revision)

• RT2, upon detecting RTConfig LBPM addressing its preceding RT1, drops RTConfig LBPM

• Host times out and declares RT1 non addressable

• RT3/RT4/Device remain in Polling.PortConfig

host

RT1

RT2

RT3

RT4

device

RT (non-addressable) RT (addressable)


Scenario analysis of re-timer addressing RT2-RT4

• Host starts addressing RT2• RT1 passes RTConfig LBPM• RT2 decodes RTConfig LBPM and acknowledge

• RT3/RT4/Device remain Polling.PortConfig

• Upon completion of RT2 configuration, host addresses RT3• RT3 passes LBPM and RT4 discarded it• Host times out and concludes RT3 non addressable and starts addressing

RT4

• After RT4 config, host issues PHY_Ready LBPM with bit-7 de-asserted• All RT pass the PHY_Ready LBPM and monitor the exit handshake• Device upon detecting PHY_Ready LBPM, participates the exit handshake

• Upon completing the exit handshake, host/dev/RT enter Polling.RxEQ

host

RT1

RT2

RT3

RT4

device

RT (non-addressable) RT (addressable)


Scenario analysis of re-timer addressing RT1~RT4

• All retimers are not addressable1. Host starts addressing RT12. RT1~RT4 passes RTConfig LBPM3. Device detect RTConfig LBPM and discarded4. Host times out and declares RT1 non-addressable

• Host repeats step 1~4 until it concludes all RT non-addressable

• Host issues PHY_Ready LBPM with bit-7 de-asserted• All RT pass the PHY_Ready LBPM and monitor the exit handshake• Device upon detecting PHY_Ready LBPM, participate the exit

handshake

• Upon completing the exit handshake, host/dev/RT enter Polling.RxEQ

host

RT1

RT2

RT3

RT4

device

RT non-(addressable) RT (addressable)


Introduction to USB 3.2 Re-timer

• Lane to lane de-skew• OS boundary shall be maintained when switching from local to received

TS1/2 OS – preserve Tx lane to lane skew• De-skew can be performed based TS1/2 OS, SKP OS, or SYNC OS

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Rx

RTSSM

RxTx

Symbol Recovery EB

Data striping

RD monitor

Protocol intercept

RTSMLTSSM LTSSM

Descramble

Symbol Recovery EB

Deskew

Deskew Tx

Scrambler Sync

Scrambler Sync

Symbol RecoveryEB

Symbol RecoveryEB

Deskew

Deskew

Scrambler Sync

Scrambler Sync

Data striping

RD monitor

Protocol intercept

Descramble

Rx[1:0]

Rx[1:0]

Tx[1:0]

Tx[1:0]

• Two-lane bonding with lane to lane de-skew

• Only SRIS re-timer is defined for x2 operation

• Re-timer SKP OS• Gen 1x2: based on re-timer presence

announcement (new)• Gen 2x2: same as Gen 2x1, option to

reduce based on re-timer presence announcement

• tDRe-timer budget• Gen 1x2: 300 ns• Gen 2x2: 150 ns

Lane to lane de-skew adds propagation delay in EB


x2 Re-timer Lane to Lane De-skew and EB Depth

• SKP OS insertion rule same as x1 – per lane based

• Packets transmitted on two-lanes – EB depth reduced

• Gen 1: 5-SI [(354 +(1056/2)x5e-3]

• Gen 2: 6-SI [(40+68/2)x16x5e-3]

• De-skew buffer depth: z = x + y

• Max input skew – 4.8ns x SI

• Gen 1: x = 3-SI

• Gen 2: x = 6-SI

• Max Rx data path skew – y SI

• Implementation specific

• Want z < 8 if use TS1 OS to perform de-skew• If z > 8

• Use SKP OS in Gen 1 (354 SI delay)

• Use SYNC OS in Gen 2 (32 block delay)

32

Rx data path skew

RxD TxD

RxCLK TxCLK

Half-full

8-SI 8-SI

RxD0

RxCLK0

5-SI 5-SIRxD1

RxCLK1

TxD0

TxCLK

TxD1

TxCLK

z-SI

Half-full

Gen 1x1 EB

Gen 1x2 EB w. De-skew


Link delay impact to Gen 2x2 performance –Problem statement• Proposed tDRe-timer, and tDHPResponse have added significant delay that

may degrade throughput performance in Gen2x2 operation• tDRe-timer = 150nS,

• tDHPResponse = 1255ns (tDPacket:~460ns; SKPs: 20ns; HP process time: ~480ns)

• Total Roundtrip delay to return LCRD: ~2.2us (150x6+1255+…)

• Rx Header Buffer Credit LCRD_x = 4 per each traffic class• Allow 4 outstanding packets

• 4 max. packets @ Gen2 x2 = 4 x 450nS (34 blocks)~1.8uS

• After burst 4 DP, the port has to wait 400ns for returned LCRD before starting another transfer 400ns of IS between the two burst

• Effective throughput (1.8/2.2)x20Gbps16Gbps (max)

Want round-trip delay < burst duration to sustain the throughput


Proposal – Apply to Gen2 x2 only

• Increase the number of credits available from 4 to 7• LCRD A,B,C,D,E,F,G. (for both Type 1 and Type 2)

• Allow upto 7 outstanding packets max burst duration is ~3.2us• Enough to cover max roundtrip delay up to 3uS and

continue the burst

• No change in header sequence numbers, LGOOD 0 – 15

• Spec changes:• Change the link command word in Gen 2x2

• b3 -> Credit Series (0 = LCRD1_x, 1 = LCRD2_x)• b[2:0] -> Rx Header buffer credit (000 – 110 -> LCRD

A to G; 111-> Reserved)


Additional Timing Adjustment in x2 Operation

• PM_LC_TIMER/PM_ENTRY_TIMER doubled in x2 operation

35


Polling.LFPS 60us LFPS EI ECR• Proposed to address legacy device passing compliance but not compliant to

spec• USB 3.1 Gen 1 devices found to not exit from Polling.LFPS even after completing the

Polling.LFPS handshake • Exit only after DFP has stopped sending Polling.LFPS

• The above behavior leads to USB 3.1 Gen 2 capable DFP, after falling back to SS operation, will NOT achieve the timeout condition of the 60-us LFPS EI timer

37


Q&A

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USB 3.2 PHY and Link Spec€¦ · 12/02/2019 · •PHY design reuse is a high priority –both...

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