UPDATE ON CLICPIX2 DESIGN Pierpaolo Valerio Edinei Santin 08.05.2015 1.
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Transcript of UPDATE ON CLICPIX2 DESIGN Pierpaolo Valerio Edinei Santin 08.05.2015 1.
UPDATE ON CLICPIX2 UPDATE ON CLICPIX2 DESIGNDESIGN
Pierpaolo ValerioEdinei Santin 08.05.2015
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Pad geometryPad geometry
2
25 um
2.5 um
3.5 um
After a discussion with Sami, we worked on the pad shape
We were recommended to leave a large enough opening for electroplating and have a spacing of 3 um from the opening to the edge of the pads
Other restrictions are imposed by DRC rules and space for power distribution
VDDA
VSSA
VDDD
VSSD
Pad geometryPad geometry
3
8 um
14 um
12 um10 um
22.5 um
There is only a 2 um spacing between the opening and the edge of the pad, but the opening is big enough for electroplating
An added aluminium “tail” can increase the capacitance to a HVCMOS sensor
IR drops on VDDA/VSSAIR drops on VDDA/VSSA
Ultra-thick metal, M6 (Rsh ≈ 5 mΩ/sq), for power distribution With Ru ≈ 36 mΩ, Ipx ≈ 10 µA, and Npx = 128, we have ∆V ≈ 5.9 mV
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Update on the readout Update on the readout schemescheme
5
The current readout architecture works as intended, but it’s difficult to use a fast clock due to synchronization issues
In order to make it easier to design the DAQ board and firmware, we want to use a higher clock frequency with a clock recovery mechanism (8/10 bit encoding)
Due to the lack of a PLL block, we will use the readout clock (100 MHz) as the input clock for control signals and have a second clock (≥ 640 MHz) only used for the readout command
Parallel ReadoutParallel Readout
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In order to decouple the readout clock from the pixel clock, we can read more columns in parallel
The picture depicts the case with one column at a time (as in CLICpix1)
Parallel ReadoutParallel Readout
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If the chip is configured to read more than one column at a time, the pixel clock is divided by the number of columns being read out
The data is then serialized with the readout clock
8/10 bit encoding can be added at the output
Readout EfficiencyReadout Efficiency
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If more than one column is being read out, all of them must finish shifting data at the same time
This means that, due to the compression, the column with the most data (the slowest) limits the readout speed
We can calculate the efficiency with various occupancies and number of parallel columns
Occupancy
Efficie
ncy
# columns
Readout TimeReadout Time
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Occupancy
Read
out t
ime
(ms)
# columns
Occupancy
Read
out t
ime
(ms)
# columnsReadout time with a
640 Mb/s serializerReadout time with
a 2 Gb/s serializerThe readout time is well within the CLIC
specifications even with 2 parallel columns
Other newsOther news
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There is an joint Engineering run being prepared by RD53. It could be possible to submit our design in this run instead that in an MPW in order to have access to full wafers, which would greatly simplify the bump bonding process. Schedules and costs for this option are still not clear
The bandgap(s) to be implemented are ready and their designer can modify the layout to have them fit CLICpix2
Better substrate isolation techniques were studied and will be implemented (specifically, using deep n-well to isolate the analog pixels from the digital logic)
Thank you!Thank you!
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