University of Tehran 1 Microprocessor System Design Processor Timing.

50
University of Tehran 1 Microprocessor System Design Processor Timing

Transcript of University of Tehran 1 Microprocessor System Design Processor Timing.

Page 1: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 1

Microprocessor System Design

Processor Timing

Page 2: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 2

Outline

• Machine cycle

• Fetch, decode, execute

• Processor timing

• Bus cycles

• Memory / IO read

• Memory / IO write

Page 3: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 3

Where is a program stored?

;assume that initially

;ds = 2000, bx = 0023, ax = 351C

;cs = 1000, ip = 0005

mov [bx], al ;8807

hlt ;F4

Page 4: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 4

How does the P works?

• Fetch

• Increment Program Counter (CS:IP) by 1

• Decode

• Execute

Page 5: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 5

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0005IP

5678DI

Inst. Queue

CS:IP

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

FETCH

Page 6: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 6

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0005IP

5678DI

Inst. Queue

1000:0005

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

FETCH

Page 7: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 7

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0005IP

5678DI

Inst. Queue

10005

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

FETCH

Page 8: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 8

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0005IP

5678DI

Inst. Queue

10005

LOW

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WRHIGH

FETCH

Page 9: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 9

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0005IP

5678DI

Inst. Queue

10005

88

LOW

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WRHIGH

FETCH

Page 10: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 10

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0005IP

5678DI

Inst. Queue

88

10005

88

LOW

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WRHIGH

FETCH

Page 11: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 11

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0005+1IP

5678DI

Inst. Queue

88 2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

INC. PC

Page 12: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 12

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0006IP

5678DI

Inst. Queue

88 2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

INC. PC

Page 13: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 13

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0006IP

5678DI

Inst. Queue

88 2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

DECODE

mov [bx], ?

Page 14: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 14

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0006IP

5678DI

Inst. Queue

88

CS:IP

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

FETCH

Page 15: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 15

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0006IP

5678DI

Inst. Queue

88

1000:0006

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

FETCH

Page 16: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 16

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0006IP

5678DI

Inst. Queue

88

10006

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

FETCH

Page 17: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 17

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0006IP

5678DI

Inst. Queue

88

10006

LOW

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WRHIGH

FETCH

Page 18: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 18

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0006IP

5678DI

Inst. Queue

88

10006

07

LOW

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WRHIGH

FETCH

Page 19: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 19

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0006IP

5678DI

Inst. Queue

8807

10006

07

LOW

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WRHIGH

FETCH

Page 20: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 20

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0006+1IP

5678DI

Inst. Queue

8807 2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

INC. PC

Page 21: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 21

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0007IP

5678DI

Inst. Queue

8807 2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

INC. PC

Page 22: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 22

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0007IP

5678DI

Inst. Queue

8807 2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

DECODE

mov [bx], al

Page 23: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 23

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0007IP

5678DI

Inst. Queue

8807

DS:BX

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

EXECUTEmov [bx], al

Page 24: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 24

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0007IP

5678DI

Inst. Queue

8807

2000:0023

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

EXECUTEmov [bx], al

Page 25: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 25

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0007IP

5678DI

Inst. Queue

8807

20023

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

EXECUTEmov [bx], al

Page 26: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 26

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0007IP

5678DI

Inst. Queue

8807

20023

1C

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

EXECUTEmov [bx], al

Page 27: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 27

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0007IP

5678DI

Inst. Queue

8807

20023

1C

HIGH

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WRLOW

EXECUTEmov [bx], al

Page 28: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 28

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0007IP

5678DI

Inst. Queue

8807

20023

1C

HIGH

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

1C

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WRLOW

EXECUTEmov [bx], al

Page 29: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 29

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0007IP

5678DI

Inst. Queue

CS:IP

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

1C

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

FETCH

Page 30: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 30

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0007IP

5678DI

Inst. Queue

1000:0007

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

1C

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

FETCH

Page 31: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 31

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0007IP

5678DI

Inst. Queue

10007

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

1C

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

FETCH

Page 32: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 32

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0007IP

5678DI

Inst. Queue

10007

LOW

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

1C

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WRHIGH

FETCH

Page 33: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 33

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0007IP

5678DI

Inst. Queue

10007

F4

LOW

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

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29

12

7D

1C

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WRHIGH

FETCH

Page 34: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 34

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0007IP

5678DI

Inst. Queue

F4

10007

F4

LOW

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

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29

12

7D

1C

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WRHIGH

FETCH

Page 35: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 35

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0007+1IP

5678DI

Inst. Queue

F4

10007

F4

LOW

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

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29

12

7D

1C

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WRHIGH

INC. PC

Page 36: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 36

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0008IP

5678DI

Inst. Queue

F4

10007

F4

LOW

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

1C

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WRHIGH

INC. PC

Page 37: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 37

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0008IP

5678DI

Inst. Queue

F4

10007

F4

LOW

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

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29

12

7D

1C

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WRHIGH

DECODE

hlt

Page 38: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 38

A19

A0

:

D7

D0

:

MEMR

MEMW

1234

BP

ES

DS

SS

CX

BX

AX

34CD

AB12

1AB3

2000

0000

0023

3F1C

FCA1

SP

DX

1243

CS

SI

1000

0008IP

5678DI

Inst. Queue

F4 2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

::

45

98

27

39

42

88

07

F4

8A

::

20020

20021

20022

20023

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29

12

7D

1C

19

25

36

::

::

::

::

A19

A0

:

D7

D0

:

RD

WR

EXECUTEhlt

Page 39: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 39

Machine Cycle

Page 40: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 40

Machine Cycle Timing Diagram

10005

IOR

IOW

MEMR

MEMW

___

____

_____

______

AddressBus

Data Bus

fetch

M1 M2 M3

88 07

10006 20023

1C

M1

10007

F4

fetch

execute

fetch

execute

mov [bx],al hlt

Control Bus

Page 41: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 41

10005

IOR

IOW

MEMR

MEMW

___

____

_____

______

AddressBus

D7

M1 M2 M3

10006 20023

M1

10007

Control Bus

D6

D5

D4

D3

D2

D1

D0

Page 42: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 42

Processor Timing

Page 43: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 43

Processor Timing Diagramfor the 1st fetch machine cycle (M1)

of instruction mov [bx],al

IOR

IOW

MEMR

MEMW

___

____

_____

______

AddressBus

Data Bus

T1 T2 T3

M1

CLOCK

10005

88

Page 44: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 44

Processor Timing Diagramfor the 2nd fetch machine cycle (M2)

of instruction mov [bx],al

IOR

IOW

MEMR

MEMW

___

____

_____

______

AddressBus

Data Bus

T1 T2 T3

M2

CLOCK

10006

07

Page 45: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 45

Processor Timing Diagramfor the execute machine cycle (M3)

of instruction mov [bx], al

IOR

IOW

MEMR

MEMW

___

____

_____

______

AddressBus

Data Bus

T1 T2 T3

M3

CLOCK

20023

1C

Page 46: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 46

Processor Timing Diagramfor the 1st fetch machine cycle (M1)

of instruction hlt

IOR

IOW

MEMR

MEMW

___

____

_____

______

AddressBus

Data Bus

T1 T2 T3

M1

CLOCK

10007

F4

Page 47: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 47

Processor Timing Diagramfor any memory read machine cycle

IOR

IOW

MEMR

MEMW

___

____

_____

______

AddressBus

Data Bus

T1 T2 T3

CLOCK

memory address

datain

Page 48: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 48

Processor Timing Diagramfor any memory write machine cycle

IOR

IOW

MEMR

MEMW

___

____

_____

______

AddressBus

Data Bus

T1 T2 T3

CLOCK

memory address

data out

Page 49: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 49

Processor Timing Diagramfor any I/O read machine cycle

IOR

IOW

MEMR

MEMW

___

____

_____

______

AddressBus

Data Bus

T1 T2 T3

CLOCK

port address

datain

Page 50: University of Tehran 1 Microprocessor System Design Processor Timing.

University of Tehran 50

Processor Timing Diagramfor any I/O write machine cycle

IOR

IOW

MEMR

MEMW

___

____

_____

______

AddressBus

Data Bus

T1 T2 T3

CLOCK

port address

data out