UNIVERSITY OF MARY HARDIN-BAYLOR COMPUTER SCIENCE CLASS SYLLABUS

Fall, 2011GENERAL INFORMATION

Course Number: ENGR 2337Course Title: Digital Logic DesignNumber of Credits: 3Location of Class: Room 101 & 122 DAVMeeting Time: 11:00 – 12:20 pm Tuesday & ThursdayProfessor: Dr. William G. Tanner, Jr.Office: Room 119 Davidson BuildingOffice Hours: See Professor’s schedule posted in DavidsonOffice Phone: (254) 295 - 4645Email: btanner@umhb.edu

COURSE DESCRIPTION

This course, i.e. Digital Logic Design, will investigate Boolean algebra, number systems and representations, analysis and design of combinational and sequential logic circuits, minimization, small and medium scale integrated devices, programmable logic and simulation of digital circuits. In this course, you will learn about and implement the building blocks that serve to construct digital systems using components in small, medium, and large scale integration (SSI, MSI, and LSI) and programmable logic devices (PLDs). The purpose is provide you with a working knowledge of digital concepts and design considerations that will allow you to apply your knowledge to more complex systems, such as microprocessors and computer architecture, including a working knowledge of VHDL.

You will also learn about the fundamental building blocks of all digital systems—logic gates, Boolean algebra, and logic simplification. Because minimization is an important concept in digital design, you will learn about various minimization techniques, such as Boolean theorems, truth tables, graphic symbol manipulation, and using Karnaugh maps to formulate a digital system in terms of a sum of products (SOP) or product of sums (POS) expression.

Finally, you will learn about the difference between combinatorial and sequential logic circuits and the importance of timing. Using flip-flops, you will learn how to implement asynchronous and synchronous counters and shift registers, and how to design sequential logic circuits from basic word descriptions. The course will involve individual homework and projects, quizzes, and group projects. Be prepared!

COURSE OBJECTIVES

Students will: Learn various numbering systems and their appropriate use in digital systems design. Learn the basic concepts of Boolean algebra and how to manipulate Boolean equations. Learn minimization techniques for designing efficient combinational & sequential logic circuits. Be familiar with basic digital circuit building blocks (for example, decoders, multiplexers, shift registers) Be able to incorporate these fundamental logic circuits into larger, more complicated digital designs. Learn the electrical characteristics of fundamental combinational and sequential circuits and understand the

impact of these characteristics on digital designs. Learn basic sequential circuit design methods and understand the use of flip-flops and latches. Learn modern software tools for implementing and designing digital systems. Be introduced to VHDL for designing and simulating digital circuits.

COURSE MATERIALS

Textbook

Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd ed. McGraw-Hill Higher Education, 2009. Other items

A flash drive is required for this class (a 4 GB drive to a 16 GB USB drive is recommended).

COMPUTING LABORATORY

Current account on the CSE Server (mars.umhb.edu) will be provided for which you have paid a laboratory fee. Sufficient disk space on the server should be available, but if you wish to maintain a backup copy of your work, you will need to purchase a sufficient number CDRs to do so.

COURSE POLICY AND PROCEDURES

1. Grading: The final grade calculation will be reached according to the distribution described on page 68 of the 2009 - 2010 UMHB Catalog. The final course grade will be computed by the following percentages:

Class participation & Laboratory Assignments 20% Unit Examinations (3) 60%Final Examination 20%

2. Attendance: Each student is expected to attend ALL scheduled classes and will be held responsible for all class work and assignments. Continued absences will result in an unsatisfactory grade report for the course, e.g. missing more than six sessions. To be counted present, a student must be in the classroom during the scheduled class or lab time for at least 80% of schedule time.

3. Cell phones: Each student will turn off all cell phones at the beginning of class and will not be allowed to be used during any examinations.

4. Examinations: Each student is required to be present for ALL examinations. If an extreme emergency occurs, and you cannot make the examination time, a student should make every effort to contact the professor by email, telephone or in person to receive permission to miss the examination. Permission will be granted only in the case of extenuating circumstances.

5. Makeup examinations: Each student who wishes to take a “makeup examination” must make arrangements with the professor to take the examination. A “makeup examination” must be scheduled during office hours BEFORE the next scheduled examination. If a student fails to seat for a “makeup examination” before the next scheduled examination, that student will receive a ZERO for the examination he/she missed.

6. Assignments: All assignments will be due on the DUE-DATE indicated in the course schedule. They are due at the beginning of a class period.

7. Final Examination: The final examination will be comprehensive and will be requisite for all students. NO MAKEUP WILL BE GIVEN FOR THE FINAL EXAM.

SCHEDULE FOR FALL 2011 - ENGR 2337 DIGITAL LOGIC DESIGN

Month Date Reading Assignment Text Laboratory AssignmentAug 23 Introduction - Syllabus B&V IntroductionAug 25 Chapter 1: Design Concepts B&V Digital Logic Lab 1

Aug 30 Chapter 1: Design Concepts B&V Digital Logic Lab 1Sep 01 Chapter 2: Intro. To Logic Circuits B&V Digital Logic Lab 2

Sep 06 Chapter 2: Intro. To Logic Circuits B&V Digital Logic Lab 2 Sep 08 Chapter 2: Intro. To Logic Circuits B&V Digital Logic Lab 3

Sep 13 REVIEW OF CHAP 1 - 2 B&V Digital Logic Lab 3Sep 15 EXAM #1 (Chap 1- 2) B&V LAB ASSIGN #1 - #3 (DLL 1)

Sep 20 Chapter 4: Optimized Implementation B&V Digital Logic Lab 4Sep 22 Chapter 4: Optimized Implementation B&V Digital Logic Lab 4

Sep 27 Chapter 4: Optimized Implementation B&V Digital Logic Lab 5Sep 29 Chapter 4: Optimized Implementation B&V Digital Logic Lab 5

Oct 04 Chapter 3: Implementation Technology B&V Digital Logic Lab 6Oct 06 Chapter 3: Implementation Technology B&V Digital Logic Lab 6

Oct 11 REVIEW OF CHAP 3 - 4 B&V Digital Logic Lab 6Oct 13 EXAM #2 (Chap 3 - 4) B&V LAB ASSIGN #4 - #6 (DLL 2)

Oct 18 Chapter 5: Number Representation B&V Digital Logic Lab 7Oct 20 Chapter 5: Number Representation B&V Digital Logic Lab 7

Oct 25 Chapter 5: Number Representation B&V Digital Logic Lab 7Oct 27 Chapter 5: Number Representation B&V Digital Logic Lab 8

Nov 01 Chapter 6: Combinational - Circuits B&V Digital Logic Lab 8Nov 03 Chapter 6: Combinational - Circuits B&V Digital Logic Lab 9

Nov 08 REVIEW OF CHAP 5 - 6 B&V Digital Logic Lab 9Nov 10 EXAM #3 (Chap 5 - 6) B&V LAB ASSIGN #7 - #10 (DLL 3)

Nov 15 Chapter 7: Flip-Flops, Registers, Count. B&V Digital Logic Lab 10Nov 17 Chapter 7: Flip-Flops, Registers, Count. B&V Digital Logic Lab 10

Nov 22 Chapter 7: Flip-Flops, Registers, Count B&V Digital Logic Lab 11Nov 24 THANKSGIVING HOLIDAYS

Nov 29 Chapter 8: Synchronous Sequential Cir. B&V Digital Logic Lab 11Dec 01 Chapter 8: Synchronous Sequential Cir. B&V Digital Logic Lab 12

Dec 06 REVIEW OF CHAP 1 – 8 B&V LAB ASSIGN #10 - #12 (DLLS)Dec 08 FINAL (Chaps 1 - 8) IN CLASS B&V CUMULATIVE EXAM