University of Calcutta CBM 1 ROC Design Issues Dr. Amlan Chakrabarti, Dr. Sanatan Chattopadhyay &...
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Transcript of University of Calcutta CBM 1 ROC Design Issues Dr. Amlan Chakrabarti, Dr. Sanatan Chattopadhyay &...
University of CalcuttaCBM 1
ROC Design Issues
Dr. Amlan Chakrabarti, Dr. Sanatan Chattopadhyay
&
Mr. Suman Sau
University of CalcuttaCBM 2
Outline
• Basic Read Out System
• Interfacing With Analog Signal using SPI
• RS 232 Serial Communication
• Communication With TEMAC Ethernet Core
• Conclusion
University of Calcutta
Basic Readout System
Detector
Detector
FEEB ROC
XY
TE
RX
YT
ER
AD
C
Tag data
Tag data
ADC data
clock
FP
GA
control
Front-End Board
Read-OutController
cableconnection
2 N-XYTER256 ch.
LVDS signalcable
Any PCConnectivity
ETH
PHY
University of CalcuttaCBM 5
The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines.
The SPI bus specifies four logic signals.• SCLK — Serial Clock (output from master)• MOSI/SIMO — Master Output, Slave Input (output from master)• MISO/SOMI — Master Input, Slave Output (output from slave)• SS — Slave Select (active low; output from master)
Serial Peripheral Interface Bus
SCLK SPI Master MOSI
MISO --- SS
SCLK SPI MOSI Slave
MISO---SS
University of Calcutta
Results
Figure shows the digital values corresponding to the onboard analog voltage according to equation
University of CalcuttaCBM 8
Analog module interfacing with FPGA
PmodAD1
PmodDA2
Analog I/P(Audio Signal)
PmodDA2
12-bit Digital Value
12-bit Digital Value I/P for D/A converter
Analog O/P
Spartan 3E FPGA
SPI Bus Communication has been successfully established
University of Calcutta
Real Time Digital Conversion of audio signal
Top view of the implemented architecture
University of CalcuttaCBM 11
Analog module interfacing with FPGA
P160 Analog ModuleVirtex-4LX/SX Development Board
University of CalcuttaCBM 12
Problem Regarding P160& Virtex-4LX/SX
• Analog Module P160 is not physically adjustable with Virtex-4 LX/SX
• We need P240 Analog Module which is physically compatible.
• Order to buy P240 Analog Module already Placed
University of CalcuttaCBM 14
Communication through RS232
RSA 32 bit Crypto core
RS232_DCE
LED Display
RS232_DTE
Downloading
Bit File
Real Time Data
From Key Board
Spartan 3E Board
Ciphertext Send and Receive
University of CalcuttaCBM 19
P
H
Y
EMAC
TEMAC EthernetFIFO
Address Swap Module
TX ClientFIFO
RX ClientFIFO
TEMAC (Loop Back) Testing in ML505
It is a simple design that mirrors incoming Ethernet packets
University of CalcuttaCBM 20
Status of the Ethernet Communication before running of the program
Status of the Ethernet Communication after the program was run
University of Calcutta
Conclusion
Research team at C.U, can contribute in the CBM research:
1. Development of Firmware for ROC boards.
2. Testing of the ROC board with the Firmware to be supplied by GSI.
3. Board level testing of the ROC provided we can get funding for the manpower and testing equipments for board level testing.
4. Developmental activities for circuit design and process technology based research for the ASIC design, again we require some funding for this to procure the IC design tools.
5. Research for radiation hardened FPGA development.