UNIVERSITI MALAYSIA PERLIS

Peperiksaan Semester Kedua

Sidang Akademik 2015/2016

Jun 2016

EKT 124 –Elektronik Digit 1

[Digital Electronics1]

Duration : 3 hours Masa : 3 jam

Please make sure that this paper has SIXTEEN (16) printed pages including this front page before

you start the examination. [Sila pastikan kertas soalan ini mengandungi ENAM BELAS (16) muka surat yang bercetak termasuk muka hadapan

sebelum anda memulakan peperiksaan ini.]

This question paper has SIX (6) questions. Answer ALL questions in SECTION A and ANY

ONE (1) question in SECTION B. Attach Appendix A and Appendix B together with the answer

script if Question 5 is chosen in Section B, while attach Appendix C, Appendix D and Appendix

E if Question 6 is chosen. [Kertas soalan ini mengandungi ENAM(6) soalan. Jawab SEMUA soalan di BAHAGIAN A dan pilih MANA-

MANA SATU (1) soalan di BAHAGIAN B. Kepilkan Lampiran A dan Lampiran B bersama-sama skrip jawapan

sekiranya Soalan 5 dipilih di Bahagian B, manakala kepilkan Lampiran C, Lampiran D dan Lampiran E sekiranya

Soalan 6 dipilih.]

SULIT -2- (EKT124)

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….3/-

SECTION A [Bahagian A]

Question 1 [Soalan 1]

[C1, CO1, PO1]

a) State an example of a system that is: [Nyatakan contoh sebuah sistem yang:]

(i) Entirely analog. [Seluruhnya analog.]

[1 Mark/markah]

(ii) Entirely digital. [Seluruhnya digital.]

[1 Mark/markah]

(iii) Combination of both digital and analog. [Gabungan kedua-dua digital dan analog.]

[1 Mark/markah]

b) Describe hexadecimal number system. [Jelaskan sistem nombor keenambelasan.]

[1 Mark/markah]

[C2, CO1, PO1]

c) Convert the following numbers according to the base given. Write the steps involved for each

conversion. [Tukar nombor-nombor berikut berdasarkan asas yang diberikan. Tulis langkah-langkah yang terlibat untuk

setiap penukaran.]

(i) 7348 to hexadecimal. [7348 kepada keenambelasan.]

[4 Marks/markah]

(ii) 58.62510 to binary. [58.62510 kepada perduaan.]

[4 Marks/markah]

(iii) 10110101111.0112 to octal. [10110101111.0112 kepada perlapanan.]

[2 Marks/markah]

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[C1, CO1, PO1]

d) Describe in words the operation of the following logic gates to produce a HIGH and a LOW

output. [Perihalkan dalam perkataan operasi bagi get-get logik berikut untuk menghasilkan output TINGGI dan

RENDAH.]

(i) Exclusive-NOR gate. [Get TAK ATAU-eksklusif.]

[2 Marks/markah]

(ii) NAND gate. [Get TAK DAN.]

[2 Marks/markah]

(iii) Inverter gate. [Get penyongsang.]

[2 Marks/markah]

….4/-

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Question 2 [Soalan 2]

[C2, CO1, PO1]

a) Convert binary number 10010102 to Gray code. [Tukarkan nombor perduaan 10010102 kepada kod Gray.]

[2 Marks/markah]

b) Compute the following binary arithmetic operations: [Kirakan operasi aritmetik perduaan berikut:]

(i) 1100002 - 11112.

[2 Marks/markah]

(ii) 1102 × 1112

[2 Marks/markah]

c) Express a given pair of decimal numbers to an 8-bit sign-magnitude form and then add both

numbers using the 2’s complement form. [Nyatakan sepasang nombor perpuluhan yang diberi kepada 8-bit tanda-magnitud dan kemudian tambah kedua-

dua nombor menggunakan bentuk pelengkap 2.]

-46 and 25

[4 Marks/markah]

[C3, CO2, PO1]

d) Given a standard POS expression as below. Obtain the following using a Karnaugh map (K-

Map): [Diberikan ungkapan piawai POS seperti di bawah. Dengan menggunakan peta Karnaugh, dapatkan yang

berikut:]

(�̅� + �̅� + 𝐶 + 𝐷)(𝐴 + �̅� + 𝐶 + 𝐷)(𝐴 + 𝐵 + 𝐶 + �̅�) (𝐴 + 𝐵 + 𝐶̅ + �̅�)(�̅� + 𝐵 + 𝐶 + �̅�)(𝐴 + 𝐵 + 𝐶̅ + 𝐷)

(i) A minimum POS expression. [Ungkapan POS yang minima.]

[3 Marks/markah]

(ii) A standard SOP expression. [Ungkapan piawai SOP.]

[3 Marks/markah]

(iii) A minimum SOP expression. [Unkapan SOP yang minima.]

[4 Marks/markah]

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Question 3 [Soalan 3]

[C5, CO3, PO2]

Figure 1 shows a circuit of an output F which combines the use of half adder and 2-bit comparator.

Input A0 originates from output sum labelled as Ʃ and input B0 originates from output carry out,

Co. [Rajah 1 menunjukkan litar keluaran F yang menggabungkan penggunaan penambah separuh dan pembanding 2-

bit. Input A0 berasal dari output hasil tambah berlabel Ʃ dan B0 berasal dari output bawaan keluar, Co.]

Figure 1 [Rajah 1]

a) Determine the truth table for the half adder and 2-bit comparator. [Tentukan jadual kebenaran untuk penambah separuh dan pembanding 2-bit.]

[6 Marks/markah]

b) Produce Boolean expression for the half adder. [Hasilkan ungkapan Boolean untuk penambah separuh.]

[1 Mark/markah]

c) Produce simplified Boolean expression for the 2-bit comparator using K-map with A0, A1, B0,

and B1 as the input. [Hasilkan ungkapan Boolean termudah untuk pembanding 2-bit menggunakan K-map dengan A0, A1, B0, dan B1

sebagai input.]

[5 Marks/markah]

d) Using the Boolean expression from (b) and laws and rules of Boolean algebra, produce

simplified Boolean expression F (W, X, Y, Z). [Dengan menggunakan ungkapan Boolean dari (b) dan undang-undang dan peraturan aljabar Boolean, hasilkan

ungkapan Boolean F (W, X, Y, Z) yang termudah.]

[5 Marks/markah]

e) Sketch a circuit based on simplified expression F from (d). [Lakar litar berdasarkan ungkapan termudah F dari (d).]

[3 Marks/markah]

W

X

Ʃ

Co

Y

Z

A0

A1

B0

B1

Half

Adder

2-bit

comparator F = A > B

.…4/- .…6/-

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Question 4 [Soalan4]

[C5, CO3, PO2]

a) Design a circuit using an 8-to-1 multiplexer (MUX) to realize the Boolean expression given

below: [Reka bentuk sebuah litar dengan menggunakan pemultipleks 8-ke-1 (MUX) untuk merealisasikan ungkapan

Boolean yang diberikan di bawah:]

FW,X,Y,Z = Σ (0,2,5,7,13)

[12 Marks/markah]

b) Construct an 8-to-1 multiplexer using a combination of 4-to-1 and 2-to-1 multiplexers. Label

the input, output and selector clearly in your design. If the output of the 8-to-1 multiplexer is

F = I3, predict the input for each selector and the output of each multiplexer. [Bina pemultipleks 8-ke-1 dengan menggunakan gabungan pemultipleks 4-ke-1 dan pemultipleks 2-ke-1.

Labelkan input, output dan pemilih dengan jelas di dalam reka bentuk anda. Jika output bagi pemultipleks 8-ke-

1 adalah F = I3, ramalkan input untuk setiap pemilih dan output untuk setiap pemultipleks.] [8 Marks/markah]

.…7/-

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Section B [Bahagian B]

Answer ANY ONE (1) question in this section. [Jawab MANA-MANA SATU (1) soalan di bahagian ini.]

Question 5 [Soalan 5]

[C5, CO4, PO2, PO11]

a) A bidirectional shift register is one in which the data can be shifted either left or right.

Determine the state of the shift register after each clock pulse for the given RIGHT/LEFT

control input waveform in Appendix A. Assume that Q0=1, Q1=1, Q2=0, and Q3=1 and that

the serial data-input line is LOW. [Daftar anjak dua arah adalah salah satu daftar di mana data boleh dianjak sama ada ke kiri atau ke kanan.

Tentukan keadaan daftar anjak selepas setiap denyutan jam bagi gelombang masukan kawalan KANAN/KIRI

dalam Lampiran A. Anggap bahawa Q0=1, Q1=1, Q2=0, dan Q3=1 serta garis masukan data bersiri adalah

RENDAH.]

[4 Marks/markah]

b) Referring to the circuit in Figure 2, construct the timing diagram in the space provided in

Appendix B, by showing the output Q (which is initially LOW). Consider also the given PRE

and CLR inputs. [Dengan merujuk kepada litar pada Rajah 2, bina rajah pemasaan dalam ruang yang disediakan pada Lampiran

B, dengan menunjukkan output Q (yang mempunyai nilai awalan RENDAH). Pertimbangkan juga input-input

PRE dan CLR.]

[6 Marks/markah]

Figure 2 [Rajah 2]

….8/-

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c) Design a synchronous counter so that it counts according to the following counting sequence.

Employ the positive edge-triggered T flip-flop. [Reka bentuk sebuah pembilang segerak supaya ia akan membilang mengikut turutan bilangan berikut. Gunakan

T flip-flop dengan pacuan pinggir positif.]

0 1 4 5 6 8 9 0…

(i) Derive the state table. [Terbitkan jadual keadaan.]

[3 Marks/markah]

(ii) Derive the simplified Boolean expression for each flip-flop using K-map. [Terbitkan ungkapan Boolean yang termudah untuk setiap flip-flop menggunakan K-map.]

[4 Marks/markah]

(iii) Construct a complete circuit. [Bina sebuah litar lengkap.]

[3 Marks/markah]

….9/-

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Question 6 [Soalan 6]

[C5, CO4, PO2, PO11]

a) Shift registers are type of sequential logic circuit consist of arrangement of flip-flops and

used in variety of applications, but two of the most important are converting number from

parallel to serial form or vice-versa and also as shift register counters. By referring to the

shift register arranged in Figure 3, show the Q outputs for the data inputs given in Appendix

C. [Daftar-daftar anjakan merupakan jenis litar logik jujukan yang terdiri daripada susunan flip-flop dan ianya

digunakan dalam pelbagai aplikasi, tetapi dua yang terpenting adalah menukar nombor daripada selari ke

bersiri atau sebaliknya dan juga sebagai pembilang-pembilang daftar anjakan. Dengan merujuk kepada

daftar-daftar anjakan yang tersusun pada Rajah 3, tunjukkan output-output Q untuk input-input data yang

diberi dalam Lampiran C.] [4 Marks/markah]

Figure 3 [Rajah 3]

.…10/-

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b) Referring to the circuit in Figure 4, construct the timing diagram in Appendix D by showing

the Q output (which is initially LOW). Consider also the given PRE and CLR inputs. [Merujuk kepada litar dalam Rajah 4, bina rajah pemasaan di dalam Lampiran D dengan menunjukkan output

Q (yang bermula dengan nilai RENDAH). Pertimbangkan juga input-input PRE dan CLR yang diberi.]

[6 Marks/markah]

Figure 4 [Rajah 4]

c) Construct the output waveforms for the signals W, X, Y and Z as indicated in Figure 5.

Assume that all of the output values are initially at 0. Use Appendix E. [Bina gelombang-gelombang output untuk isyarat W, X, Y dan Z seperti yang ditunjukkan dalam Rajah 5.

Anggapkan bahawa semua nilai output adalah berada pada nilai 0 pada awalnya. Gunakan Lampiran E.]

[10 Marks/markah]

Figure 5 [Rajah 5]

….11/-

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Appendix A: Lampiran A:

Question 5(a) Soalan 5(a)

Angka Giliran:___________________________ No. Meja: ______________________

RIGHT/

LEFT

CLK

….12/-

(right) (left) (right) (left)

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Appendix B: Lampiran B:

Question 5(b) Soalan 5(b)

Angka Giliran:___________________________ No. Meja: ______________________

….13/-

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Appendix C: Lampiran C:

Question 6(a) Soalan 6(a)

Angka Giliran:___________________________ No. Meja: ______________________

CLK

D0

D1

D2

D3

….14/-

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Appendix D: Lampiran D:

Question 6(b) Soalan 6(b)

Angka Giliran:___________________________ No. Meja: ______________________

….15/-

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Appendix E: Lampiran E:

Question 6(c) Soalan 6(c)

Angka Giliran:___________________________ No. Meja: ______________________

CLK

A

B

-oo0oo- ….16/-

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Course Outcomes (COs)

CO1 Ability to identify different numbering systems and to understand basic theory of binary

system.

CO2 Ability to apply method of minimizing Boolean functions for digital logic circuit.

CO3 Ability to design and evaluate combinational logic circuit in terms of Boolean function.

CO4 Ability to design and evaluate sequential logic circuit in terms of Boolean function.

Program Outcomes (POs)

PO 01 Ability to acquire and apply knowledge of mathematics, science, engineering and an

in-depth technical competence in computer engineering discipline to solve the

complex engineering problem

PO 02 Ability to identify, formulate and solve complex engineering problems.

PO 03 Ability to design solutions for complex engineering problems and systems,

components or processes to meet desired needs.

PO 04 Ability to conduct investigation into complex problems as well as to analyze and

interpret data.

PO 05 Ability to use techniques, skills and modern engineering tools necessary for complex

engineering practices so as to be easily adaptable to industrial needs.

PO 06 Understanding of the social, cultural, global and environmental responsibilities of a

professional engineer.

PO 07 Ability to have entrepreneurship, the process of innovation and the need for

environmental and sustainable development.

PO 08 Ability to understand the professional and ethical responsibilities and commitment to

the community.

PO 09 Ability to function on multi-disciplinary teams.

PO 10 Ability to communicate effectively on complex engineering activities with the

engineering community and with society at large

PO 11 A recognition of the need for, and an ability to engage in life-long learning

PO 12 Demonstrate the understanding of project management and finance principles