Unit_V Microcontroller_Programming___Applications.pdf

UNIT – V : MICROCONTROLLER PROGRAMMING

& APPLICATIONS

Instruction Set of 8051

An instruction is a single Operation of a Processor defined by an

Instruction set architecture. According to type of operations, the instruction set

of 8051 is classified as,

→ Data transfer instructions

→ Byte level logical instructions

→ Bit level logical instructions

→ Arithmetic instructions

→ Jump & Call instructions

Data transfer instructions:

An immediate, direct, register and indirect addressing modes are used in

different MOVE instructions.

MOV (direct), (SVC) : Move 8 bit/16 bit

1) MOV A, Rn - (A) ← (Rn)

Copy the contents of Register Rn of selected register bank to A.

2) MOV A, direct

eg: MOV A. 30 H

(A) ← direct

Copy the contents of the address specified with instructions

3) MOV A, @ Ri

(A) ← ((Ri))

Copy the contents of the address in Ri to A

4) MOV A, # data

(A) ← # data

Load the given data in the instruction to A

5) MOV Rn, A

(Rn) ← (A)

Copy the contents of A to Register Rn of selected register bank.

6) MOV Rn, direct

(Rn) ← (direct)

Copy the contents of the address to register Rn of selected register bank.

7) MOV Rn, # data

(Rn) ← # data

Load the given data in the instruction to Register Rn of the selected Register

bank.

8) MOV direct, A

(direct) ← (A)

9) MOV direct, Rn

(direct) ← (Rn)

10) MOV direct, direct

(direct) ← (direct)

Copy the contents of the address specified in the instruction to the address

specified in the instruction.

11) MOV direct, @ Ri

(direct) ← ((Ri))

12) MOV direct, # data

(direct) ← # data

13) MOV @ Ri, A

((Ri)) ← (A)

14) MOV @ Ri, direct

((Ri)) ← (direct)

15) MOV @ Ri # data

((Ri)) ← # data

16) MOV C, bit

(C) ← (bit)

17) MOV bit, C

(bit) ← (C)

Instructions to Access External Data memory

1) MOVX A, @ Ri

((Ri)) → (A)

Copy the contents of the external address in Ri to A.

2) MOVX A, @ DPTR

This instruction copies data from the 16 bit address in DPTR to A

((DPTR)) → (A)

3) MOVX A, @ Ri, A

(A) → ((Ri))

4) MOVX A, @ DPTR, A

(A) → ((DPTR))

This instruction copies the data from A to the 16 bit address in DPTR.

Important points to remember in Accessing external data memory

→ All external data moves with external RAM involve the A register

→ While accessing external RAM, Rp can access 256 bytes and DPTR

can access 64 K bytes.

→ MOVX instruction is used to access external RAM or I/o addresses

Instructions to Access External ROM/Program memory:

1) MOVC A, @ A + DPTR

Copy the contents of the external ROM address formed by adding A and

the DPTR, to A

(A) ← ((A + DPTR))

2) MOVC A, @ A + PC

Copy the contents of the external ROM address formed by adding A and

the PC, to A

(A) ← ((A + PC))

Data Transfer with Stack instructions:

1) PUSH direct “ Push onto stack

The stack pointer is incremented by one. The contents of the indicated

variable is then copied to the internal ROM location addressed by the stack

pointer. Otherwise no flags are affected

(SP) ← (SP) + 1

((SP)) ← (direct)

2. POP direct : Pop from stack

(direct) ← ((SP))

(SP) ← (SP) – 1

Data exchange instructions:

1) XCH A, RN

Exchange data bytes between register Rn and A

(A) ↔ (Rn)

2) XCH A, direct

Exchange data bytes between address directly given within instruction

and A

(A) ↔ (direct)

3) XCH A, @ Ri

Exchange data bytes between A and address in Ri

((Ri)) ↔ (A)

4) XCHD A, @ Ri

XCHD exchanges the low order nibble of the Accumulator (bits 3-0) with

that of internal RAM location indirectly addressed by the specific

Register. The higher order nibbles (7-4) of each Register are not affected.

(A) 3-0 ↔ ((Ri)) 3-0

Arithmetic Instructions:

The 8051 provides the basic mathematical operations like addition,

subtraction, multiplication, division, increment, decrement, etc.,

Only the 8-bit Operations using unsigned arithmetic are supported directly

Addition:

1) ADD A, Rn - (A) ← (A) + (Rn)

The contents of Register RN is added with the contents of Accumulator and the

result will be placed in accumulator.

2) ADD A, direct - (A) ← (A) + (direct)

3) ADD A, @ Ri - (A) ← (A) + ((Ri))

4) ADD A, # data - (A) ← (A) + # data

5) ADD C, Rn - (A) ← (A) + (C) + (Rn)

The contents of accumulator and Register Rn are added along with the carry

flag content and the result will be placed in the accumulator

6) ADD C A, direct - (A) ← (A) + (C) + (direct)

7) ADD C A, @ Ri - (A) ← (A) + (C) + ((Ri))

8) ADD C A, # data - (A) ← (A) + # data + (C)

Subtraction

1) SUBB A, Rn - (A) ← (A) - (C) - (Rn)

2) SUBB A, direct - (A) ← (A) - (C) - (direct)

3) SUBB A, @ Ri - (A) ← (A) - (C) - ((Ri))

4) SUBB A, # data - (A) ← (A) - (C) - # data

Multiplication

MUL AB

(A) x (B) → (A) 7 – 0

(B) 15 – 8

This multiplies the unsigned 8 – bit integers in the accumulator and Register B.

The Lower order byte of the 16 – bit product is left in the accumulator and the

higher order byte in Register B.

Division

DIV AB

(A) / (B) → (A) 15 - 8

(B) 7 – 0

This divides the unsigned 8-bit integers in the accumulator by the unsigned 8-bit

integer in the register B. The Accumulator Receives the integer part of

Quotient : register receives the integer remainder.

Incrementation:

1) INC A - (A) ← (A) + 1

2) INC Rn - (Rn) ← (Rn) + 1

3) INC direct - (direct) ← (direct) + 1

4) INC @ Ri - ((Ri)) ← ((Ri)) + 1

5) INC DPTR - (DPTR) ← (DPTR) + 1

Decrementation:

1) DEC A - (A) ← (A) - 1

2) DEC Rn - (Rn) ← (Rn) - 1

3) DEC @ Ri - ((Ri)) ← ((Ri)) - 1

4) DEC direct - (direct) ← (direct) - 1

DA A (Decimal Adjust Accumulator for addition)

The DA A adjusts the 8-bit value in the Accumulator, resulting from the

earlier addition of two variables (each in packed BCD formal), producing two

4-bit digits. Any ADD or ADDC instruction may have been used to perform

the addition. The algorithm followed is as follows:-

1) If the value of the lower ribble in ACC is greater than 9, or if AC flag

is set, then 6 is added to Acc

2) If the value of higher ribbe is now greater than 9, or if CY flag is set, then

6 is added to the higher ribble of ACC

All flags are affected

If [[(A3 – 0) › 9] V [(AC) =1]]

Then (A3 – 0) ← (A3 – 0) + 6

and,

If [[(A7 – 4) › 9] V [(C) =1]]

Then, (A7 – 4) ← (A7 – 4) + 6

Logical Instructions:

1) CLR A clear Accumulator)

The Accumulator is cleared (all bits set to 0). No flags are affected

(A) ← D

2) CLR bit (Clear bit)

The indicated bit is cleared. No other flags are affected. CLR can

operate on the carry flag or any other directly addressable bit.

CLR C ─ (c) ← 0

3. SET B C ─ (c) ← 0

4. CPL A (Complement Accumulator)

Each bit of the Accumulator is logically complemented (1st complement).

No flags are affected.

(A) ← (A)

5. CPL bit (Complement bit)

CPL C

← (C)

6. RL A (Rotate Accumulator left)

The eight bits in the Accumulator are rotated 1 bit to the left. Bit 7 is

rotated into the bit 0 position. No flats are affected.

(An + 1) ← (An) , n = 0 - 6

(Ao) ← (A7)

7. RLC A (Rotate Accumulator left though the carry flag)

(An + 1) ← (An)

(Ao) ← (C)

(C) ← (A7)

The eight bits in the Accumulator and the Carry flag are together rotated 1 bit to

the left.

8. RR A (Rotate Accumulator Right)

(An) ← (An + 1)

9. RRC A (Rotate Accumulator Right through Carry flag)

(An) ← (An + 1)

(A7) ← (C)

← (Ao)

10. SWAP A (Swap nibbles within the Accumulator)

This interchanges the low and higher order nibbles (4 – bit) of the

accumulator. No flags are affected.

(A 3-0) ↔ (A7-4)

11. Logical AND for byte Variables

1) ANL A, Rn - (A) ← (A) Λ (Rn)

2) ANL A, direct - (A) ← (A) Λ (direct)

3) ANL A, @ Ri - (A) ← (A) Λ ((Ri))

4) ANL A, # data - (A) ← (A) Λ # data

5) ANL direct, A - (direct) ← (direct) Λ (A)

6) ANL A, # data - (direct) ← (direct) Λ # data

7) ANL C, bit - (C) ← (C) Λ (bit)

8) ANL C, / bit - (C) ← (C) Λ (bit)

12. Logical OR for byte Variables.

ORL A, Rn - (A) ← (A) ۷ (Rn)

ORL A, direct - (A) ← (A) ۷ (direct)

ORL A, @ Ri - (A) ← (A) ۷ ((Ri))

ORL A, # data - (A) ← (A) ۷ # data

ORL direct, A - (direct) ← (direct) ۷ (A)

ORL direct, # data - (direct) ← (direct) ۷ # data

ORL C, bit - (C) ← (C) ۷ (bit)

ORL C, / bit - (C) ← (C) ۷ (bit)

13. Logical XOR for byte Variables

XRL A, Rn - (A) ← (A) ۷ (Rn)

XRL A, direct - (A) ← (A) ۷ (direct)

XRL A, @ Ri - (A) ← (A) ۷ ((Ri))

XRL A, # data - (A) ← (A) ۷ # data

XRL A direct, A - (direct) ← (direct) ۷ (A)

XRL direct, # data - (direct) ← (direct) ۷ # data

Control Transfer Instructions:

There are three classes of Control transfer Operations

1) Unconditional Calls, jumps, returns

2) Conditional Jumps

3) Interrupts

Unconditional Calls, returns and jumps:

1) A CALL addr (Absolute call)

(PC) ← (PC) + 2

(SP) ← (SP) + 1

((SP)) ← (PC 7-0)

(SP) ← (SP) + 1

((SP)) ← (P(15-8)

(PC 10-0) ← Page address

ACALL unconditionally calls a subroutine located at the indicated address.

Since ACALL is a 2-byte instruction, PC is incremented by 2 to point the next

instruction.

2) LCALL addr (Long Call)

This LCALL is Calls a subroutine located at the indicate address. Since it

is a 3-byte instruction, PC is incremented by 3 to point to the next instruction.

(PC) ← (PC) + 3

(SP) ← (SP) + 1

((SP)) ← (PC 7-0)

(SP) ← (SP) + 1)

((SP)) ← (P(15-8)

(PC) ← address 15 – 0

3) RET (Return from Subroutine)

The Return Pops the return address from the stack and load into the PC.

Program Execution continues at the resulting address. No flags are affected.

(P(15-8) ← ((SP))

(SP) ← (SP) - 1

(P(7-0) ← ((SP)

-11-

(SP) ← (SP) – 1)

4. RETI (Return from Interrupt)

The RETI Pops the return address from the stack and loads into the PC

and restores the interrupt logic to accept additional interrupts at the same

priority level as the one just processed Program execution continues at the

resulting address.

(P(15-8) ← ((SP))

(SP) ← (SP) - 1

(P(7-0) ← ((SP)

(SP) ← (SP) – 1)

5. AJMP addr. (Absolute Jump)

(PC) ← (PC) + 2

(P(10-6) ← Page Address.

6. LJMP addr (Long Jump)

(PC) ← addr 15 – 0

7. SJMP rel (Short Jump)

Program control branches unconditionally to the address indicated the

branch destination is computed by adding the signed displacement in the 2nd

ins.

byte to the PC, after incrementing PC twice.

(PC) ← (PC) + 2

(PC) ← (PC) + rel.

8. JMP @ A, DPTR (Jump Direct)

(PC) ← (A) + (DPTR)

9. NOP (No Operation)

Execution continues at the following instruction. Other than PC, no

registers or flags are affected

(PC) ← (PC) + 1

Conditional Jumps:

1) JB bit, rel (Jump if bit set)

If the indicated bit is a 1, Jump to the address indicated: Otherwise

proceed with the next instruction.

(PC) ← (PC) + 3

if (bit) = 1

then,

(PC) ← (PC) + rel.

2) JBC bit, rel (Jump if bit is set and clear bit)

(PC) ← (PC) + 3

if (bit) = 1

then

(bit) ← 0

(PC) ← (PC) + rel.

3. JC rel (Jump if carry is set)

(PC)←(PC)+2

If (C)=1

Then, (PC)←(PC)+rel

4. JNB bit, rel (Jump if bit not set)

(PC)←(PC)+3

If (bit)=0


5. JNC rel (jump if carry not set)

(PC)←(PC)+2

If (C)=0


6. JNZ rel (jump if accumulator not zero)

(PC)←(PC)+2

If (A)≠0


7. JZ rel (Jump if accumulator zero)

(PC)←(PC)+2

If (A)=0


8. CJNE (compare and jump if not equal)

CJNE A, direct, rel

(PC)←(PC)+3

If (direct)<(A)

Then, (PC)←(PC)+rel and (C)←0

Or

If (direct)>(A)


CJNE A, #data, rel

(PC)←(PC)+3

If #data<(A)


Or

If #data>(A)


CJNE Rn, #data, rel

(PC)←(PC)+3

If #data<(Rn)


Or

If #data>(Rn)


CJNE @R, #data, rel

(PC)←(PC)+3

If #data<((Ri))


Or

If (direct)>(A)


9. DJNZ (decrement and jump if not zero)

DJNZ Rn, rel

(PC)←(PC)+2

(Rn)←(Rn)-1

If (Rn)>0 or (Rn)<0


DJNZ direct, rel

(PC)←(PC)+2

(direct)←(direct)-1

If (direct)>0 or (direct)<0


Microcontroller applications:

Keyboard interface:

Here eight keys are individually connected to specific pins of port P1. Each port

pin gives the status of key connected to the pin. When port pin is logic 1, key is

open otherwise key is closed

Software routine to get keycode with key debounce:

START MOV A, P1 Read key status

CJNE, A, #FFH, START Check if keys are open

PRO LCALL DEBOUNCE_DELAY Call debounce delay

AGAIN MOV A, P1 Read key status

CJNE A, #FFH PRO1 Check if any key is processed

LJMP AGAIN If no goto AGAIN otherwise

continue

PRO1 LCALL DEBOUNCE_DELAY Call debounce delay

MOV A, P1 Get key code

RET Return from subroutine

This program reads status of all keys by getting data through P1 and

composes it with FFH to check whether all keys are open. If all keys are open

instruction compare sets the zero flag and the program waits for key debounce

Matrix keyboard interface:

In simple keyboard interface one input line is required to interface one

key and this number will increase with number of keys. Such technique is not

suitable when it is necessary to interface large number of keys. To reduce

number of connections keys are arranged in the matrix form as shown in the

following figure

The figure shows the sixteen keys arranged in four rows and four

columns. When keys are open row and column don’t have any connections.

When a key is pressed it shows corresponding one row and one column.

This matrix keyboard requires eight lines to make all connections instead

of the sixteen lines required if the keys are connected individually

The following figure shows the interfacing of matrix keyboard it requires

two ports an input port and an output port

The following sections explain the steps required to identify pressed key.

Check 1: whether any key is pressed or not

Make all column lines zero by sending low on all output lines. This

activates all keys in the keyboard matrix

Read the status of return lines. If the status of all lines is high key is not

pressed otherwise key is pressed

Check 2:

Activate keys from any one column by making any column line zero

Read the status of return lines. The zero on any one return line indicates

key is pressed from the corresponding row and selected column. If the

status of all lines is logic high key is not pressed from that column

Activate keys from the next column and repeat 2 and 3 for all the

columns

The steps in algorithm are as follows:

Initialize P1.0, P1.1, P1.2, P1.3 as inputs ie., write ‘1’ to these prior

Key check: check if all the keys are released by writing ‘0’ to P1.4-P1.7

and check if all the return lines are in state ‘1’. If NO then wait. If YES

then goto step 3

Call debounce

Wait for key closure. Ground all scan lines by writing ‘0’ and then check

if atleast one of return lines shows ‘0’ level

Key pressed? No step 4

Yes step 5

Call debounce (allow sufficient time for debounce)

Is key really pressed?

No step 4

Yes step 7

Find keycode and display the key pressed on 7 segment display

Program:

Org lookup_table_address

Db 30h, 31h, 32h, 33h, 34h, 35h, 36h, 37h, 38h, 39h, 41h, 42h, 43h, 44h,

45h, 46h

Org program-start-address

beg: MOV P1, #ofh

MOV dptr, #lookup_table_address

aga: MOV a, P1

anl a, #ofh

cjne a, #ofh, aga

1 call delay

aga1: MOV a, P1

anl a, #ofh

cjne a, #ofh, go

1 jmp aga1

go: 1 call delay

MOV a, P1

anl a, #ofh

cjne a, #ofh, go1

1 jump aga1

go1: MOV r1, #01h

MOV r0, #0efh

MOV r3, #04h

aga3: MOV P1 , r0

MOV a, P1

jnb acc.0, display

inc dptr

jnb acc.1, display

inc dptr

jnb acc.2, display

inc dptr

jnb acc.3, display

inc dptr

MOV a, r0

r1 a

MOV r0, a

djnz r3, aga3

1jmp beg

end

Display interface:

LED interfacing:

Sourcing current: it refers to the maximum current that the 8051 port pin can

supply to drive on externally connected device. The device can be an LED, a

buzzer or TTL logic device. For TTL family of 8051 devices the sourcing

current is approximately 60µA

Sinking current: it refers to the maximum current if the 8085 pin can absorb

through a device which is connect to an external supply. Pins of P1, P2 and P3

can sink a maximum current of 1.6mA. Port 0 can sink current upto 3.2mA

A typical LED consumes 10 to 15 mA. Thus we cannot drive LED

directly in current source mode. However we can drive LED directly in current

sink mode

We can use driver transistor to solve the problem of current sinking and

sourcing

ALP to flash the LED connected to port 2.0:

ORG 0000H

BACK: SET B P2.0

ACALL delay

CLR P2.0

ACALL delay

SJMP BACK

Multiplexed 7 segment display interfacing:

Seven segment displays are generally used as numerical indicators and

consists of a number of LED’s arranged in seven segments.

Any number between 0 and 9 can be indicated by lighting the appropriate

segments

The seven segments are labeled a to g and dot is labeled as h. by forward

biasing different LED segments we can display the digits 0 through 9. These 7

segment displays are of two types

Common anode type

Common cathode type

In common anode type all anodes of LEDs are connected together. In

common cathode are connected together

Fig. Commom Anode Type

Subroutine to display message:

Mov R0, #8H

Mov R1, #7Fh

Mov OPTR, #6000H

AGAIN: Mov P3, R1

Mov A, @DPTR

Mov P1, A

LCALL DELAY

Mov A, R1

RR A

Mov R1, A

INC DPTR

DJNZ R0, AGAIN

RET

Closed loop control of servo motor:

A servo motor is a special type of DC motor to which position or velocity

feedback gravity has been added to implement a closed loop control system like

the DC motor, the seno motor can rotate in either direction however generally

the range is less than 360 degrees

The function of servo motor is to receive a control signal that represents a

derived output position of a seno shaft and apply power to its DC motor until its

shaft runs to that position. It uses the position sensing device to determine the

rotational position of the shaft. so it knows which way the motor must turn to

move the shaft to the commanded position.

The servo motor has 3 wire connection: Power, Ground and control;

The power source must be constantly applied, the seno has its own power

electronics that d4aw current from the power lead to drive the motor.

The control signal is pulse width modulated (PWM) but here the duration

of the signal which is positive gaining determines the position of the seno shaft.

There are two important differences between the control pulse of servo

motor versus the DC motor. First, in the Servo motor, duty cycle has no

meaning whatsoever, all that matter is the absolute duration of the positive

gaining pulse, which corresponds to a commanded output position of the servo

shaft. Second, the seno has its own power electronics, so very little power

flows over the control signal.

The following figure shows the microcontroller based closed loop, servo

motor control Gravity. These systems control a motor with an incremental feed

back device known as a sequential encoder.

They consists of an encoder Counter, microcontroller some form of D/A

Converter, and a Power amplifier which delivers current or voltage to the motor.

The D/A conversion can be handled by a conventional DAC or by using

the microcontroller’s pulse wide modulation. The amplifier can be configured

to supply a Control Voltage or current to the motor. Most embedded system

use Voltage output because its simpler and cheaper.

The encoder signals are usually decoded into count up and count down

pulses.

Stepper motor control

A stepper motor is a digital motor. It can be driven by digital signal. The

following figure shows the typhical 3 phase motor interfaced using 8051.

Motor shown in the circuit has two phases, with center tap winding. The Center

taps of these windings are connected to the 12 V supply. Due to this, motor can

be excited by grounding four terminals of the two windings. Motor can be

rotated in steps by giving proper excitation sequence to these windings.

The following tables shows the typical excitation sequences. The given

excitation sequences rotates the motor in clockwise direction. In full step

sequence excitation ends of the sphase are changed in one step.

In half step sequence, it takes two steps to change excitation ends of the phase

Step X1 X2 Y1 Y2

1 0 1 0 1

2 1 0 0 1

3 1 0 1 0

4 0 1 1 0

1 0 1 0 1

Table: Full step excitation sequence

Step X1 X2 Y1 Y2

1 0 1 0 1

2 0 0 0 1

3 1 0 0 1

4 1 0 0 0

5 1 0 1 0

6 0 0 1 0

7. 0 1 1 0

8 0 1 0 0

1 0 1 0 1

Table: Half step excitation sequence

Program:

MOV Ro, # COUNT

AGAIN MOV DPTR, # ETC

MOV R1, # 04

BACK MOVX A, @ DPTR

MOV P1, A

LCALL DELAY

INC DPTR

DJNZ R1, BACK

DJNZ Ro, AGAIN

RET

ORG 3000H

ETC DB 03H, 06H , 09H, OCH

Washing Machine Control

let us assume that the Washing machine has the following control options

Prewash

Main Wash 1

Main wash 2

Rinse 1

Rinse 2

Graduated spin

Spin

The user can select option to prewash or main wash 1 to indicate the initial state

for the wash. When the start button is pressed, the cycle begins in the selected

initial state. The machine has a program control to indicate the kind of fabrics

being washed: Cotton or woolen. Finally, the programme advances directly to

spin skipping the graduated spin.

Pin Name Pin

Prewash

Main Wash 1

Main Wash 2

Rinse 1

Rinse 2

Graduated spin

Spin

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

Program:

SMRT : JNB P0.0, START

JNB P0.1, SKIPPW

SETB P1.0

CALL D – PREWASH

CLRB P1.0

SKIPPW SETB P1.1

CALL D- MAINWASH 1

CLRB P1.1

JNB P0.2, SKIPPW

SET B P1.2

CALL D – MAIN WASH 2

CLR B P1.2

SKIP MW2 SETB P1.3

CALL D – RINSE 1

CLR B P1.3

JNB P0.2, SKIP RINSE 2

SET B P1.4

CALL D-RINSE 2

CLR B P1.4

JNB P0.2, SKIP GS

SET B P1.5

CALL D- GS

CLRB P1.5

SKIP GS SET B 1.6

CALL D – SPIN

CLRB P1.6

LJMP START

Unit_V Microcontroller_Programming___Applications.pdf

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