Unitii Armarchitecture 130305014346 Phpapp01

7/25/2019 Unitii Armarchitecture 130305014346 Phpapp01

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Dr.Y.Narasimha [email protected]

UNIT-II ARM 7 Microcontroller

INTRODUCTION:

The ARM was originally developed at Acorn Computers Limited of Cambridge , England,

between 1!" and 1!#$ %t was the first R%&C microprocessor developed for commercial use and

has some significant differences from subse'uent R%&C architectures$ %n 1( ARM Limited

was established as a separate company specifically to widen the e)ploitation of ARM technology

and it is established as a mar*et+leader for low+power and cost+sensitive embedded

applications$ The ARM is supported by a tool*it which includes an instruction set emulator for

hardware modelling and software testing and benchmar*ing, an assembler, C and C compilers,

a lin*er and a symbolic debugger$

The 1-+bit C%&C microprocessors that were available in 1!" were slower than standard memory

parts$ They also had instructions that too* many cloc* cycles to complete .in some cases, many

hundreds of cloc* cycles/, giving them very long interrupt latencies$As a result of these

frustrations with the commercial microprocessor offerings, the design of a proprietary

microprocessor was considered and ARM chip was designed$

ARM 7TDMI-S Processor : The ARM0TM%+& processor is a member of the ARM

family of general+purpose "2+bit microprocessors$ The ARM family offers high performance for

very low+power consumption and gate count$ The ARM0TM%+& processor has a 3on 4eumann

architecture, with a single "2+bit data bus carrying both instructions and data$ 5nly load, store,

and swap instructions can access data from memory$ The ARM0TM%+& processor uses a three

stage pipeline to increase the speed of the flow of instructions to the processor$ This enables

several operations to ta*e place simultaneously, and the processing, and memory systems to

operate continuously$ %n the three+stage pipeline the instructions are e)ecuted in three stages$

The three stage pipelined architecture of the ARM0 processor is shown in the above figure$

1


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ARM7TDMIS stands for

T6 T78M9 :

D for on+chip ebug support, enabling the processor to halt in response to a debug re'uest,

M6 enhanced Multiplier, yield a full -;+bit result, high performance

I6 Embedded %CE hardware .%n Circuit emulator/

S :&ynthesi


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resources are limited$ The ?a


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ARM Re$isters : ARM has a total of "0 registers $%n which + "1 are general+purpose registers

of "2+bits, and si) status registers $9ut all these registers are not seen at once$ The processor

state and operating mode decide which registers are available to the programmer$ At any time,

among the "1 general purpose registers only 1- registers are available to the user$ The remaining

1# registers are used to speed up e)ception processing$ there are two program status registers6

C&R and &&R.the current and saved program status registers, respectively

%n ARM state the registers r( to r1"are orthogonalBany instruction that you can apply to r(you

can e'ually well apply to any of the other registers.

The main ban* of 1- registers is used by all unprivileged code$ These are the 8ser mode

registers$ 8ser mode is different from all other modes as it is unprivileged$ %n addition to this

register ban* ,there is also one "2+bit Current rogram status Register.C&R/

#


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%n the 1# registers ,the r1" acts as a stac* pointer register and r1; acts as a lin* register and r1#

acts as a program counter register$

Register r1" is the sp register ,and it is used to store the address of the stac* top$ R1" is used by

the 8&7 and 5 instructions in T variants, and by the &R& and RE instructions from

ARMv-$

Register 1; is the Lin* Register.LR/$ This register holds the address of the ne)t instruction after

a 9ranch and Lin* .9L or 9LD/ instruction, which is the instruction used to ma*e a subroutine

call$ %t is also used for return address information on entry to e)ception modes$ At all other times,

R1; can be used as a general+purpose register$

Register 1# is the rogram Counter .C/$ %t can be used in most instructions as a pointer to the

instruction which is two instructions after the instruction being e)ecuted.

The remaining 1" registers have no special hardware purpose .

C#SR6 The ARM core uses the C&R register to monitor and control internal operations$ The

C&R is a dedicated "2+bit register and resides in the register file$ The C&R is divided into

four fields, each of ! bits wide 6 flags, status, e)tension, and control$ The e)tension and status

fields are reserved for future use$ The control field contains the processor mode, state, and

interrupt mas* bits$ The flags field contains the condition flags$ The "2+bit C&R register is

shown below$

$


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#rocessor Modes:There are seven processor modes $&i) privileged modes abort, fast interrupt

re'uest, interrupt re'uest, supervisor, system, and undefined and one non+privileged mode

called user mode$

The processor enters abort mode when there is a failed attempt to access memory$ ast interrupt

re'uest and interrupt re'uest modes correspond to the two interrupt levels available on the ARM

processor$ &upervisor mode is the mode that the processor is in after reset and is generally the

mode that an operating system *ernel operates in$ &ystem mode is a special version of user mode

that allows full read+write access to the C&R$ 8ndefined mode is used when the processor

encounters an instruction that is undefined or not supported by the implementation$ 8ser mode is

used for programs and applications$

'an(ed Re$isters : 5ut of the "2 registers , 2( registers are hidden from a program at different

times$ These registers are called ban*ed registers and are identified by the shading in the

diagram$ They are available only when the processor is in a particular mode: for e)ample, abort

mode has ban*ed registers r1"abt , r1;abt and spsr abt$ 9an*ed registers of a particular

mode are denoted by an underline character post+fi)ed to the mode mnemonic or mode$

Fhen the T bit is 1, then the processor is in Thumb state$ To change states the core e)ecutes a

speciali


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instruction i$e identifies the instruction to be e)ecuted and finally E)ecutes the instruction and

writes the result bac* to a register$

The ARM0 processor has a three stage pipelining architecture namely etch , ecode and

E)ecute$And the ARM has five stage ipe line architecture$The three stage pipelining is

e)plained as below$

To e)plain the pipelining ,let us consider that there are three instructions Compare, &ubtract and

Add$The ARM0 processor fetches the first instruction CM in the first cycle and during the

second cycle it decodes the CM instruction and at the same time it will fetch the &89

instruction$ uring the third cycle it e)ecutes the CM instruction , while decoding the &89

instruction and also at the same time will fetch the third instruction A$ This will improve the

speed of operation$ This leads to the concept of parallel processing $This pipeline e)ample is

shown in the following diagram$

&


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As the pipeline length increases, the amount of wor* done at each stage is reduced, which allows

the processor to attain a higher operating fre'uency$ This in turn increases the performance$ 5ne

important feature of this pipeline is the e)ecution of a branch instruction or branching by the

direct modification of the Ccauses the ARM core to flush its pipeline$

Exceptions, Interrupts, and te !ector Ta"#e :

E)ceptions are generated by internal and e)ternal sources to cause the ARM processor to handle

an event, such as an e)ternally generated interrupt or an attempt to e)ecute an 8ndefined

instruction$ The processor state Just before handling the e)ception is normally preserved so that

the original program can be resumed after the completion of the e)ception routine$ More than

one e)ception can arise at the same time$ARM e)ceptions may be considered in three groups

1$ E)ceptions generated as the direct effect of e)ecuting an instruction$&oftware interrupts,

undefined instructions .including coprocessor instructions where the re'uested coprocessor is

absent/ and prefetch aborts .instructions that are invalid due to a memory fault occurring during

fetch/ come under this group$

2$ E)ceptions generated as a side+effect of an instruction$ata aborts .a memory fault during a

load or store data access/ are in this group$

"$ E)ceptions generated e)ternally, unrelated to the instruction flow$Reset, %RH and %H are in

this group$

The ARM architecture supports seven types of e)ceptions$

i$Reset

ii$8ndefined %nstruction

iii$&oftware %nterrupt.&F%/

iv$ re+fetch abort.%nstruction etch memory fault/

v$ata abort .ata access memory fault/

vi$ %RH.normal %nterrupt/

vii$ %H .ast %nterrupt re'uest/$

Fhen an E)ception occurs , the processor performs the following se'uence of actions6

K %t changes to the operating mode corresponding to the particular e)ception$

K %t saves the address of the instruction following the e)ception entry instruction in r1; of the

new mode$

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K %t saves the old value of the C&R in the &&R of the new mode$

K %t disables %RHs by setting bit 0 of the C&R and, if the e)ception is a fast interrupt, disables

further fast interrupts by setting bit - of the C&R$

K %t forces the C to begin e)ecuting at the relevant vector address

!*cd+tion , Interru+t Na%e Address i$h Address

Reset RE&ET (D(((((((( (Dffff((((

8ndefined %nstruction 84E (D(((((((; (Dffff(((;

&oftware %nterrupt &F% (D(((((((! (Dffff(((!

re+fetch Abort A9T (D(((((((C (Dffff(((c

ata Abort A9T (D((((((1( (Dffff((1(

Reserved +++ (D((((((1; (Dffff((1;

%nterrupt Re'uest %RH (D((((((1! (Dffff((1!

ast %nterrupt Re'uest %H (D((((((1C (Dffff((1c

The e)ception 3ector table shown above gives the address of the subroutine program to be

e)ecuted when the e)ception or interrupt occurs$ Each vector table entry contains a form of

branch instruction pointing to the start of a specific routine$

Reset vector is the location of the first instruction e)ecuted by the processor when power is

applied$ This instruction branches to the initiali


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designs$ The ascending number indicates an increase in performance and sophistication$

Though ARM ! was introduced during 1-, it is no more available in the mar*et$ The

following table gives a brief comparison of their performance and available resources$

The ARM0 core has a 3on 4eumann>style architecture, where both data and instructions use the

same bus$ The core has a three+stage pipeline and e)ecutes the architecture ARMv;T instruction

set$ The ARM0TM% was introduced in 1# by ARM$ %t is currently a very popular core and is

used in many "2+bit embedded processors$

The ARM family was released in 10$ %t has five stage pipeline architecture $7ence , the

ARM processor can run at higher cloc* fre'uencies than the ARM0 family$ The e)tra stages

improve the overall performance of the processor$ The memory system has been redesigned to

follow the 7arvard architecture, with separate data and instruction $buses$ The first processor in

the ARM family was the ARM2(T, which includes a separate % cache and an MM8$ This

processor can be used by operating systems re'uiring virtual memory support$ ARM22T is a

variation on the ARM2(T but with half the %cache si


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ARM

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ARM0 1# 3on 4eumann " stage !( M$7< !)"2 ($0

ARM 10 7arvard # stage 1#(M$7< !)"2 1$1ARM1

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1 7arvard - stage 2-(M$7< 1-)"2 1$"

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ARM INSTRUCTION S!T

ARM instructions process data held in registers and only access memory with load and store

instructions$ ARM instructions commonly ta*e two or three operands$or e)ample ,the A instruction adds the two values stored in registers r1and r2.the source

registers/$ %t stores the result to register r".the destination register/$ ADD r/0 r10 r2

ARM instructions are classified into data processing instructions, branch instructions, load+store

instructions, software interrupt instruction, and program status register instructions$

Data #rocessin$ Instructions :

The data processing instructions manipulate data within registers$ They are move instructions,Arithmetic instructions, logical instructions, comparison instructions, and multiply instructions$

Most data processing instructions can process one of their operands using the barrel shifter$

ata processing instructions are processed within the arithmetic logic unit .AL8/$ A uni'ue and

powerful feature of the ARM processor is the ability to shift the "2+bit binary pattern in one of

the source registers left or right by a specific number of positions before it enters the AL8$ This

shift increases the power and fle)ibility of many data processing operations.

There are data processing instructions that do not use the barrel shift, for e)ample, the M8L

.multiply/, CLI .count leading


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i.Mo3e Instructions : Move instruction copies R into a destination register Rd, where Ris a

register or immediate value$ This instruction is useful for setting initial values and transferring

data between registers$

!*a%+le1 : #R! r# G #

r0 G !

MO4 r70 r5 6

#OST r# G #

r0 G #

The M53 instruction ta*es the contents of register r#and copies them into register r0$

E)ample 26 M53& r(, r1, L&L 1

M53& instruction shifts register r1 left by one bit

Arith%etic Instructions :The arithmetic instructions implement addition and subtraction of

"2+bit signed and unsigned values$ the various addition and subtraction instructions are given intable below$

&89 r(, r1, r2 : This subtract instruction subtracts a value stored in register r2from a value

stored in register r1$ The result is stored in register r($

R&9 r(, r1, ( : This reverse subtract instruction .R&9/ subtracts r1from the constant value (, writing$ the result to r($ Nou can use this instruction to negate numbers$

&89& r1, r1, 1 : The &89& instruction is useful for decrementing loop counters$ %n this

e)ample we subtract the immediate value one from the value one stored in

register r1$ The result value


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)o$ical Instructions : TheseLogical instructions perform bitwise logical operations on the two

source registers$

9%C r(, r1, r2 : 9%C, carries out a logical bit clear$ register r2contains a binary pattern where

every binary 1 in r2 clears a corresponding bit location in register r1$ This instruction is

particularly useful when clearing status bits and is fre'uently used to change interrupt mas*s in

the cpsr$

Co$parison Instructions : The comparison instructions are used to compare or test aregister with a "2+bit value$ This instruction affects only C&R register flags$

'ranch Instructions: A branch instruction changes the normal flow of e)ecution of a main

program or is used to call a subroutine routine$ This type of instruction allows programs to have

subroutines, if+then+else structures, and loops$ The change of e)ecution flow forces the program

counterpc to point to a new address$*+ample 1 , for-ar / 0ucoitioal 2rach to for-ar3

ADD r14 r!4 5# /

ADD r)4 r%4 5! /

ADD r"4 r&4 5# /

for-ar S6, r14 r!4 5# /

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Similarly ,ac7-ar 2rach

2ac7-ar ADD r14 r!4 5# /

S6, r14 r!4 5# /

ADD r#4 r%4 r& /

, 2ac7-ar / 2rach to the tar8et

2ac7-ar.

The 2rach -ith li74 or ,94 istructio is similar to the , istructio 2ut over-rites

the

li7 re8ister lr-ith a retur aress. It performs a su2routie call.

,9 su2routie / 2rach to su2routie

CMP r14 5$ / compare r1 -ith $

M:;*< r14 5) / if 0r1==$3 the r1 = )

Su2routie

M:; pc4 lr / retur 2y movi8 pc = lr

The ,rach *+cha8e 0,>3 a ,rach *+cha8e -ith 9i7 0,9>3 are the thir type

of 2rach istructio. The ,> istructio uses a a2solute aress store i re8ister

Rm. It is primarily use to 2rach to a from Thum2 coe. The T 2it i the cpsr is

upate 2y the least si8i?cat 2it of the 2rach re8ister. Similarly the ,9>

istructio upates the T 2it of the cpsr-ith the least si8i?cat 2it a aitioally

sets the li7 re8ister -ith the retur aress.

The etails of the 2rach istructios are 8ive i the ta2le a2ove.

1#


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)oad-Store Instructions: 9oastore istructios trasfer ata 2et-ee memory a

processor re8isters. There are three types of loastore istructios

Si8lere8ister trasfer

Multiplere8ister trasfer4 a

S-ap.Sin%#e-Re%ister Trans&er : These istructios are use for movi8 a si8le ata

item i a out of a re8ister. The ata types supporte are si8e a usi8e

-ors 0"!2it34 half-ors 01%2it34 a 2ytes. *+1 STR r)4 r1B / = STR r)4 r14

5)B / store the cotets of re8ister r) to the

memory aress poite to 2y re8ister r1.

*+! 9DR r)4 r1B / = 9DR r)4 r14 5)B / loa re8ister r) -ith the cotets of the

memory aress poite to 2y re8ister r1.

Multi+le-Re$ister Transfer : Load+store multiple instructions can transfer multiple registers

between memory and the processor in a single instruction$ The transfer occurs from a base

address register Rnpointing into memory$ Multiple+register transfer instructions are more

efficient than single+register transfers for moving bloc*s of data around memory and saving and

restoring conte)t and stac*s$

Load+store multiple instructions can increase interrupt latency$ ARM implementations do not

usually interrupt instructions while they are e)ecuting$ or e)ample, on an ARM0 a load multiple

instruction ta*es 2 4$tcycles, where 4is the number of registers to load and t is the number of

cycles re'uired for each se'uential access to memory$ %f an interrupt has been raised, then it has

no effect until the load+store multiple instruction is complete$

E)ample 16 LM%A r(O, Pr1+r"Q : %n this e)ample, register r( is the base register Rn and is

followed by O, indicating that the register is updated after the instruction is e)ecuted$ %n this case

the range is from register r1to r"$

1$


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E)ample 2 6 LM%9 6 load multiple and increment before

E) "6 LM%9 r(O, Pr1+r"Q :

E) ; 6 LMA r(O, Pr1+r"Q

Stac( O+erations : The ARM architecture uses the load+store multiple instructions to carry out

stac* operations$ The pop operation .removing data from a stac*/ uses a load multiple

instruction: similarly, the push operation .placing data onto the stac*/ uses a store multiple

instruction$

A stac* is either ascending .A/ or descending ./$ Ascending stac*s grow towards higher

memory addresses: in contrast, descending stac*s which grow towards lower memory addresses$

Fhen a full stac* ./is used , the stac* pointer sppoints to an address that is the last used or full

location .i$e$, sppoints to the last item on the stac*/$ %n contrast, if an empty stac* .E/ is used ,

the sppoints to an address that is the first unused or empty location .i$e$, it points after the last

item on the stac*/$

E)ample1 6 The &TM instruction pushes registers onto the stac*, updating the sp$

&TM spO , Pr1,r;Q: &tore Multiple ull escending &tac*

#R! r1 G ()(((((((2

r; G ()((((((("

sp G ()(((!((1;

POST r1 = )+)))))))!

r# = )+)))))))"

sp = )+)))')))c.

The stac7 operatio is sho- 2y the follo-i8 ia8ram.

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E)ample26 The &TME instruction pushes the registers onto the stac* but updates register spto

point to the ne)t empty location as shown in the below diagram$$

#R! r1 G ()(((((((2

r; G ()((((((("

sp G ()(((!((1(

&TME spO , Pr1,r;Q : &tore Multiple Empty escending &tac*

#OST r1 G ()(((((((2

r; G ()((((((("

sp G ()(((!(((!

This operation is e)plained in the following figure$

Sa+ Instruction :

The &wap instruction is a special case of a load+store instruction$ %t swaps .&imilar to e)change/

the contents of memory with the contents of a register$ This instruction is an atomic operationBit

reads and writes a location in the same bus operation, preventing any other instruction from

reading or writing to that location until it completes$&wap cannot be interrupted by any other

instruction or any other bus access$ &o, the system holds the busS until the transaction is

complete$

E) 16 &F 6 &wap a word between memory and a register tmp = mem32[Rn]

mem"2RnU GRm Rd G tmp

1&


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E)2 6 &F9 &wap a byte between memory and a register tmp G mem!RnU

mem!RnU GRm Rd G tmp$

E) "6 &F r(, r1, r2U : The swap instruction loads a word from memory into register

r( and overwrites the memory with register r1$

Softare Interru+t Instruction : A software interrupt instruction .&F%/ is used to generate a

software interrupt e)ception, which can be used to call operating system routines$Fhen the

processor e)ecutes an &F% instruction, it sets the program counter pc to the offset ()! in the

vector table$ The instruction also forces the processor mode to &3C, which allows an operating

system routine to be called in a privileged mode$ Each &F% instruction has an associated &F%

number, which is used to represent a particular function call or feature$

!*: ()((((!((( &F% ()12";#-

7ere ()12";#-, is the &F% number used by ARM tool*its as a debugging &F%$ Typically

the &F% instruction is e)ecuted in user mode.

#ro$ra% Status Re$ister Instructions : There are two instructions available to directly control

a program status register .&R/$ The MR& instruction transfers the contents of either the C&R

or &&Rinto a register$&imilarly the M&R instruction transfers the contents of a register into the

C&R or &&R $These instructions together are used to read and write the C&Rand &&R$

MR& 6 copy program status register to a general+purpose register , RdG &R

M&R 6 move a general+purpose register to a program status register, &RfieldUGRm

M&R 6 move an immediate value to a program status register,&RfieldUGimmediate

E) 6 MR& r1, C&R

9%C r1, r1, ()!( : (b(1((((((

M&R C&RC, r1$

1'


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The M&R first copies the C&Rinto register r1$ The 9%C instruction clears bit 0 of r1$ Register

r1is then copied bac* into the C&R, which enables %RH interrupts$ 7ere the code preserves all

the other settings in the C&R intact and only modifies the %bit in the control field$

)oadin$ Constants : %n ARM instruction set there are no instructions to move the "2+bit

constant into a register$ &ince ARM instructions are "2 bits in si


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reduced$ Code density was the main driving force for the Thumb instruction set$ 9ecause it was

also designed as a compiler target, rather than for hand+written assembly code$ 9elow e)ample

e)plains the difference between ARM and Thumb code

rom the above e)ample it is clear that the Thumb code is more denser than the ARM code$

E)ceptions generated during Thumb e)ecution switch to ARM e)ecution before e)ecuting the

e)ception handler $ The state of the T bit is preserved in the &&R, and the LR of the e)ception

mode is set so that the normal return instruction performs correctly, regardless of whether the

e)ception occurred during ARM or Thumb e)ecution$

%n Thumb state, all the registers can not be accessed $ 5nly the low registers r( to r0 can be

accessed$ The higher registers r! to r12 are only accessible with M53, A, or CM

instructions$ CM and all the data processing instructions that operate on low registers update the

condition flags in the C&R

The list of registers and their accessibility in Thumb mode are shown in the following table$$

S.No Re$isters Access

1 r( > r0 ully accessible

2 r! > r12 5nly accessible by M53 ,A VCM" r1"& Limited accessibility

; r1; lr Limited accessibility

# r1# C Limited accessibility

- C&R 5nly indirect access

0 &&R 4o access

!)


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orm the above discussion, it is clear that there are no M&R and MR& e'uivalent Thumb

instructions$ To alter the C&R or &&R , one must switch into ARM state to use M&R and

MR&$ &imilarly, there are no coprocessor instructions in Thumb state$ Nou need to be in ARM

state to access the coprocessor for configuring cache and memory management$

ARM+Thumb interwor*ing is the method of lin*ing ARM and Thumb code together for both

assembly and C=C$ %t handles the transition between the two states$ To call a Thumb routine

from an ARM routine, the core has to change state$ This is done with the T bit of C&R $ The

9D and 9LD branch instructions cause a switch between ARM and Thumb state while branching

to a routine$ The 9D lrinstruction returns from a routine, also with a state switch if necessary$

The data processing instructions manipulate data within registers$ They include move

instructions, arithmetic instructions, shifts, logical instructions, comparison instructions, and

multiply instructions$ The Thumb data processing instructions are a subset of the ARM data

processing instructions$

E)s 6 AC 6 add two "2+bit values and carry Rd G Rd Rm C flag A 6 add two "2+bit values Rd G Rn immediate

Rd G Rd immediate

Rd G Rd Rm

A4 6 logical bitwise A4 of two "2+bit values Rd G Rd V Rm A&R 6 arithmetic shift right Rd G Rmimmediate,

C flagG Rmimmediate W 1U

Rd G RdRs, C flag G RdRs + 1U

9%C 6 logical bit clear .A4 45T/ of two "2+bit Rd G Rd A445T.Rm/values

CM4 6 compare negative two "2+bit values Rn Rm sets flags

CM 6 compare two "2+bit integers RnWimmediate sets flags RnWRm sets flags E5R 6 logical e)clusive 5R of two "2+bit values Rd G Rd E5R Rm

L&L 6 logical shift left Rd G Rm immediate, C flagG Rm"2 W immediateU

Rd G RdRs, C flag G Rd"2 W RsU

L&R 6 logical shift right Rd G Rm immediate, C flag G Rd immediate W 1U

Rd G Rd Rs, C flag G RdRs W 1U

M53 6 move a "2+bit value into a register Rd G immediate

!1


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Rd G Rn

Rd G Rm

M8L 6 multiply two "2+bit values Rd G .Rm X Rd/"16(U M34 6 move the logical 45T of a "2+bit value into a register Rd G 45T.Rm/

4E 6 negate a "2+bit value Rd G ( W Rm 5RR 6 logical bitwise 5R of two "2+bit values Rd G Rd 5R Rm

R5R 6 rotate right a "2+bit value Rd G Rd R%7TR5TATE Rs, C flagG RdRsW1U

&9C 6 subtract with carry a "2+bit value Rd G Rd W Rm W 45T.C flag/

&89 6 subtract two "2+bit values Rd G Rn W immediate Rd G Rd W immediate

Rd G Rn W Rm

sp G sp W .immediate2/

T&T 6 test bits of a "2+bit value Rn A4 Rm sets flags

4ote 6 Thumb deviates from the ARM style in that the barrel shift operations .A&R, L&L, L&R,

and R5R/ are separate instructions$

Than*ful to the following people for their invaluable information $

References : 1.ARM &ystem eveloperYs uide esigning and 5ptimi

Andrew 4$ &loss ,ominic &ymes and Chris Fright$ 2$ ARM+&ystem on+Chip Architecture >&teve urber$

"$ARM Architecture Reference Manual Copyright Z 1-+1!, 2(((, 2((;, 2((# ARM Limited$

!!

Unitii Armarchitecture 130305014346 Phpapp01

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Transcript of Unitii Armarchitecture 130305014346 Phpapp01