Unit iii ppt1

-> Logic Gates and other Complex gates, Switch logic,Alternate gate circuits,

-> Physical Design, Floor Planning ,Placement –Routing,Power Delay Estimation,Clock and Power Routing

Complementary CMOS logic gates◦ nMOS pull-down network◦ pMOS pull-up network◦ a.k.a. static CMOS

pMOSpull-upnetwork

outputinputs

nMOSpull-downnetwork

X (crowbar)0Pull-down ON

1Z (float)Pull-down OFF

Pull-up ONPull-up OFF

Logic Gates: AND,OR, NOT, NAND ,NOR ,XOR and XNOR

A 4-input CMOS NOR gate

A

B

C

DY

nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON Parallel: either can be ON

(a)

a

b

a

b

g1

g2

0

0

a

b

0

1

a

b

1

0

a

b

1

1

OFF OFF OFF ON

(b)

a

b

a

b

g1

g2

0

0

a

b

0

1

a

b

1

0

a

b

1

1

ON OFF OFF OFF

(c)

a

b

a

b

g1 g2 0 0

OFF ON ON ON

(d) ON ON ON OFF

a

b

0

a

b

1

a

b

11 0 1

a

b

0 0

a

b

0

a

b

1

a

b

11 0 1

a

b

g1 g2

Complementary CMOS gates always produce 0 or 1

Ex: NAND gate◦ Series nMOS: Y=0 when both inputs are 1◦ Thus Y=1 when either input is 0◦ Requires parallel pMOS

Rule of Conduction Complements◦ Pull-up network is complement of pull-down◦ Parallel -> series, series -> parallel

A

B

Y

Compound gates can do any inverting function Ex: AND-AND-OR-INV (AOI22) )()( DCBAY •+•=

A

B

C

D

A

B

C

D

A B C DA B

C D

B

D

YA

CA

C

A

B

C

D

B

D

Y

(a)

(c)

(e)

(b)

(d)

(f)

DCBAY •++= )(

A B

Y

C

D

DC

B

A

Transistors can be used as switchesg

s d

g

s d

Transistors can be used as switchesg

s d

g = 0s d

g = 1s d

0 strong 0

Input Output

1 degraded 1

g

s d

g = 0

s d

g = 1

s d

0 degraded 0

Input Output

strong 1

g = 1

g = 1

g = 0

g = 0

Figure 3 How voltages

correspond to logic levels.V

DD

logic 1

VH

unknown (X)

VL

VSS

logic 0

Strength of signal◦ How close it approximates ideal voltage source

VDD and GND rails are strongest 1 and 0 nMOS pass strong 0◦ But degraded or weak 1

pMOS pass strong 1◦ But degraded or weak 0

Thus NMOS are best for pull-down network Thus PMOS are best for pull-up network

Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well

g = 0, gb = 1

a b

g = 1, gb = 0

a b

0 strong 0

Input Output

1 strong 1

g

gb

a b

a b

g

gb

a b

g

gb

a b

g

gb

g = 1, gb = 0

g = 1, gb = 0

Other Forms of CMOS Logic (or) Alternate gate circuits:

Pseudo-nMOS logic:

Pseudo-nMOS Nand gate.

Pseudo-nMOS Inverter when driven from a similar Inverter.

DCVS Logic(Differential cascode voltage switch logic):

pulldown

network

-

complementary

complementarypulldown

inputsnetwork

-

inputs

out’out

Figure : shows the circuit for a particular DCVSL gate. This gatecomputes a+bc on one output and (a+bc)’ = a’b’+a’c’ on its otheroutput.

ab

c

a’

b' c'

a'b'+a'c' (a+bc)'

Dynamic CMOS logic:

Dynamic CMOS logic three-input Nand gate

Clocked CMOS logic:

Clocked CMOS (C2MOS) logic

CMOS domino logic:

Charge sharing in a domino circuit

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Physical Design

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Placement

Cost Estimation

Routing RegionDefinition

Global Routing

Compaction/clean-up

Detailed Routing

Cost Estimation

Write Layout Database

Floorplanning

Partitioning

Improvement

Cost EstimationImprovement

Improvement

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Physical Design:1. FloorPlanning : Architect’s job

2. Placement : Builder’s job

3. Routing : Electrician’s job

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Circuit Design

Partitioning

Floorplanning&

Placement

Routing

Fabrication

21: Package, Power, and Clock

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Through-hole vs. surface mount

Traditionally, chip is surrounded by pad frame◦ Metal pads on 100 – 200 µm pitch◦ Gold bond wires attach pads to package◦ Lead frame distributes signals in package◦ Metal heat spreader helps with cooling

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Decompose a large complex system into smaller subsystems

Decompose hierarchically until each subsystem is of manageable size

Design each subsystem separately to speed up the process

Minimize connection between two subsystems to reduce interdependency

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System Level Partitioning

Board Level Partitioning

Chip Level Partitioning

System

PCBs

Chips

Subcircuits/ Blocks

Several blocks after partitioning:

Need to:◦ Put the blocks together.◦ Design each block.

How to put the blocks together without knowing their shapes and the positions of the I/O pins?

If we design the blocks first, those blocks may not be able to form a tight packing.

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Top-down partitioning◦ Iterative improvement◦ Spectral based◦ Clustering methods◦ Network flow based◦ Analytical based◦ Multi-level

Bottom-up clustering◦ Unit delay model◦ General delay model◦ Sequential circuits with retiming

The floorplanning problem is to plan the positions and shapes of the modules at the beginning of the design cycle to optimize the circuit performance◦ chip area◦ total wirelength◦ delay of critical path◦ routability◦ others, e.g., noise, heat dissipation, etc.

Both determines block positions to optimize the circuit performance.

Floorplanning:◦ Details like shapes of blocks, I/O pin positions, etc. are not

yet fixed (blocks with flexible shape are called soft blocks). Placement:◦ Details like module shapes and I/O pin positions are fixed

(blocks with no flexibility in shape are called hard blocks).

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Output from partitioning used for floorplanning Inputs: ◦ Blocks with well-defined shapes and area◦ Blocks with approximated area and no particular shape◦ Netlist specifying block connections

Outputs:◦ Locations for all blocks

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Objectives◦ Minimize area◦ Reduce wirelength◦ Maximize routability◦ Determine shapes of

flexible blocks Constraints◦ Shape of each block◦ Area of each block◦ Pin locations for each

block◦ Aspect ratio

Dead space is the space that is wasted:

Minimizing area is the same as minimizing deads pace.

Dead space

Slicing Floorplan: One that can be obtained by repetitively subdividing (slicing) rectangles horizontally or vertically.

Non-Slicing Floorplan:One that may not be obtained by repetitively subdividing alone.

Otten (LSSS-82) pointed out that slicing floorplans are much easier to handle.

General case: all modules are soft macros Phase 1: bottom-up◦ Input – floorplan tree, modules shapes◦ Start with a sorted shapes list of modules◦ Perform vertical_node_sizing and horizontal_node_sizing◦ On reaching the root node, we have a list of shapes,

select the one that is best in terms of area Phase 2: top-down◦ Traverse the floorplan tree and set module locations

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Placement

Cost Estimation


Global Routing

Compaction/clean-up

Detailed Routing

Cost Estimation


Floorplanning

Partitioning

Improvement


Improvement

The process of arranging circuit components on a layout surface

Inputs : Set of fixed modules, netlist Output : Best position for each module based on

various cost functions Cost functions include wirelength, wire routability,

hotspots, performance, I/O pads

Good placement◦ No congestion◦ Shorter wires◦ Less metal levels◦ Smaller delay◦ Lower power dissipation

Bad placement Congestion Longer wire lengths More metal levels Longer delay Higher power dissipation

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Placement

Cost Estimation


Global Routing

Compaction/clean-up

Detailed Routing

Cost Estimation


Floorplanning

Partitioning

Improvement


Improvement

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Connect the various standard cells using wires Input:◦ Cell locations, netlist

Output:◦ Geometric layout of each net connecting various

standard cells Two-step process◦ Global routing◦ Detailed routing

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Two phases:

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Objective◦ 100% connectivity of a system◦ Minimize area◦ Minimize wirelength

Constraints◦ Number of routing layers◦ Design rules◦ Timing (delay)◦ Crosstalk◦ Process variations

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Looked at the physical design flow Involved several steps◦ Partitioning◦ Floorplanning◦ Placement◦ Routing

Each step can be formulated as an optimization problem

Need to go through 2 or more iterations in each step to generate an optimized solution

Unit iii ppt1

Engineering

Transcript of Unit iii ppt1