BHARATHIDASAN ENGINEERING COLLEGE

Degree / Branch : B.E./ECE Year / Sem : II/ III

Sub.Code / Name : EC6302/DIGITAL ELECTRONICS

FREQUENTLY ASKED QUESTIONS

UNIT –I

MINIMIZATION TECHNIQUES AND LOGIC GATES

Part – A

1. Apply De-Morgan’s theorem to simplify A+BC’. (MAY 2013)

2. Define the term prime implicants and Essential prime implicants. (MAY

2013)

3. Draw the XOR logic using only NAND gates. (NOV 2013)

4. Implement the following Boolean function with NOR – NOR logic

F = Π(0,2, 4,5,6) (NOV 2013)

5. Implement Y= AB+A+(B+C) using NAND gate only. (MAY 2014)

6. Define minterm & Maxterm. Give examples. (MAY 2014)

7. Simplify the given Boolean Expression F= x’+xy+xz’+xy’z’. (NOV 2014)

8. State Demorgan’s theorem. (NOV 2014)

9. Simplify the following Boolean function. (MAY 2015)

i) x(x’+y)

ii) xy+x’z+yz

10. Show that A+A’B=A+B using the theorems of Boolean algebra. (MAY

2015)

11. Realize F = A’B+AB’ using minimum universal gates. (NOV 2015)

12. Convert Y= A+BC'+AB+A'BC into canonical form. (NOV 2015)

13. Write down fan-in & fan-out of a standard TTL IC. (MAY 2016)

14. Prove that AB+A’C+BC = AB + A’C (MAY 2016)

15. Implement the following Boolean function with NAND – NAND logic

F = ∑(0,1, 3, 5)

16. What are don’t care terms?

17. Define noise margin.

18. Convert the following function into sum of product form (AB+C)(B+C’D).

19. Define the term (i). Propagation delay (ii). Power dissipation

20. Define canonical form. Express F=BC’+AC in a canonical SOP form.

21. Simplify the following expression X.Y+X(Y+Z)+Y(Y+Z). NOV 2016

22. Why totem pole outputs cannot be connected together. NOV 2016

23. Name the universal gates? Why are they called so. MAY 2017

24. Simplify F=xy+xy’. MAY 2017

PART-B

1. i). Simplify the following function using K – map, (MAY 2014)

f=ABCD+AB’C’D’+AB’C+AB & realize the SOP using only NAND

gates and POS using only NOR gates (10)

ii) Show that if all the gate in a two-level OR-AND gate network are

replaced by NOR gate, the output function does not change. (6)

2. i). Using Quine Mc-Cluskey method, examine the given function.

F(A,B,C,D)=∑m(1,2,3,7,8,9,1011,14,15) . (10)

ii). Explain the operation of 3 input TTL NAND gate with required diagram &

truth table. (6) (MAY 2014)

3. (i) Use QM method to simply the Boolean expression (NOV 2015)

(x1,x2,x3,x4,x5)=Σ(0,1,4,5,16,17,21,25,29) (10)

ii). Draw the circuits of 2 input NAND & 2 input NOR gate using CMOS. (6)

4. i). Using Quine McCluskey method Simplify the Boolean expression (NOV

2015) F(v,w,x,y,z) = Σ (4,5,9,11,12,14,15,27,30) +Σd(1,17,25,26,31) (10)

ii). Explain the working of a basic totem-pole TTL 2 input NAND gate. (6)

5. i).Find a minimal SOP representation for (MAY 2015)

f(A,B,C,D,E) = Σm(1,4,6,10,20,22,24,26) + d(0,11,16,27) using K-map

method. Draw the circuit of the minimal expression using only NAND. (12)

ii). Obtain 3 level NOR – NOR implementation of f = [ab + cd] ef (4)

6. (i) Explain Tri-state TTL inverter circuit diagram and its operation.

(ii) How would you express the Boolean function using K-map and draw the

logic diagram. F(w,x,y,z)=∑m(0,1,2,4,5,6,8,9,12,13,14) (MAY 2015)

7. Find a minimal SOP representation for (NOV 2015)

f(A,B,C,D,E)=Σm(1,4,6,10,20,22,24,26)+ d(0,11,16,27) using K-map

method. Draw the circuit of the minimal expression using only NAND.

(ii) Express the Boolean function F=XY+X’Z in product of maxterm. (4)

8. (i) Design the given function using Quine Mc-Cluskey method and Verify

your result using Kmap. F=∑m(0,1,2,4,5,6,8,9,12,13,14)

(ii) Draw the schematic and explain the operation of a CMOS inverter. Also

explain its characteristics. (NOV 2015)

9. Simplify the 5 variable switching function using Karnaugh map (MAY

2016)

F(A,B,C,D,E)=Σm(3,5,6,8,9,12,13,14,19,22,24,25,30). (10)

(ii) Implement the expression Y (A, B, C) = ΠM (0, 2, 4, 5, 6,) using only

NOR-NOR logic. (6)

10. (i) Analyze the basic rules (laws) that are used in Boolean expressions with

example. (MAY 2016)

(ii) Simplify using K-map to obtain minimum POS expression(A’+B’+C+D)

(A+B’+C+D) (A+B+C+D’) (A+B+C’+D’) (A’+B+C+D’) (A+B+C’+D). (8)

11.(i) Find the MSOP representation for F(A,B,C,D,E) =

m(1,4,6,10,20,22,24,26)+d(0,11,16,27) using K-map method. Draw the circuit

of the minimal expression using only NAND gates. (7) (NOV 16)

(ii) With neat circuit diagram, explain the function of 3-input TTL NAND

gate. (6)

12. What are advantages of using tabulation method? Determine the Minimal

sum of products for the Boolean expressions F= Σm(1,2,3,7,8,9,10,11,14,15)

using tabulation method. (13) (NOV 16)

13. (i) Express F=A+B’C in a sum of minterms. (6) (MAY 2017)

(ii) Using Quine McCluskey method minimize the function F=

Σm(0,5,7,8,9,10,11,14,15). (10) (MAY 2017)

14. Simplify the logic function F= Σm(10,11,14,15) and implement using

NAND gates. (10) (MAY 2017)

UNIT – 2 COMBINATIONAL CIRCUITS

2 marks

1. Define half adder and full adder. (MAY 2013)

2. Define half subtractor and full subtractor. (MAY 2013)

3. What is a combinational circuit? Give an example. (NOV 2013)

4. Write an expression for borrow and difference in a full subtractor circuit. (NOV 2013)

5. List the advantage of look ahead carry? When should it be used? (MAY 2014)

6. Distinguish between Decoder and Demultiplexer. (MAY 2014)

7. Write down the truth table of a half subtractor. (NOV 2014)

8. Convert gray code 101011 into its binary equivalent. (NOV 2014)

9. Define magnitude comparator. (MAY 2015)

10. Compare the serial and parallel adder. (MAY 2015)

11. Define look ahead carry addition. (NOV 2015)

12. Relate carry generate, carry propagate, sum and carry-out of a Carry look ahead adder. (NOV

2015)

13. Build a 4:1 mux using only 2:1 mux. (MAY 2016)

14. Draw the circuit of 2 bit even and odd parity checker and generator. (MAY 2016)

15. What is a decoder?

16. What do you mean by encoder?

17. What is a priority encoder?

18 . What is a multiplexer?

19. Give applications of multiplexer?

20. Design a Half subtractor using gates.

21. Draw a full adder using two half adders and an OR gate.

22. Draw the logic diagram of 4-bit parallel adder/subtractor.

23. Design a full subtractor using gates.

24. Write about the design procedure for combinational circuits. (NOV 2016)

25. Draw the logic diagram and truth table of Full adder. (NOV 2016)

26. Write the truth table for half subtractor. MAY 2017

27. Convert a decoder into a demultiplexer. MAY 2017

16 MARK QUESTIONS

1. (i) Design a Binary to Gray code converter. (MAY 2014)

(ii) Design a half adder and full adder circuits .

2. (i) Explain the concept of carry look ahead adder with neat logic diagram.

(ii) Implement full subtractor using Demultiplexer. (MAY 2014)

3. (i) Design a 4-bit Magnitude Comparator with 3 outputs; A>B,A=B,A<B.

(ii) Explain even parity checker and generator. (NOV 2015)

4. (i) Design a BCD to Gray code converter. Use don’t cares.

(ii) Design a half subractor and design a subractor. (NOV 2015)

5. Design a 4-bit binary to BCD code converter. (MAY 2015)

6. Design a combinational circuit to convert Excess-3 code to BCD code. (MAY 2015)

7. i) Design an 8X1 MUX using only 4 X1 MUX. (8) (NOV 2015)

ii) Realize F(w,x,y,z)=S(1,4,6,7,8,9,10,15) using 4 to 1 Mux (8)

8. Design a BCD adder to add two BCD digits. (NOV 2015)

10. Design a combinational logic circuit to compare two 2- bit binary numbers A and B and to

Generate the outputs A<B,A=B and A>B (MAY 2016)

11. (i) Design and implement the conversion circuit for BCD to Excess 3 code (10) (MAY

2016)

(ii) Draw & explain the block diagram of a 4-bit parallel adder / Subtractor (6)

12. (i) Design a BCD adder and explain its working with necessary circuit diagram.

(ii) Draw & explain the block diagram of a 4-bit serial adder to add contents of two registers.

13. (i) Design and explain 1 of 8 demultiplexer. (8) (NOV 16) (ii) What is parity checker? (5)

14. Describe the operation of 3-bit magnitude comparator. (13) (NOV 16)

15. (i) Explain the carry look ahead adder with a diagram. (10) (MAY 2017)

(ii) Implement the function y=AB and y=A+B using 2:1 MUX. (6)

16. Implement BCD to 7 segment code converter. (16) (MAY 2017)

UNIT –III SEQUENTIAL CIRCUITS

Part – A

1. Compare Asynchronous and Synchronous sequential logic. (MAY 2013)

2. Draw the state diagram and characteristics equation of a D FF. (MAY 2013)

3. What is latch? What is the difference between latch and flip flop? (NOV 2013)

4. Realize T Flip Flop using SR Flip Flop. (NOV 2013)

5. How does the JK FF differ from an SR FF in its basic equation? (MAY 2014)

6. Define Synchronous counter. (MAY 2014)

8. What is the condition on JK FF to work as D FF? (NOV 2014)

9. What is race around condition? How do you eliminate it? (NOV 2014)

10. Mention any two differences between the edge triggering and level triggering. (MAY 2015)

11. Draw the state diagram of MOD -10 counters. (MAY 2015)

12. What is sequential circuit? Give some example. (NOV 2015)

13. Draw a NAND based logic diagram of Master Slave JK FF. (NOV 2015)

14. Convert Transparent flip flop into a JK flip flop. (MAY 2016)

16. Define the terms State table and State Assignment. (MAY 2016)

18. Draw the state table and excitation table of T flip flop.

19. How many Flip Flops are required to build a binary counter that counts from 0 to 1023.

20. Name the different types of shift registers.

21. What is a sequential circuit?

22. Distinguish between latch and flip-flop.

23. Write the flip-flop excitation tables for JK and T FF.

24. What is counter?

25. What is a shift register?

26.Derive the characteristic equation of T flip flop

27.What is the minimum of Flip flops required to build a counter of modulus 8

28.Draw the logic diagram for T flip flop.

29. What is modulo n counter?

30. How many states are there in a 3 bit ring counter? What are they?

31. Define race around condition in flip flop. NOV 2016

32. Draw D-latch with truth table. NOV 2016

33. Give some basic applications of flip flops. MAY 2017

34. What is meant by modulus of a counter? MAY 2017

16 MARK QUESTIONS

1. i) Draw a 4 bit serial in parallel out (SIPO) and explain its operation. (8) (MAY 2014)

ii) Explain the operation universal shift register with neat block diagram (8) (MAY 2014)

2. With a neat state diagram and logic diagram ,design and explain the sequence of states of BCD

counter (16) (MAY 2014)

3. (i) Draw the circuit and explain the working operation of JK Master Slave flip-flop.

(ii) Provide the characteristic table, characteristic equation and excitation table of D flip flop

And JK flip flop. (NOV 2015)

4. Using JK flip-flops, design a synchronous counter which counts in the sequence 000, 111, 101,

110,

001, 010, 000…… (NOV 2015)

5. Design a binary counter using T flip-flops to count pulses in the following sequence

(i) 000, 001, 010, 011, 100, 101, 110, 111, 000 (8)

(ii) 000, 100, 111, 010, 011, 000 (8) (MAY 2015)

6. (i) Design and explain the working of a MOD-11 counter. (MAY 2015)

(ii) Design and explain the working of a up-down ripple counter

7. (i) Design a Mod 5 Asynchronous counter draw the wave forms. (8marks) (NOV 2015)

(ii) How can a D flip flop converted into a T flip flop. (8marks)

8. Using JK flip-flops, design a synchronous counter which counts in the sequence 2,6,1,7,5,4 and

repeat. (NOV 2015)

9. (i) Using RS flip-flops, design a Parallel counter which counts in the sequence 000, 111, 101, 110,

001, 010, 000…… (MAY 2016)

ii) Draw the four bit Johnson counter and explain the operation (8) (MAY 2016)

10. (i) Draw a 4-bit SISO SIPO, PIPO and PISO shift register and draw its waveforms.

(ii) Design a counter to count the sequence 0, 1, 2, 4, 5, 6,...using SR FF’s.

11. (i) Explain the operation of JK flip-flop with neat diagram. (6) (NOV 16) (ii) Explain the operation of Serial-in-Serial-out shift register. (7)

12. Design synchronous MOD-6 counter. (13) (NOV 16) 13. (i) Write the characteristic table, equation and excitation table of a JK flip flop and T flip flop. (6)

(ii) Design a mod-6 synchronous counter using TFFs. (10) (MAY 2017)

14. (i) What is a serial adder? Explain. (8) (MAY 2017)

(ii) With Truth table and timing diagram explain the operation of 4 bit ring counter. (8)

UNIT –IV MEMORY DEVICES

Part – A

1. How the memories are classified. (MAY 2013)

2. What is an EPROM? (MAY 2013)

3. Compare and contrast static RAM and dynamic RAM. (NOV 2013)

4. What is PLD? List their types. (NOV 2013)

5. Distinguish between PAL and PLA. (MAY 2014)

6. Which memory is called volatile? Why? (MAY 2014)

7. Write the advantages of EPROM over a PROM. (NOV 2014)

8. Compare the features of PROM, PAL and PLA. (NOV 2014)

10. What is PLA? How does it differ from PAL and PROM? (MAY 2015)

11. What is memory decoding? (MAY 2015)

12. Implement the Exclusive-OR function using PROM. (NOV 2015)

13. Write the advantages of E2PROM over an EPROM. (NOV 2015)

14. Implement the function F1=∑ (0, 1, 2, 5, 7) and F2 = ∑ (1, 2, 4, 6) using PROM. (MAY

2016)

15. Draw the static and dynamic RAM cells. (MAY 2016)

16. Implement a 2-bit multiplier using ROM.

17. What is meant by memory expansion? Mention its limit.

18. Compare PLD’s with FPGA.

19. Draw the equivalent logic circuit of a binary memory cell that stores one bit of information.

20. What is volatile and Non-volatile memory?

21. Briefly explain about EEPROM. NOV 2016

22. What is programmable logic array? How it differs from ROM? NOV 2016

23. What is the disadvantages of dynamic RAM cell? MAY 2017

24. How PAL differs from ROM? MAY 2017

Part – B

1. i). Give the classification of semiconductor memories (8)

ii). Implement the following function using PLA F1=∑ (2, 4, 5, 10, 12, 13, 14) and F2 = ∑ (2, 9, 10,

11,13, 14, 15). (MAY 2014)

2. i). Realized BCD to Excess-3 code using PROM array.

ii). A combinational circuit is defined as the functionF1 = AB’C’+AB’C+ABC and F2 =

A’BC+AB’C+ABC. Implement the digital circuit with a PLA having 3 inputs, 3 product terms

and 2 outputs. (8) (MAY 2014)

3. i). Write short note on RAM, types of ROMs (10) (NOV 2015)

ii). Implement the following function using PLA F1=∑ (0, 1, 2, 4) and F2 = ∑ (0, 5, 6, 7). (6)

4. i). Realize the following function using PAL F1(x, y, z) = ∑ (1, 2, 4, 5, 7),

F2(x, y, z) = ∑m(0, 1, 3, 5, 7) (8)

ii). Write a note on FPGA with neat diagram. (8) (NOV 2015)

5. i).Write short notes on PLD, types of PLDs. (8)

ii). Implement the following Boolean function using 3×4×2 PLA, F1(x, y, z) = ∑ (0, 1,3, 5) and

F2(x, y, z) = ∑ (3, 5, 7) (8) (MAY 2015)

6. (i) Design using PAL the following Boolean functions W(A,B,C,D) = ∑(2, 12, 13) X(A,B,C,D) =

∑(7, 8, 9, 10, 11, 12, 13, 14, 15) Y(A,B,C,D) = ∑(0, 2,3, 4, 5, 6, 7, 8, 10, 11, 15) Z(A,B,C,D) = ∑(1,

2, 8, 12, 13)

ii). Describe the RAM organization. (8) (MAY 2015)

7. i). Explain the principle of operation of Bipolar SRAM cell. (8) (NOV 2015)

ii). Write short notes on EPROM and EEPROM. (8)

8. Implement the following Boolean functions using 4 × 3 × 4 PAL (16) (NOV 2015)

i. W(A, B, C, D) = ∑ (0, 2, 6, 7, 8, 9, 12, 13)

ii. X (A, B, C, D) = ∑ (0, 2, 6, 7, 8, 9, 12, 13, 14).

iii. Y(A, B, C, D) = ∑ ( 2, 3, 8, 9, 10, 12, 13)

iv. Z(A, B, C, D) = ∑ (1, 3, 4, 6, 9, 12, 14)

9. (i)A combinational circuit is defined by the functions (8) (MAY 2016)

F1(A,B,C)=Σ(3,5,6,7)

F2(A,B,C)=Σ(0,2,4,7) implement the circuit with a PLA.

(ii) A combinational circuit is defined by the functions F1 = ∑m(1,3,5),F2 = ∑m(5,6,7). Implement

the circuit with a PLA having 3 inputs, 3 product terms and two outputs. (8)

10. Differentiate static and dynamic RAM. Draw the circuits of one cell of each and explain

its working principle. (13) (NOV 16)

11. Write short notes on: (13) (NOV 16) (i) PAL

(ii) FPGA.

12. (i) Describe the RAM organization and explain the write and read operations. (10)

(ii) Discuss on various types of ROM. (6) (MAY 2017)

13. (i)Implement the functions A(x,y,z)= ∑m(1,2,4,6) and B=(x,y,z)= ∑m(0,1,6,7) using (1) ROM (2)

PLA (8)

(ii) Outline the features of various programmable logic devices. (8) (MAY 2017)

UNIT – V SYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS

1. Define asynchronous sequential circuit. (MAY 2013)

2. State the difference between the synchronous and asynchronous sequential circuits. (MAY

2013)

3. What is a fundamental mode asynchronous sequential circuits. (NOV 2013)

4. What is a critical race? Why should it be avoided? (NOV 2013)

5. Define cycle. (MAY 2014)

6. Define Hazard. (MAY 2014)

7. Define race, critical race and non-critical race. (NOV 2014)

8. Define a primitive flow table. (NOV 2014)

9. What is Static 1 Hazard? (MAY 2015)

10. Define static Hazard. (MAY 2015)

11. Define Glitch. (NOV 2015)

12. What is a dynamic hazard? (NOV 2015)

13. What is essential hazard? (MAY 2016)

14. What are Mealy and Moore machines? (MAY 2016)

15. What is a race?

16. What is a cycle?

17. What is shared row state assignment?

18. Mention any advantage and disadvantage of asynchronous sequential circuits.

19. Define static 0-hazard,static 1-hazard and dynamic hazard.

20. What is the difference between Mealy machine and Moore machine

21.Explain the procedure for state minimization.

22. What is pulse mode circuit?

23. What are the types of Hazards?

24.What are the assumptions made for pulse mode circuit?

25. What are the assumptions made for fundamental mode circuit?

26. Define Critical race and Non Critical race. NOV 2016

27. What is hazard and give it types? NOV 2016

28. Compare mealy and moore machine. MAY 2017

29. List the effects due to hazards in logic circuits. MAY 2017

16 MARK QUESTIONS

1. i)Give examples for critical race and cycle and explain. (MAY 2014)

ii) Describe the hazards with neat circuit diagram.

2. Give the hazard free realization for the following functions. (MAY 2014)

f(a, b, c, d) = ∑ m (0, 2, 6, 7, 8, 10, 12)

3 .Design an asynchronous sequential circuit that has two inputs X2 and X1 and one output z. When

x1 = 0, the output Z is 0. The first change in X2 that occurs while X1 is 1 will cause output Z to be 1.

The output Z will remain 1 until X1 returns to zero . (NOV 2015)

4. An asynchronous sequential circuit has two internal states and one output. The excitation and

output function describing the circuit are as follows.

Y1 = x1x2 + x1y2 + x2y1

Y2 = x2 + x1y1y2 + x1y1

Z = x2 + y1 (NOV 2015)

5. i) Give hazard-free realization for the following Boolean function

F(A,B,C,D)=Σm(1,3,6,7,13,15) (MAY 2015)

ii) Summarize the design procedure for asynchronous sequential circuit.

6. An asynchronous sequential circuit is described by the following excitation and output function.

Y=X1X2+(X1+X2)Y i) Draw the logic diagram. ii) Derive the transition table and output

map.

iii) Describe the behavior of the circuit. (MAY 2015)

7. An asynchronous circuit described by the following excitation and output function

Y=X1.X2+(X1+X2).Y Z=Y Draw the logic diagram of the circuit. Derive the transition

table and output map. Describe the behavior of the circuit. (NOV 2015)

8. What are the problems in asynchronous circuits and what are essential hazards and static hazards

how it can be eliminated. (NOV 2015)

9.(i) .Give the hazard free realization for the following functions. (MAY 2016)

f(a, b, c, d) = ∑ m (1,3,6,7,13,15) (8marks)

(ii) Summarize the design procedure for asynchronous sequential circuit. ( 8marks )

10.Explain essential , static and dynamic Hazards in Digital circuit. Give the hazard free realization

for the following functions. F(I,J,K,L) = ∑m (1,3,4,5,6,7,9,11,15) (MAY 2016)

11. i) Differentiate critical races from non-critical races. (6) NOV’2010

ii) Explain the steps involved in the reduction of state table. (10)

12. Explain the steps involved in the design of asynchronous sequential circuit. (13) (NOV

16) 13. Design an asynchronous circuit that will output only the second pulse received and ignore

any other pulse. (13) (NOV 16)

14. (i) Draw the general model of a sequential circuit and explain. (6) (MAY 2017)

(ii) List out the steps involved in the design of synchronous sequential circuit. (10)