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Contents
1. 8085 pin description2. 8085 system bus3. Internal architecture of 8085 microprocessor
4. 8085 functional description.5. Interrupts of 8085 microprocessor6. Instruction set classification.7. Instruction format.
8. Addressing modes.9. Instructions of 80859. Sample programs.
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8085 microprocessor..
It is a program controlled semiconductordevice (IC}, which fetches, decode and
executes instructions.
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Introduction of 8085
It is a 8 bit processor
It is a single chip N-Mos Device with 40 Pins
It has multiplexed address and Data lines(AD0
to AD)
It works on 5 Volt power supply
The Max clock frequency is 3 MHz and the Min
is 500KHz It Provides 74 instruction with 5 different
addressing Modes
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Introduction Of 8085
It provides 16 address lines so it can access 2 ^ 16 =64Kbytes of memory.
It generates 8 bit I/O address so it can access 2 ^8=256input ports.
It provides 5 hardware interrupts: TRAP, RST 5.5, RST6.5, RST 7.5,INTR.
It provides Acc ,one flag register ,6 general purposeregisters and two special purpose registers(SP,PC).
It provides serial lines SID ,SOD.So serial peripherals canbe interfaced with 8085 directly.
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PIN DIAGRAM
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8085
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The 8085 MicroprocessorArchitecture
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Intel 8085 CPU (Architecture)Block Diagram
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16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
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Flag Register of 8085
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Control UnitGenerates signals within uP to carry out the instruction, which has beendecoded. Inreality causes certain connections between blocks of the uP to be opened orclosed, sothat data goes where it is required, and so that ALU operations occur.Arithmetic Logic UnitThe ALU performs the actual numerical and logic operation such as add,
subtract, AND, OR, etc. Uses data from memory and from Accumulator to
perform arithmetic. Always stores result of operation in Accumulator.RegistersThe 8085/8080A-programming model includes six registers, one accumulator,and one flag register, as shown in Figure. In addition, it has two 16-bit registers:the stack pointer and the program counter. They are described briefly as follows.The 8085/8080A has six general-purpose registers to store 8-bit data; these
are identified as B,C,D,E,H, and L as shown in the figure. They can becombined as register pairs - BC, DE, and HL - to perform some 16-bitoperations. The programmer can use these registers to store or copy data intothe registers by using data copy instructions.
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AccumulatorThe accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU).This register is used to store 8-bit data and to perform arithmetic and logicaloperations. The result of an operation is stored in the accumulator. The
accumulator is also identified as register A.FlagsThe ALU includes five flip-flops, which are set or reset after an operationaccording to data conditions of the result in the accumulator and other registers.They are called Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry(AC) flags; they are listed in the Table and their bit positions in the flag register
are shown in the Figure below. The most commonly used flags are Zero, Carry,and Sign. The microprocessor uses these flags to test data conditions.
For example, after an addition of two numbers, if the sum in theaccumulator id larger than eight bits, the flip-flop uses to indicate a carry -- calledthe Carry flag (CY) is set to one. When an arithmetic operation results in zero,
the flip-flop called the Zero(Z) flag is set to one. The first Figure shows an 8-bitregister, called the flag register, adjacent to the accumulator. However, it is notused as a register; five bit positions out of eight are used to store the outputs ofthe five flip-flops. The flags are stored in the 8-bit register so that theprogrammer can examine these flags (data conditions) by accessing the registerthrough an instruction.
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Signal Flow in 8085
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Now, Let us see how the different unitsand bus systems stay connected:
A15-A8
LatchAD7-AD0
D7- D0
A7- A0
8085
ALE
IO/MRDWR
1K ByteMemory
Chip
WRRD
CS
A9- A0
A15- A10Chip Selection
Circuit
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Types of Interrupts:
8085 supports two types of interrupts.
Hardware interrupts
Softwareinterrupts
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Software interrupts: The software interrupts are program
instructions. These instructions are insertedat desired locations in a program.
The 8085 has eight software interrupts fromRST 0 to RST 7. The vector address for theseinterrupts can be calculated as follows.
Interrupt number * 8 = vector address For RST 5,5 * 8 = 40 = 28H
Vector address for interrupt RST 5 is 0028H
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The Table shows the vector addresses of allinterrupts.
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Hardware interrupts:
External device initiates the hardwareinterrupts and placing an appropriatesignal at the interrupt pin of theprocessor.
If the interrupt is accepted then the
processor executes an interrupt serviceroutine.
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Hardware interrupts Cont..
The 8085 has five hardware interrupts
(1) TRAP
(2) RST 7.5(3) RST 6.5
(4) RST 5.5
(5) INTR
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8085 Interrupts
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How SIM Interprets the Accumulator
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SDO
SDE
XXX
R7.5
MSE
M7.5M6.5
M5.5
01234567
RST5.5 Mask
RST6.5 Mask
RST7.5Mask }
0 - Available
1 - Masked
Mask Set Enable0 - Ignore bits 0-21 - Set the masks according
to bits 0-2
Force RST7.5 Flip Flop to resetNot Used
Enable Serial Data0 - Ignore bit 71 - Send bit 7 to SOD pin
erial Data Out
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RIM sets the Accumulators different bits
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TRAP:
This interrupt is a non-maskable interrupt. It is unaffected by any maskor interrupt enable.
TRAP bas the highest priority and vectored interrupt.
TRAP interrupt is edge and level triggered. This means hat the TRAPmust go high and remain high until it is acknowledged.
In sudden power failure, it executes a ISR and send the data from main
memory to backup memory.
The signal, which overrides the TRAP, is HOLD signal. (i.e., If theprocessor receives HOLD and TRAP at the same time then HOLD isrecognized first and then TRAP is recognized).
There are two ways to clear TRAP interrupt.
1.By resetting microprocessor (External signal) 2.By giving a high TRAP ACKNOWLEDGE (Internal signal)
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RST 7.5:
The RST 7.5 interrupt is a maskable interrupt.
It has the second highest priority.
It is edge sensitive. ie. Input goes to high and no need tomaintain high state until it recognized.
Maskable interrupt. It is disabled by,
1.DI instruction2.System or processor reset.3.After reorganization of interrupt.
Enabled by EI instruction.
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RST 6.5 and 5.5:
The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes
to high and stay high until it recognized.
Maskable interrupt. It is disabled by,
1.DI, SIM instruction2.System or processor reset.3.After reorganization of interrupt.
Enabled by EI instruction.
The RST 6.5 has the third priority whereas RST 5.5 has the fourthpriority.
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INTR:
INTR is a maskable interrupt. It is disabled by,
1.DI, SIM instruction2.System or processor reset.3.After reorganization of interrupt.
Enabled by EI instruction.
Non- vectored interrupt. After receiving INTA (active low) signal, it hasto supply the address of ISR.
It has lowest priority.
It is a level sensitive interrupts. ie. Input goes to high and it isnecessary to maintain high state until it recognized.
The following sequence of events occurs when INTR signal goes high.
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Interrupt table
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1.3 INSTRUCTION SET
BASED ON FUNCTIONS
Data Transfer Instructions
Arithmetic Instructions
Logical Instructions
Branch Instructions
Machine Control
BASED ON LENGTH
One-word or 1-byte instructions
Two-word or 2-byte instructions
Three-word or 3-byte instructions
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8085 Instruction Set
The 8085 instructions can be classified as follows:
Data transfer operations Between Registers
Between Memory location and a Registers
Direct write to a Register/Memory
Between I/O device and Accumulator
Arithmetic operations (ADD, SUB, INR, DCR)
Logic operations (AND, OR, NOT)
Branching operations (JMP, CALL, RET)
Stack, Machine, I/O Control Operations
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8085 Instruction Types
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8085 Instruction Types
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8085 Instruction Types
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Direct Addressing:Jump instructions include a 16-bit address as part of
the instruction. For example,
JMP 1000H
the instruction JMP 1000H causes a jump to the hexadecimaladdress 1000 by replacing the current contents of the programcounter with the new value 1000H.
Instructions that include a direct address require
three bytes of storage: one for the instruction code, and two for the16-bit address
ADDRESSING MODES
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Indirect Addressing:Register indirect instructions reference memory via a
register pair. Thus,
MOV M,C
the instruction MOV M,C moves the contents of the C register intothe memory address stored in the H and L register pair. Theinstruction LDAX B loads the accumulator with the byte of dataspecified by the address in the B and C register pair.
ADDRESSING MODES
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Register Addressing:Quite a large set of instructions call for register
addressing. With these instructions, specify one of theregisters A through E, H or L as well as the operation code. With
these instructions, the accumulator is implied as a secondoperand. For example, the instruction
CMP Emay be interpreted as 'compare the contents of the E register with thecontents of the accumulator.
Most of the instructions that use register addressingdeal with 8-bit values. However, a few of these instructions deal
with 16-bit register pairs. For example, the PCHL instructionexchanges the contents of the program counter with the contents
of the H and L registers.
ADDRESSING MODES
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Immediate Addressing:Instructions that use immediate addressing have
data assembled as a part of the instruction itself. For example, theinstruction
CPI C, 08
may be interpreted as compare the contents of the accumulatorwith the letter C. When assembled, this instruction has thehexadecimal value FE43. Hexadecimal 43 is the internal
representation for the letter C. When this instruction is
executed, the processor fetches the first instruction byte anddetermines that it must fetch one more byte. The processor fetchesthe next byte into one of its internal registers and then
performs the compare operation.
ADDRESSING MODES
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Implied Addressing:
The addressing mode of certain instructions isimplied by the instructions function. For example, the
STC(set carry flag)
instruction deals only with the carry flag, the DAA (decimal adjustaccumulator) instruction deals with the accumulator.
ADDRESSING MODES
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Instruction Set of 8085An instruction is a binary pattern designed inside a
microprocessor to perform a specific function.
The entire group of instructions that a microprocessorsupports is called Instruction Set.
8085 has 246 instructions.
Each instruction is represented by an 8-bit binary value.
These 8-bits of binary value is called Op-Codeor
Instruction Byte.
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Classification of Instruction Set
Data Transfer Instruction
Arithmetic Instructions
Logical Instructions
Branching Instructions
Control Instructions
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Data Transfer Instructions
These instructions move data between registers, orbetween memory and registers.
These instructions copy data from source to destination.
While copying, the contents of source are not modified.
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Opcode Operand Description
1 MOV Rd, Rs Copy from source to destination.
M, Rs
Rd, M
This instruction copies the contents of the source register into thedestination register.
The contents of the source register are not altered.
If one of the operands is a memory location, its location is specified
by the contents of the HL registers.
Example: MOV B, C or MOV B, M
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Opcode Operand Description
2 MVI Rd, Data Move immediate 8-bit
M, Data
The 8-bit data is stored in the destination register or
memory.
If the operand is a memory location, its location is
specified by the contents of the H-L registers.
Example: MVI B, 57H or MVI M, 57H
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Opcode Operand Description
3 LDA 16- bit address Load Accumulator
The contents of a memory location, specified by a 16-bit address in the operand, are copied to theaccumulator.
The contents of the source are not altered. Example: LDA 2034H
Opcode Operand Description4 LXI Reg. pair, Load register pair immediate
16-bit data
This instruction loads 16-bit data in the register pair. Example: LXI H, 2034 H
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Opcode Operand Description
5. LDAX B/D Register Pair Load Accumulator
Indirect
The contents of the designated register pair point to amemory location.
This instruction copies the contents of that memorylocation into the accumulator.
The contents of either the register pair or the memory
location are not altered.
Example: LDAX B
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Opcode Operand Description
6 LHLD 16- bit address Load H-L register
Direct
This instruction copies the contents of memory
location pointed out by 16-bit address into register L.
It copies the contents of next memory location into
register H.
Example: LHLD 2040 H
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Opcode Operand Description
7 STA 16- bit address Store accumulator
Direct
The contents of accumulator are copied into the memory locationspecified by the operand.
Example: STA 2500 H
Opcode Operand Description
8 STAX Reg. Pair Store accumulator
Indirect
The contents of accumulator are copied into the
memory location specified by the contents of the
register pair.
Example: STAX B
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Opcode Operand Description
9 SHLD 16- bit address STORE H-L register
Direct
The contents of register L are stored into memory location specifiedby the 16-bit address.
The contents of register H are stored into the next memory location.
Example: SHLD 2550
Opcode Operand Description
10 XCHG NONE EXCHANGE H-L with D-E
The contents of register H are exchanged with the contents ofregister D.
The contents of register L are exchanged with the contents ofregister E.
Example: XCHG
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Arithmetic Instructions
These instructions perform the operations like:
Addition
Subtract
Increment
Decrement
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Addition
Any 8-bit number, or the contents of register, orthe contents of memory location can be added tothe contents of accumulator.
The result (sum) is stored in the accumulator.
No two other 8-bit registers can be addeddirectly.
Example: The contents of register B cannot beadded directly to the contents of register C.
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Subtraction Any 8-bit number, or the contents of register, or the
contents of memory location can be subtracted from
the contents of accumulator.
The result is stored in the accumulator.
Subtraction is performed in 2s complement form.
If the result is negative, it is stored in 2s complement
form.
No two other 8-bit registers can be subtracted directly.
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Increment / Decrement
The 8-bit contents of a register or amemory location can be incremented ordecremented by 1.
The 16-bit contents of a register pair canbe incremented or decremented by 1.
Increment or decrement can be performedon any register or a memory location
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Opcode Operand Description
1 ADD R Add register or memory to accumulator
M
The contents of register or memory are added to the contents ofaccumulator.
The result is stored in accumulator.If the operand is memory location, its address is specified by H-L pair.All flags are modified to reflect the result of the addition.
Example: ADD B or ADD M
Opcode Operand Description2 ADC R Add register or memory to accumulator with carry
M
The contents of register or memory and Carry Flag (CY) are added tothe contents of accumulator.
The result is stored in accumulator.If the operand is memory location, its address is specified by H-L pair.All flags are modified to reflect the result of the addition.Example: ADC B or ADC M
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Opcode Operand Description
3 ADI 8-bit data Add immediate to accumulator
The 8-bit data is added to the contents of accumulator.
The result is stored in accumulator. All flags are modified to reflect the result of the
addition.
Example: ADI 45 H
Opcode Operand Description
4 ACI 8-bit data Add immediate to accumulator with carry
The 8-bit data and the Carry Flag (CY) are added to the
contents of accumulator.
The result is stored in accumulator.
All flags are modified to reflect the result of the addition.
Example: ACI 45 H
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Opcode Operand Description
5 DAD Reg. pair Add register pair to H-L pair.
The 16-bit contents of the register pair are added to the
contents of H-L pair. The result is stored in H-L pair.
If the result is larger than 16 bits, then CY is set.
No other flags are changed.
Example: DAD B
Opcode Operand Description6 SUB R Subtract register or memory to accumulator
MThe contents of the register or memory location are subtracted from
the contents of the accumulator.The result is stored in accumulator.If the operand is memory location, its address is specified by H-L pair.All flags are modified to reflect the result of subtraction.Example: SUB B or SUB M
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Opcode Operand Description
7 SBB R Subtract register or memory from
M accumulator with borrow
The contents of the register or memory location and Borrow Flag (i.e.CY)are subtracted from the contents of the accumulator.
The result is stored in accumulator.
If the operand is memory location, its address is specified by H-L pair.
All flags are modified to reflect the result of subtraction.
Example: SBB B or SBB M
Opcode Operand Description8 SUI 8-bit data Subtract immediate from accumulator
The 8-bit data is subtracted from the contents of the accumulator.The result is stored in accumulator.All flags are modified to reflect the result of subtraction.Example: SUI 45 H
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Opcode Operand Description
9 SBI 8-bit data Subtract immediate from accumulator
with borrow
The 8-bit data and the Borrow Flag (i.e. CY) is subtracted from thecontents of the accumulator.
The result is stored in accumulator.All flags are modified to reflect the result of subtraction.Example: SBI 45 H
Opcode Operand Description10 INR R Increment register or memory by 1
MThe contents of register or memory location are incremented by 1.
The result is stored in the same place.If the operand is a memory location, its address is specified by
the contents of H-L pair.Example: INR B or INR M
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Opcode Operand Description
11 INX R Increment register pair by 1
The contents of register pair are incremented by 1.
The result is stored in the same place.Example: INX H
Opcode Operand Description12 DCR R Decrement register or memory by 1
M
The contents of register or memory location are decremented by 1.The result is stored in the same place.If the operand is a memory location, its address is specified by
the contents of H-L pair.Example: DCR B or DCR M
Opcode Operand Description13 DCX R Decrement register pair by 1
The contents of register pair are decremented by 1.The result is stored in the same place.Example: DCX H IFETCE/IT/II Year/ IV
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Logical Instructions These instructions perform logical operations on
data stored in registers, memory and status flags.
The logical operations are:
AND OR
XOR
Rotate Compare
Complement
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AND OR XOR
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AND, OR, XOR Any 8-bit data, or the contents of register, or
memory location can logically have AND operation OR operation XOR operation
with the contents of accumulator.The result is stored in accumulator
Rotate
Each bit in the accumulator can be shifted eitherleft or right to the next position.
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Compare Any 8-bit data, or the contents of register, or memory
location can be compares for: Equality
Greater Than
Less Than
with the contents of accumulator.
The result is reflected in status flags.
Complement The contents of accumulator can be complemented.
Each 0 is replaced by 1 and each 1 is replaced by 0
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Opcode Operand Description
1 CMP R Compare register or memory
M with accumulator
The contents of the operand (register or memory) are comparedwith the contents of the accumulator.
Both contents are preserved .
The result of the comparison is shown by setting the flags of thePSW as follows:
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset.
Example: CMP B or CMP M
Opcode Operand Description2 CPI 8-bit data Compare immediate with accumulator
The 8-bit data is compared with the contents of accumulator.IFETCE/IT/II Year/ IV
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The values being compared remain unchanged.
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g p g
The result of the comparison is shown by setting the flags of thePSW as follows:
if (A) < data: carry flag is set
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset
Example: CPI 89H
Opcode Operand Description3 ANA R Logical AND register or memory
M with accumulator
The contents of the accumulator are logically ANDed with the contentsof register or memory.
The result is placed in the accumulator.If the operand is a memory location, its address is specified by thecontents of H-L pair.
S, Z, P are modified to reflect the result of the operation.CY is reset and AC is set.Example: ANA B or ANA M.IFETCE/IT/II Year/ IV
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Opcode Operand Description
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Opcode Operand Description
4 ANI 8-bit data logical AND immediate with accumulator
The contents of the accumulator are logically ANDed with the 8-bit data.
The result is placed in the accumulator.S, Z, P are modified to reflect the result.CY is reset, AC is set.Example: ANI 86H
Opcode Operand Description5 ORA R Logical OR register or memory
M with accumulator
The contents of the accumulator are logically ORed with the contentsof the register or memory.
The result is placed in the accumulator.If the operand is a memory location, its address is specified by the
contents of H-L pair.S, Z, P are modified to reflect the result.CY and AC are reset.Example: ORA B or ORA M.IFETCE/IT/II Year/ IV
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Opcode Operand Description
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Opcode Operand Description
6 ORI 8-bit data logical OR immediate with accumulator
The contents of the accumulator are logically ORed with the 8-bit data.
The result is placed in the accumulator.S, Z, P are modified to reflect the result.CY and AC are reset.Example: ORI 86H.
Opcode Operand Description7 XRA R Logical XOR register or memory
M with accumulator
The contents of the accumulator are XORed with the contents ofthe register or memory.
The result is placed in the accumulator.If the operand is a memory location, its address is specified by
the contents of H-L pair.S, Z, P are modified to reflect the result of the operation.CY and AC are reset.
Example: XRA B or XRA M.IFETCE/IT/II Year/ IV
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Opcode Operand Description
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Opcode Operand Description
8 XRI 8-bit data XOR immediate with accumulator
The contents of the accumulator are XORed with the 8-bit data.
The result is placed in the accumulator. S, Z, P are modified to reflect the result.
CY and AC are reset.
Example: XRI 86H.
Opcode Operand Description9 RLC NONE Rotate accumulator Left
Each binary bit of the accumulator is rotated left by one position.Bit D7 is placed in the position of D0 as well as in the Carry flag.
CY is modified according to bit D7.S, Z, P, AC are not affected.Example: RLC.
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Opcode Operand Description
10 RRC NONE Rotate accumulator Right
Each binary bit of the accumulator is rotated right by one position.
Bit D0 is placed in the position of D7 as well as in the Carry flag.CY is modified according to bit D0.S, Z, P, AC are not affected.Example: RRC.
Opcode Operand Description11 RAL NONE Rotate accumulator Left through Carry
Each binary bit of the accumulator is rotated left by one positionthrough the Carry flag.
Bit D7 is placed in the Carry flag, and the Carry flag is placed in the
least significant position D0.CY is modified according to bit D7.S, Z, P, AC are not affected.Example: RAL.
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Opcode Operand Description
12 RAR NONE Rotate accumulator Right through Carry
Each binary bit of the accumulator is rotated right by one positionthrough the Carry flag.
Bit D0 is placed in the Carry flag, and the Carry flag is placed in themost significant position D7.
CY is modified according to bit D0.
S, Z, P, AC are not affected.
Example: RAR.
Opcode Operand Description13 CMA NONE Complement accumulator
The contents of the accumulator are complemented.No flags are affected.Example: CMA.
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Opcode Operand Description
14 CMC NONE Complement Carry
The Carry flag is complemented.
No other flags are affected.Example: CMC.
Opcode Operand Description
15 STC NONE Set Carry
The Carry flag is set to 1.No other flags are affected.Example: STC.
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Branching Instructions
The branching instruction alter the normalsequential flow.
These instructions alter either
unconditionally or conditionally
Opcode Operand Description1 JMP 16-bit Address Jump Unconditionally
The program sequence is transferred to the memorylocation specified by the 16-bit address given in theoperand.Example: JMP 2034 H.
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Jump conditionally
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JNZ Not Zero (Z = 0)JZ Zero (Z = 1)JNC No Carry (C = 0)JC Carry (C = 1)JPO Parity Odd (P = 0)JPE Parity Even (P = 1)JP Plus (S = 0)
JM Minus (S = 1)
Stack I/O, and Machine Control
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Instructions:
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The following instructions affect the Stackand/or Stack Pointer:
PUSH Push Two bytes of Data onto the StackPOP Pop Two Bytes of Data off the StackXTHL Exchange Top of Stack with H & LSPHL Move content of H & L to Stack Pointer
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The I/0 instructions are as follows:
IN Initiate Input OperationOUT Initiate Output Operation
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The Machine Control instructions are as
follows:EI Enable Interrupt SystemDI Disable Interrupt System
HLT HaltNOP No OperationSIM Set Interrupt Mask
RIM Read Interrupt Mask
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SIM instruction Format
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RIM instruction Format
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8085 Programming Model
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8085 Programming Model
ProgrammingRegisters
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8085Mnemonics
HexCode
BinaryCode
Flow
Chart
Manual
LookupMonitor
Program
To memory for
Storage
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Timing Diagram is a graphicalrepresentation. It representsthe execution time taken by
each instruction in a graphicalformat. The execution time isrepresented in T-states.
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Instruction Cycle:
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y
The time required to execute an instructionis called instruction cycle.
Machine Cycle:
The time required to access the memory or
input/output devices is called machine cycle.
T-State:
The machine cycle and instruction cycle
takes multiple clock periods.A portion of an operation carried out in onesystem clock period is called as T-state.
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MACHINE CYCLES OF 8085
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MACHINE CYCLES OF 8085:
The 8085 microprocessor has 5 (seven)basic machine cycles. They are
Opcode fetch cycle (4T)
Memory read cycle (3 T)
Memory write cycle (3 T)
I/O read cycle (3 T)
I/O write cycle (3 T)
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Each instruction of the 8085 processorconsists of one to five machine cycles, i.e.,when the 8085 processor executes aninstruction, it will execute some of themachine cycles in a specific order.
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Ti i di f STA 526AH
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Timing diagram for STA 526AH.
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Timing diagram for IN C0H
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Timing diagram for IN C0H
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Ti i di f MVI B 43H
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Timing diagram for MVI B, 43H.
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S l P
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Sample Program
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Sample problem
(4000H) = 14H
(4001H) = 89H
Result = 14H + 89H = 9DH
Source program
LXI H 4000H : HL points 4000H
MOV A, M : Get first operand
INX H : HL points 4001H
ADD M : Add second operand
INX H : HL points 4002HMOV M, A : Store result at 4002H
HLT :Terminate program execution
Add two 8-bit numbers
Sample ProgramAdd two 16-bit numbers
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Sample problem:(4000H) = 15H(4001H) = 1CH
(4002H) = B7H(4003H) = 5AHResult = 1C15 + 5AB7H = 76CCH(4004H) = CCH(4005H) = 76H
Source Program 1:
LHLD 4000H : Get first I6-bit number in HLXCHG : Save first I6-bit number in DELHLD 4002H : Get second I6-bit number in HLMOV A, E : Get lower byte of the first numberADD L : Add lower byte of the second numberMOV L, A : Store result in L registerMOV A, D : Get higher byte of the first numberADC H : Add higher byte of the second numberwith carryMOV H, A : Store result in H registerSHLD 4004H : Store I6-bit result in memory locations
4004H and 4005H.HLT : Terminate program execution
Sample ProgramMultiply two 8-bit numbersS m l bl m 1
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Sample problem 1:(2200H) = 03H
(2201H) = B2H
Result = B2H + B2H + B2H = 216H
(2300H) = 16H(2301H) = 02H
Source program :
LDA 2200H
MOV E, A
MVI D, 00 : Get the first number inDE register pair
LDA 2201H
MOV C, A : Initialize counter
LX I H, 0000 H : Result = 0
BACK: DAD D : Result = result +
first number
DCR C : Decrement countJNZ BACK : If count 0 repeat
SHLD 2300H : Store result
HLT : Terminate program