Unit 3 Session- 2

7/26/2019 Unit 3 Session- 2

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MICROPROCESSOR &COMPUTERARCHITECTURE

4CS253 / UE 4CS253

UNIT-3

Session 2

CACHE MEMORY - ANINTRODUCTION


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CACHE MEMORIES

Processor is much !s"er "h!n "he m!in memor#$ As a result, the processor has to spend much of its

time waiting while instructions and data are beingfetched from the main memory.

Major obstacle towards achieving good performance.

S%ee o "he m!in memor# c!nno" 'e incre!se'e#on ! cer"!in %oin".

Cache memory is an architectural arrangement whichmakes the main memory appear faster to the processorthan it really is.

Cache memory is based on the property of computerprograms known as (oc!(i"# o reerence.


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)OCA)ITY O* RE*ERENCE

Analysis of programs indicates that manyinstructions in localied areas of a program aree!ecuted repeatedly during some period of time,while the others are accessed relatively lessfre"uently.

#hese instructions may be the ones in a loop, nested loop orfew procedures calling each other repeatedly.

#his is called locality of reference.

#emporal locality of reference$

%ecently e!ecuted instruction is likely to be e!ecuted againvery soon.

&henever an instruction or data is needed for the 'rst time,

it should be brought into a cache. (t will hopefully be usedagain repeatedly.


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)OCA)ITY O* RE*ERENCE +CONTD$$,

)patial locality of reference$ (nstructions with addresses close to a recently

instruction are likely to be e!ecuted soon.

(nstead of fetching just one item from the mainmemory to the cache at a time, several items thathave addresses adjacent to the item being fetchedmay be useful.

#he term block refers to a set of contiguousaddresses locations of some sie.


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CACHEMEMORIES

Cache Main

memory

Processor

* Cache is the name given to the highest or 'rst level of memoryhierarchy

encountered after the address leaves the processor.* +rocessor issues a %ead re"uest, a block line run, of words istransferred from

the main memory to the cache, one word at a time.* )ubse"uent references to the data in this block of words arefound in the cache.* At any given time, only some blocks in the main memory areheld in the cache.

which blocks in the main memory are in the cache isdetermined by a mapping


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CACHE MEMORIES +CONTD$$,

* -!istence of a cache is transparent to the processor. #heprocessor issues

%ead and &rite re"uests in the same manner.* (f the data is in the cache it is called a %ead or &rite hit thatis CACHE HIT..

* Re! hi" #he data is obtained from the cache.

* /ri"e hi"0 Cache is a replica of the contents of the main memory.

Contents of the cache and the main memory may beupdatedsimultaneously. This is "he 1ri"e-"hrouh %ro"oco(.

/pdate the contents of the cache, and mark it as updatedby setting a bit

known as the dirty bit or modi'ed bit.#he contents of the main memory are updated when this


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(f the data is not present in the cache, then a Re! missor /ri"e missoccurs, CACHE MISS..

#ime re"uired for a cache miss depends on both latency 0bandwidth.

)!"enc# 0#ime re"uired to retrieve the 'rst word of the

block. 4!n1i"h0#ime re"uired to retrieve the rest of the block.Re! miss0 1lock of words containing this re"uested word is

transferred from the

memory. After the block is transferred, the desired word is

forwarded to theprocessor.

#he desired word may also be forwarded to the

processor as soon as it istransferred without waiting for the entire block to be


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* A bit called as valid bit is provided for each block.

* (f the block contains valid data, then the bit is set to 2, else it is 3.* 4alid bits are set to 3, when the power is just turned on.* &hen a block is loaded into the cache for the 'rst time, the valid bit isset to 2.

* 5ata transfers between main memory and disk occur directly bypassingthe cache.* &hen the data on a disk changes, the main memory block is alsoupdated.* 6owever, if the data is also resident in the cache, then the valid bit isset to 3.

* &hat happens if the data in the disk and main memory changes andthe writeback protocol is being used7

* (n this case, the data in the cache may also have changed and isindicated by the

dirty bit.* #he copies of the data in the cache, and the main memory are


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CACHE MEMORIES +CONTD$$,- /RITE4U**ER

/ri"e-"hrouh0* -ach write operation involves writing to the main memory.* (f the processor has to wait for the write operation to becomplete, it slows

down the processor.* +rocessor does not depend on the results of the writeoperation.* &rite bu8er can be included for temporary storage of writere"uests.* +rocessor places each write re"uest into the bu8er andcontinues e!ecution.

* (f a subse"uent %ead re"uest references data which is still inthe write bu8er,

then this data is referenced in the write bu8er./ri"e-'!c0* 1lock is written back to the main memory when it is

replaced.* (f the processor waits for this write to complete, before


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Mapping functions

Mapping functions determine how memory blocks are placed in thecache.

A sim%(e %rocessor e5!m%(e0

Cache consisting of 2;< blocks of 2= words each.

#otal sie of cache is ;3>< ?;@ words.

Main memory is addressable by a 2=bit address. Main memory has =>@ words.

Main memory has >@ blocks of 2= words each.

Consecutive addresses refer to consecutive words.

Three m!%%in unc"ions0

Direc" m!%%in Associ!"i6e m!%%in

Se"-!ssoci!"i6e m!%%in.


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DIRECT MAPPIN7

Mainmemory

Block 0

Block 1

Block 127

Block 128

Block 129

Block 255

Block 256

Block 257

Block 4095

7 4

Main memory address

Tag Block Word

5

tag

tag

tag

Cache

Block 0

Block 1

Block 127

1lock j of the main memory maps to j

modulo 2;< ofthe cache. 3 maps to 3, 2;B maps to 2.

More than one memory block is mapped

onto thesame position in the cache.

* May lead to contention for cache blockseven if the

cache is not full.* %esolve the contention by allowing newblock to

replace the old block, leading to a trivialreplacement

algorithm.

* Memory address is divided into three'elds$ ow order > bits determine one of the2= words

in a block. &hen a new block is brought into the

cache,

the ne!t D bits determine which cacheblock this


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ASSOCIATI8E MAPPIN7

Mainmemory

Block 0

Block 1

Block 127

Block 128

Block 129

Block 255

Block 256

Block 257

Block 4095

tag

tag

tag

Cache

Block 0

Block 1

Block 127

412

Main memory address

Tag Word

* Main memory block can be placed into

anycache position.

* Memory address is divided into two'elds$ ow order > bits identify the wordwithin a

block. 6igh order 2; bits or tag bitsidentify a

memory block when it is resident inthe cache.* :le!ible, and uses cache space

eHciently.* %eplacement algorithms can be usedto replace

an e!isting block in the cache whenthe cache is

full.* Cost is higher than directmapped


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SET-ASSOCIATI8E MAPPIN7

Mainmemory

Block 0

Block 1

Block 127

Block 128

Block 129

Block 255

Block 256

Block 257

Block 4095

tag

tag

tag

Cache

Block 0

Block 1

Block 126

tag

tag

Block 2

Block 3

tagBlock 127

Set 0

Set 1

Set 63

Main memory address

6 6 4

Tag Set Word

1locks of cache are grouped into sets.

Mapping function allows a block of themain

memory to reside in any block of aspeci'c set.

5ivide the cache into => sets, with twoblocks per set.

Memory block 3, =>, 2;< etc. map toblock 3, and they can occupy either ofthe two positions.

Memory address is divided into three'elds$

= bit 'eld determines the set

number. 6igh order = bit 'elds are compared

to the tag 'elds of the two blocks in a set. )etassociative mapping combination

of direct and associative mapping. Iumber of blocks per set is a design


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REP)ACEMENT A)7ORITHMS

5irectmapped cache, the position that each memory block occupiesin the cache is '!ed. As a result, the replacement strategy is trivial.

Associative and setassociative mapping provide some Ge!ibility indeciding which memory block occupies which cache block.

&hen a new block is to be transferred to the cache, and all thepositions it may occupy are full, which block in the cache should bereplaced7

&hen a miss occurs, cache controller must select a block to bereplaced with the desired data.

#here are three primary strategies employed for selectingwhich block to replace$

R!nom

)e!s" Recen"(# Use )RU.

*irs" In *irs" Ou" *I*O.


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REP)ACEMENT A)7ORITHMS

R!nom0#o spread allocation uniformly, candidate blocks arerandomly selected.

)e!s" Recen"(# Use +)RU,0ocality of reference suggests that it may be okay to replace the blockthat has gone the longest time without being referenced.

#his block is called east %ecently /sed ?%/ block, and thereplacement strategy is called %/ replacement algorithm.%/ algorithm has been used e!tensively.

(t provides poor performance in some cases. +erformance of the %/ algorithm may be improved by

introducing a small amount of randomness into which block

might be replaced.

*irs" In *irs" Ou"09ther replacement algorithms include removing the oldest block.

6owever, theydisregard the locality of reference principle and do not perform as

well.


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MEMORY HIERARCHY 9UESTIONS

9:0 /here c!n ! '(oc 'e %(!ce in "he u%%er (e6e( ;- 1lock +lacement

920 Ho1 is ! '(oc oun i i" is in "he u%%er (e6e(;- 1lock (denti'cation.

930 /hich '(oc shou( 'e re%(!ce on ! miss;

1lock %eplacement.9


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CACHE MEMORY

Unit 3 Session- 2

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