UNIT 2. ADDITION & SUBTRACTION OF SIGNED NUMBERS.
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Transcript of UNIT 2. ADDITION & SUBTRACTION OF SIGNED NUMBERS.
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UNIT 2
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ADDITION & SUBTRACTION OF SIGNED NUMBERS
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xi Yi carry ci sum si carry-out ci+1
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
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Logic for single stage
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Logic for single stage
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n-bit ripple carry adder
• A cascaded connection of n full adder blocks can be used to add n-bit numbers .since carry propagate or ripple through the adder it is called an n-bit ripple carry adder.
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DESIGN OF FAST ADDERS
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DESIGN OF FAST ADDERS
• Two approaches to reduce delay in adders– 1st approach-Fastest possible electronic
technology in implementing ripple carry logic design
– 2nd approach-Use an augmented logic gate network structure that is larger
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MULTIPLICATION OF POSITIVE NUMBERS
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• Product of n digit numbers can be accommodated in 2n digits
• Product of 4bit numbers will fit into 8bits• Refer pg-378 4th para alone for register
configuration diagram
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Manual multiplication
1 1 0 1 x multiplicand M 1 0 1 1 multiplier Q 1 1 0 1 1 1 0 1 0 0 0 0 1 1 0 1
1 0 0 0 1 1 1 1 Product P
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REGISTER CONFIGURATION
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SIGNED OPERAND MULTIPLICATIONBOOTH ALGORITHM
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BOOTH MULTIPLIER TABLE
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FAST MULTIPLICATION1.BIT PAIR RECODING OF
MULTIPLIER
2.CARRY SAVE ADDITION OF SUMMANDS
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• 1.BIT PAIR RECODING OF MULTIPLIER
2.CARRY SAVE ADDITION OF SUMMANDS
Have been used in various ways by the high performance processor to reduce the time needed to perform multiplication
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BIT PAIR RECODING OF MULTIPLIER
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• A technique called Bit pair recoding halves the maximum number of summands
• It is derived directly from booth algorithm
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CARRY SAVE ADDITION OF SUMMANDS
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• Multiplication requires the addition of several summands
• A technique called carry save addition(CSA) speeds up the addition process
• Instead of letting the carries ripples along the rows, they can be saved and introduced into the next row ,at the correct weighted position
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• Delay through carry save array is somewhat less than delay through ripple carry array
• A more significant reduction in delay can be achieved as follows– Consider addition of many summands,as required
in multiplication of longer operand– Group the summands in three and perform carry
save addition on each of these group
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• In parallel to generate a set of S and C– Next we group all of the S and C vectors into three
and perform carry save addition on them,generate further set of S and C
- We continue this process until there are only two vectors remaining
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INTEGER DIVISION1.Restoring Division
2.Non Restoring Division1.
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Restoring Division
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Non Restoring Division
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