Unit 13Unit 13Analysis ofAnalysis of

Clocked Sequential CircuitsClocked Sequential Circuits

Ku-Yaw ChangKu-Yaw Changcanseco@mail.dyu.edu.twcanseco@mail.dyu.edu.tw

Assistant Professor, Department of Assistant Professor, Department of Computer Science and Information EngineeringComputer Science and Information Engineering

Da-Yeh UniversityDa-Yeh University

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OutlineOutline

13.113.1 A Sequential Parity CheckerA Sequential Parity Checker

13.213.2 Analysis by Signal Tracing andAnalysis by Signal Tracing and Timing Charts Timing Charts

13.3 State Tables and Graphs13.3 State Tables and Graphs

13.4 General Models for Sequential Circuits13.4 General Models for Sequential Circuits

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State TablesState Tables

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State GraphState Graph

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Construct the State TableConstruct the State Table

1.1. Determine the flip-flop input equations and the Determine the flip-flop input equations and the output equations from the circuit.output equations from the circuit.

2.2. Derive the next-state equation for each flip-flop Derive the next-state equation for each flip-flop from its input equations, using one of the from its input equations, using one of the following relations:following relations:

D flip-flop QD flip-flop Q++ = D = DT flip-flop QT flip-flop Q++ = T = T Q Q

: :3.3. Plot a next-state map for each flip-flop.Plot a next-state map for each flip-flop.4.4. Combine these maps to form the state table.Combine these maps to form the state table.

A transition tableA transition table

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First ExampleFirst Example

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Construct the State TableConstruct the State Table

1.1. Determine the flip-flop input equations and the Determine the flip-flop input equations and the output equations from the circuit.output equations from the circuit.

2.2. Derive the next-state equation for each flip-flop Derive the next-state equation for each flip-flop from its input equations, using one of the from its input equations, using one of the following relations:following relations:

D flip-flop QD flip-flop Q++ = D = DT flip-flop QT flip-flop Q++ = T = T Q Q

: :3.3. Plot a next-state map for each flip-flop.Plot a next-state map for each flip-flop.4.4. Combine these maps to form the state table.Combine these maps to form the state table.

A transition tableA transition table

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Construct the State TableConstruct the State Table

Determine the flip-flop input equations and the Determine the flip-flop input equations and the output equations from the circuit.output equations from the circuit.

DDAA = X = X B’ B’

DDBB = X + A = X + A

Z = A Z = A B B

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Construct the State TableConstruct the State Table

1.1. Determine the flip-flop input equations and the Determine the flip-flop input equations and the output equations from the circuit.output equations from the circuit.

2.2. Derive the next-state equation for each flip-flop Derive the next-state equation for each flip-flop from its input equationsfrom its input equations, using one of the , using one of the following relations:following relations:

D flip-flop QD flip-flop Q++ = D = DT flip-flop QT flip-flop Q++ = T = T Q Q

: :3.3. Plot a next-state map for each flip-flop.Plot a next-state map for each flip-flop.4.4. Combine these maps to form the state table.Combine these maps to form the state table.

A transition tableA transition table

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Construct the State TableConstruct the State Table

2.2. Derive the next-state equation for each flip-flop Derive the next-state equation for each flip-flop from its input equations, using one of the from its input equations, using one of the following relations:following relations:

D flip-flop D flip-flop QQ++ = D = DD-CE flip-flop D-CE flip-flop QQ++ = D = D ·· CE + Q CE + Q ·· CE’ CE’T flip-flop T flip-flop QQ++ = T = T Q QS-R flip-flop S-R flip-flop QQ++ = S + R’Q = S + R’QJ-K flip-flop J-K flip-flop QQ++ = JQ’ + K’Q = JQ’ + K’Q

AA++ = X = X B’ B’ BB++ = X + A = X + A

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Construct the State TableConstruct the State Table

1.1. Determine the flip-flop input equations and the Determine the flip-flop input equations and the output equations from the circuit.output equations from the circuit.

2.2. Derive the next-state equation for each flip-flop Derive the next-state equation for each flip-flop from its input equations, using one of the from its input equations, using one of the following relations:following relations:

D flip-flop QD flip-flop Q++ = D = DT flip-flop QT flip-flop Q++ = T = T Q Q

: :3.3. Plot a next-state map for each flip-flop.Plot a next-state map for each flip-flop.4.4. Combine these maps to form the state table.Combine these maps to form the state table.

A transition tableA transition table

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Construct the State TableConstruct the State Table

3.3. Plot a next-state map for each flip-flop.Plot a next-state map for each flip-flop.

A+ = X B’B+ = X + A

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Construct the State TableConstruct the State Table

1.1. Determine the flip-flop input equations and the Determine the flip-flop input equations and the output equations from the circuit.output equations from the circuit.

2.2. Derive the next-state equation for each flip-flop Derive the next-state equation for each flip-flop from its input equations, using one of the from its input equations, using one of the following relations:following relations:

D flip-flop QD flip-flop Q++ = D = DT flip-flop QT flip-flop Q++ = T = T Q Q

: :3.3. Plot a next-state map for each flip-flop.Plot a next-state map for each flip-flop.4.4. Combine these maps to form the state table.Combine these maps to form the state table.

A transition tableA transition table

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Construct the State TableConstruct the State Table

4.4. Combine these maps to form the state table.Combine these maps to form the state table. A transition tableA transition table

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Moore State GraphMoore State Graph

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Second ExampleSecond Example

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Construct the State TableConstruct the State Table

Determine the flip-flop input equations and the Determine the flip-flop input equations and the output equations from the circuit.output equations from the circuit.

JJAA = XB, K = XB, KAA = X = X

JJBB = X, K = X, KBB = XA = XA

Z = XB’+XA+X’A’BZ = XB’+XA+X’A’B

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Construct the State TableConstruct the State Table

2.2. Derive the next-state equation for each flip-flop Derive the next-state equation for each flip-flop from its input equations, using one of the from its input equations, using one of the following relations:following relations:

D flip-flop D flip-flop QQ++ = D = DD-CE flip-flop D-CE flip-flop QQ++ = D = D ·· CE + Q CE + Q ·· CE’ CE’T flip-flop T flip-flop QQ++ = T = T Q QS-R flip-flop S-R flip-flop QQ++ = S + R’Q = S + R’QJ-K flip-flop J-K flip-flop QQ++ = JQ’ + K’Q = JQ’ + K’Q

AA++ = J = JAAA’ + KA’ + KAA’A = XBA’ + X’A’A = XBA’ + X’A

BB++ = J = JBBB’ + KB’ + KBB’B = XB’ + (AX)’B = XB’+ X’B + A’B’B = XB’ + (AX)’B = XB’+ X’B + A’B Z = X’A’B + XB’ + XAZ = X’A’B + XB’ + XA

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Construct the State TableConstruct the State Table

3.3. Plot a next-state and output map.Plot a next-state and output map.

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Construct the State TableConstruct the State Table

4.4. Combine these maps to form the state table.Combine these maps to form the state table.

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Mealy State GraphMealy State Graph

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Third ExampleThird Example

Serial AdderSerial Adderxxii yyii ccii cci+1i+1 ssii

00 00 00 00 00

00 00 11 00 11

00 11 00 00 11

00 11 11 11 00

11 00 00 00 11

11 00 11 11 00

11 11 00 11 00

11 11 11 11 11

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Timing DiagramTiming Diagram

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Serial AdderSerial Adder

Initially the carry flip-flop must be clearedInitially the carry flip-flop must be cleared CC00=0=0

Start by adding the least-significant Start by adding the least-significant (rightmost) bits in each word.(rightmost) bits in each word.

Reading the sum output just before the Reading the sum output just before the rising edge of the clockrising edge of the clock

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State GraphState Graph

A Mealy machineA Mealy machine Inputs: xInputs: xii and y and yii

Output: sOutput: sii

Two states represent Two states represent a carry (ca carry (cii)) SS00 for 0 and S for 0 and S11 for 1 for 1

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Multiple Inputs and OutputsMultiple Inputs and Outputs

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Multiple Inputs and OutputsMultiple Inputs and Outputs