7/10/2003 CS267 Lecure 2 1

Uniprocessor Optimizations and

Matrix Multiplication

BeBOP Summer 2002http://www.cs.berkeley.edu/~richie/bebop

7/10/2003 CS267 Lecure 2 2

Applications ...• Scientific simulation and modeling

• Weather and earthquakes• Cars and buildings• The universe

• Signal processing• Audio and image compression• Machine vision• Speech recognition

• Information retrieval• Web searching• Human genome

• Computer graphics and computational geometry• Structural models• Films: Final Fantasy, Shrek

7/10/2003 CS267 Lecure 2 3

… and their Building Blocks (Kernels)• Scientific simulation and modeling

• Matrix-vector/matrix-matrix multiply• Solving linear systems

• Signal processing• Performing fast transforms: Fourier, trigonometric, wavelet• Filtering• Linear algebra on structured matrices

• Information retrieval• Sorting• Finding eigenvalues and eigenvectors

• Computer graphics and computational geometry• Matrix multiply• Computing matrix determinants

7/10/2003 CS267 Lecure 2 4

Outline• Parallelism in Modern Processors• Memory Hierarchies• Matrix Multiply Cache Optimizations• Bag of Tricks

7/10/2003 CS267 Lecure 2 5

Modern Processors: Theory & Practice• Idealized Uniprocessor Model

• Execution order specified by program• Operations (load/store, +/*, branch) have roughly the same cost

• Processors in the Real World• Registers and caches

• Small amounts of fast memory• Memory ops have widely varying costs

• Exploit Instruction-Level Parallelism (ILP)• Superscalar — multiple functional units• Pipelined — decompose units of execution into parallel stages• Different instruction mixes/orders have different costs

• Why is this your problem?• In theory, compilers understand all this mumbo-jumbo and optimize

your programs; in practice, they don’t.

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What is Pipelining?

• In this example:• Sequential execution takes

4 * 90min = 6 hours• Pipelined execution takes

30+4*40+20 = 3.3 hours

• Pipelining helps throughput, but not latency

• Pipeline rate limited by slowest pipeline stage

• Potential speedup = Number pipe stages

• Time to “fill” pipeline and time to “drain” it reduces speedup

A

B

C

D

6 PM 7 8 9

Task

Order

Time

30 40 40 40 40 20

Dave Patterson’s Laundry example: 4 people doing laundry

wash (30 min) + dry (40 min) + fold (20 min)

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Limits of ILPHazards prevent next instruction from executing in its designated clock cycle

Task

Order

• Structural: single person to fold and put clothes away

• Data: missing socks• Control: dyed clothes need

to be rewashed

• Compiler will try to reduce these, but careful coding helps!

A

B

C

D

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Outline• Parallelism in Modern Processors• Memory Hierarchies• Matrix Multiply Cache Optimizations• Bag of Tricks

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Memory Hierarchy• Most programs have a high degree of locality in their accesses

• spatial locality: accessing things nearby previous accesses• temporal locality: reusing an item that was previously accessed

• Memory hierarchy tries to exploit locality

on-chip cacheregisters

datapath

control

processor

Secondary storage (Disk)

Second level

cache (SRAM)

Tertiary storage

(Disk/Tape/WWW)

Main memory

(DRAM)

Speed (ns): 1 10 100 10 ms 10 sec

Size (bytes): 100,1Ks Ms Gs Ts Ps

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Processor-DRAM Gap (latency)• Memory hierarchies are getting deeper

• Processors get faster more quickly than memory

µProc60%/yr.

DRAM7%/yr.

1

10

100

100019

8019

81

1983

1984

1985

1986

1987

1988

1989

1990

1991

1992

1993

1994

1995

1996

1997

1998

1999

2000

DRAM

CPU19

82

Processor-MemoryPerformance Gap:(grows 50% / year)

Perf

orm

ance

Time

“Moore’s Law”

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Cache Basics• Cache hit: in-cache memory access—cheap• Cache miss: non-cached memory access—expensive• Consider a tiny cache (for illustration only)

X000 X001

X010 X011

X100 X101

X110 X111

• Cache line length: # of bytes loaded together in one entry• Associativity

• direct-mapped: only one address (line) in a given range in cache• n-way: 2 or more lines with different addresses exist

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Experimental Study of Memory• Microbenchmark for memory system performance

(Saavedra ’92)

• time the following program for each size(A) and stride s

(repeat to obtain confidence and mitigate timer resolution)

for array A of size from 4KB to 8MB by 2x

for stride s from 8 Bytes (1 word) to size(A)/2 by 2x

for i from 0 to size by s

load A[i] from memory (8 Bytes)

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Memory Hierarchy on a Sun Ultra-IIi

L2: 2 MB, 36 ns

(12 cycles)

Sun Ultra-IIi, 333 MHz

L2: 64 byte line 8 K pages

L1: 16 byte line

Array size

Mem: 396 ns

(132 cycles)

L1: 16K, 6 ns

(2 cycle)

See www.cs.berkeley.edu/~yelick/arvindk/t3d-isca95.ps for details

7/10/2003 CS267 Lecure 2 14

Memory Hierarchy on a Pentium III

L1: 32 byte line ?

L2: 512 KB 60 ns

Katmai processor on Millennium, 550 MHz Array size

L1: 64K5 ns, 4-way?

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Lessons• True performance can be a complicated function of the

architecture• Slight changes in architecture or program change performance

significantly• To write fast programs, need to consider architecture• We would like simple models to help us design efficient algorithms• Is this possible?

• Next: Example of improving cache performance: blocking or tiling

• Idea: decompose problem workload into cache-sized pieces

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Outline• Parallelism in Modern Processors• Memory Hierarchies• Matrix Multiply Cache Optimizations• Bag of Tricks

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Note on Matrix Storage• A matrix is a 2-D array of elements, but memory

addresses are “1-D”• Conventions for matrix layout

• by column, or “column major” (Fortran default)• by row, or “row major” (C default)

01234

56789

1011121314

1516171819

0481216

1591317

26101418

37111519

Row majorColumn major

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Note on “Performance”• For linear algebra, measure performance as rate of

execution:• Millions of floating point operations per second (Mflop/s)• Higher is better• Comparing Mflop/s is not the same as comparing time unless flops are

constant!

• Speedup taken wrt time• Speedup of A over B = (Running time of B) / (Running time of A)

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Using a Simple Model of Memory to Optimize

⎟⎟⎠

⎞⎜⎜⎝

⎛⋅+⋅⋅=⋅+⋅qt

ttftmtff

mfmf

11

• Assume just 2 levels in the hierarchy, fast and slow• All data initially in slow memory

• m = number of memory elements (words) moved between fast and slow memory

• tm = time per slow memory operation• f = number of arithmetic operations• tf = time per arithmetic operation << tm

• q = f / m average number of flops per slow element access

• Minimum possible time = f* tf when all data in fast memory

• Actual time

• Larger q means time closer to minimum f * tf

Key to algorithm efficiency

Key to machine efficiency

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Warm up: Matrix-vector multiplication{implements y = y + A*x}for i = 1:n

for j = 1:ny(i) = y(i) + A(i,j)*x(j)

A(i,:)+= *

y(i)y(i) x(:)

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Warm up: Matrix-vector multiplication{read x(1:n) into fast memory}{read y(1:n) into fast memory}for i = 1:n

{read row i of A into fast memory}for j = 1:n

y(i) = y(i) + A(i,j)*x(j){write y(1:n) back to slow memory}

• m = number of slow memory refs = 3n + n2

• f = number of arithmetic operations = 2n2

• q = f / m ~= 2

• Matrix-vector multiplication limited by slow memory speed

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“Naïve” Matrix Multiply{implements C = C + A*B}for i = 1 to n

for j = 1 to nfor k = 1 to n

C(i,j) = C(i,j) + A(i,k) * B(k,j)

= + *A(i,:)C(i,j) C(i,j)

B(:,j)

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“Naïve” Matrix Multiply{implements C = C + A*B}for i = 1 to n{read row i of A into fast memory}for j = 1 to n

{read C(i,j) into fast memory}{read column j of B into fast memory}for k = 1 to n

C(i,j) = C(i,j) + A(i,k) * B(k,j){write C(i,j) back to slow memory}

C(i,j)

= + * B(:,j)

A(i,:)C(i,j)

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“Naïve” Matrix MultiplyNumber of slow memory references on unblocked matrix multiply

m = n3 read each column of B n times+ n2 read each row of A once + 2n2 read and write each element of C once= n3 + 3n2

So q = f / m = 2n3 / (n3 + 3n2)~= 2 for large n, no improvement over matrix-vector multiply

= + *A(i,:)C(i,j) C(i,j)

B(:,j)

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Blocked (Tiled) Matrix MultiplyConsider A,B,C to be N by N matrices of b by b subblocks where b=n / N is

called the block size for i = 1 to N

for j = 1 to N{read block C(i,j) into fast memory}for k = 1 to N

{read block A(i,k) into fast memory}{read block B(k,j) into fast memory}C(i,j) = C(i,j) + A(i,k) * B(k,j) {do a matrix multiply on blocks}

{write block C(i,j) back to slow memory}

= + *A(i,k)C(i,j) C(i,j)

B(k,j)

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Blocked (Tiled) Matrix MultiplyRecall:

m : # of moves from slow to fast memoryMatrix is n x n, and N x N blocks each of size b x bf = 2n3 for this problemq = f / m is algorithmic memory efficiency

So:m = N*n2 read each block of B N3 times (N3 * n/N * n/N)

+ N*n2 read A+ 2n2 read and write each block of C once

= (2N + 2) * n2

So q = f / m = 2n3 / ((2N + 2) * n2)~= n / N = b for large n

So we can improve performance by increasing the block size b Can be much faster than matrix-vector multiply (q=2)

7/10/2003 CS267 Lecure 2 27

Limits to Optimizing Matrix Multiply

Blocked algorithm has ratio q ~= b• Larger block size => faster implementation• Limit: All three blocks from A,B,C must fit in fast

memory (cache): 3b2 <= M

So: q ~= b <= sqrt(M/3)

Lower bound:Theorem (Hong & Kung, 1981): Any reorganization of

this algorithm (using only algebraic associativity) is limited to: q = O(sqrt(M))

7/10/2003 CS267 Lecure 2 28

Basic Linear Algebra Subroutines• Industry standard interface (evolving)• Hardware vendors, others supply optimized implementations• History

• BLAS1 (1970s): • vector operations: dot product, saxpy (y=α*x+y), etc• m=2*n, f=2*n, q ~1 or less

• BLAS2 (mid 1980s)• matrix-vector operations: matrix vector multiply, etc• m=n^2, f=2*n^2, q~2, less overhead • somewhat faster than BLAS1

• BLAS3 (late 1980s)• matrix-matrix operations: matrix matrix multiply, etc• m >= 4n^2, f=O(n^3), so q can possibly be as large as n, so BLAS3 is

potentially much faster than BLAS2

• Good algorithms used BLAS3 when possible (LAPACK)• See www.netlib.org/blas, www.netlib.org/lapack

7/10/2003 CS267 Lecure 2 29

BLAS speeds on an IBM RS6000/590Peak speed = 266 Mflops

BLAS 3

BLAS 2BLAS 1

Peak

BLAS 3 (n-by-n matrix matrix multiply) vsBLAS 2 (n-by-n matrix vector multiply) vsBLAS 1 (saxpy of n vectors)

7/10/2003 CS267 Lecure 2 30

Locality in Other Algorithms• The performance of any algorithm is limited by q• In matrix multiply, we increase q by changing

computation order• increased temporal locality

• For other algorithms and data structures, even hand-transformations are still an open problem

• sparse matrices (reordering, blocking)• trees (B-Trees are for the disk level of the hierarchy)• linked lists (some work done here)

7/10/2003 CS267 Lecure 2 31

Outline• Parallelism in Modern Processors• Memory Hierarchies• Matrix Multiply Cache Optimizations• Bag of Tricks

7/10/2003 CS267 Lecure 2 32

Tiling Alone Might Not Be Enough• Naïve and a “naïvely tiled” code

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Optimizing in Practice• Tiling for registers

• loop unrolling, use of named “register” variables

• Tiling for multiple levels of cache• Exploiting fine-grained parallelism in processor

• superscalar; pipelining

• Complicated compiler interactions• Hard to do by hand (but you’ll try)• Automatic optimization an active research area

• BeBOP: www.cs.berkeley.edu/~richie/bebop• PHiPAC: www.icsi.berkeley.edu/~bilmes/phipac

in particular tr-98-035.ps.gz• ATLAS: www.netlib.org/atlas

7/10/2003 CS267 Lecure 2 34

PHiPAC: Portable High Performance ANSI C

Speed of n-by-n matrix multiply on Sun Ultra-1/170, peak = 330 MFlops

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ATLAS (DGEMM n = 500)

0.0

100.0

200.0

300.0

400.0

500.0

600.0

700.0

800.0

900.0

AMD Ath

lon-600

DEC ev56

-533

DEC ev6-5

00HP90

00/73

5/135

IBM PPC60

4-112

IBM Power2

-160

IBM Power3

-200

Pentiu

m Pro-20

0Pen

tium II-

266

Pentiu

m III-55

0

SGI R10

000ip

28-20

0

SGI R12

000ip

30-27

0

Sun U

ltraS

parc2-2

00

Architectures

MFL

OPS

Vendor BLASATLAS BLASF77 BLAS

Source: Jack Dongarra

• ATLAS is faster than all other portable BLAS implementations andit is comparable with machine-specific libraries provided by the vendor.

7/10/2003 CS267 Lecure 2 36

Removing False Dependencies• Using local variables, reorder operations to remove false

dependencies

a[i] = b[i] + c;a[i+1] = b[i+1] * d;

false read-after-write hazardbetween a[i] and b[i+1]

float f1 = b[i];float f2 = b[i+1];

a[i] = f1 + c;a[i+1] = f2 * d;

• With some compilers, you can say explicitly (via flag or pragma) that a and b are not aliased.

7/10/2003 CS267 Lecure 2 37

Exploit Multiple Registers• Reduce demands on memory bandwidth by pre-loading

into local variables

while( … ) {*res++ = filter[0]*signal[0]

+ filter[1]*signal[1]+ filter[2]*signal[2];

signal++;}

float f0 = filter[0];float f1 = filter[1];float f2 = filter[2];while( … ) {

*res++ = f0*signal[0]+ f1*signal[1]+ f2*signal[2];

signal++;}

also: register float f0 = …;

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Minimize Pointer Updates• Replace pointer updates for strided memory addressing

with constant array offsets

f0 = *r8; r8 += 4;f1 = *r8; r8 += 4;f2 = *r8; r8 += 4;

f0 = r8[0];f1 = r8[4];f2 = r8[8];r8 += 12;

7/10/2003 CS267 Lecure 2 39

Loop Unrolling• Expose instruction-level parallelism

float f0 = filter[0], f1 = filter[1], f2 = filter[2];float s0 = signal[0], s1 = signal[1], s2 = signal[2];*res++ = f0*s0 + f1*s1 + f2*s2;do {

signal += 3;s0 = signal[0];res[0] = f0*s1 + f1*s2 + f2*s0;

s1 = signal[1];res[1] = f0*s2 + f1*s0 + f2*s1;

s2 = signal[2];res[2] = f0*s0 + f1*s1 + f2*s2;

res += 3;} while( … );

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Expose Independent Operations• Hide instruction latency

• Use local variables to expose independent operations that can execute in parallel or in a pipelined fashion

• Balance the instruction mix (what functional units are available?)

f1 = f5 * f9;f2 = f6 + f10;f3 = f7 * f11;f4 = f8 + f12;

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Copy optimization• Copy input operands or blocks

• Reduce cache conflicts• Constant array offsets for fixed size blocks• Expose page-level locality

Original matrix(numbers are addresses)

Reorganized into2x2 blocks

0123

4567

891011

12131415

0145

2367

8 109 1112 1314 15

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Summary• Performance programming on uniprocessors requires

• understanding of fine-grained parallelism in processor • produce good instruction mix

• understanding of memory system• levels, costs, sizes• improve locality

• Blocking (tiling) is a basic approach • Techniques apply generally, but the details (e.g., block size) are

architecture dependent• Similar techniques are possible on other data structures and

algorithms

• Now it’s your turn: Homework 0 (due 6/25/02)• http://www.cs.berkeley.edu/~richie/bebop/notes/matmul2002

7/10/2003 CS267 Lecure 2 43

End

(Extra slides follow)

7/10/2003 CS267 Lecure 2 44

Example: 5 Steps of MIPS DatapathFigure 3.4, Page 134 , CA:AQA 2e by Patterson and Hennessy

MemoryAccess

WriteBack

InstructionFetch

Instr. DecodeReg. Fetch

ExecuteAddr. Calc

ALU

Mem

ory

RegFile

MU

XM

UX

Data

Mem

ory

MU

X

SignExtend

Zero?

IF/ID

ID/EX

MEM

/WB

EX/M

EM4

Adder

Next SEQ PC Next SEQ PC

RD RD RD WB

Dat

a

• Pipelining is also used within arithmetic units– a fp multiply may have latency 10 cycles, but throughput of 1/cycle

Next PC

Address

RS1

RS2

Imm

MU

X

7/10/2003 CS267 Lecure 2 45

Dependences (Data Hazards) Limit Parallelism• A dependence or data hazard is one of the following:

• true of flow dependence:• a writes a location that b later reads• (read-after write or RAW hazard)

• anti-dependence• a reads a location that b later writes• (write-after-read or WAR hazard)

• output dependence• a writes a location that b later writes• (write-after-write or WAW hazard)

true anti outputa = = a

= a a =

a = a =

7/10/2003 CS267 Lecure 2 46

Observing a Memory Hierarchy

Dec Alpha, 21064, 150 MHz clock

0

100

200

300

400

500

600

1 4 16 64 256 1K 4K 16K 64K 256K 1M 4M

Tim

e (

na

no

seco

nd

s)

Stride (bytes)

DEC Workstation Memory Hierarchy

8 M4 M2 M1 M

512 K256 K128 K64 K32 K16 K8 K4 K

L2: 512 K, 52 ns (8 cycles)

L1: 8K, 6.7 ns (1 cycle)

Mem: 300 ns (45 cycles)

32 byte cache line

8 K pages

See www.cs.berkeley.edu/~yelick/arvindk/t3d-isca95.ps for details