UNDERSTANDINGBEHAVIORAL SYNTHESIS

A Practical Guide to High-Level Design

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UNDERSTANDING BEHAVIORAL SYNTHESIS

A Practical Guide to High-Level Design

John P. Elliott

SPRINGER SCIENCE+BUSINESS MEDIA, LLC

...... " Library of Congress Cataloging-in-Publication Data

Elliott, John P., 1966-Understanding behavioral synthesis: a practical guide to high

- level design / John P. Elliott p. cm.

Includes bibliographical references.

Additional material to this book can be downloaded from http://extras.springer.com.

ISBN 978-1-4613-7300-1 ISBN 978-1-4615-5059-4 (eBook) DOI 10.1007/978-1-4615-5059-4 1. Digital integrated circuits--Design and construction--Data

processing. 2. System design--Data processing. 3. VHDL (Hardware description language) 4. Abstraction. I. Title. TK7874.65.E38 1999

621.3815--dc21 99-27961

Copyright © 1999 by Springer Science+Business Media New York Originally published by Kluwer Academic Publishers in 1999 Softcover reprint of the hardcover 1st edition 1999

Second printing with corrections 2000.

CIP

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo­copying, recording, or otherwise, without the prior written permission of the publisher, Springer Science+Business Media, LLC.

Printed on acid-free paper.

Table of Contents

Preface

Acknowledgements

1. How Did We Get Here?

Chapter 1 provides a brief history of electronic design automation from ICmask generation to schematic capture to logic synthesis and finally tobehavioral synthesis. Extreme market pressures and rapid changes insilicon technology have changed the design process which has in turn led tothe development of design tools of increasing complexity.

1.1 Step Back In Time

1.2 The Year Is 1981...

1.3 The Year Is 1986...

1.4 The Year is 1991...

1.5 Today...

2. An Introduction to Behavioral Synthesis

Chapter 2 introduces the behavioral design process. The ability to evaluatemultiple architectures (which may not be practical in traditional systemdesign) is an important advantage of the behavioral design process.

2.1 Why Behavioral Synthesis?

Design Space ExplorationProductivity GainsArchitecture / Goal FlexibilityLimitations of Behavioral SynthesisBehavioral Design vs. System Design

2.2 The RTL Design Process

Developing the AlgorithmExploring Alternate Architectures

2.3 The Behavioral Design Process

A Simple AlgorithmData Dependencies

RTL Synthesis Implementation

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Resource Allocation

SchedulingControl Logic / State MachineMemoryData Path Elements

Gantt ChartsChained OperationsMulti-cycle Operations

2.4 Summary

3. The Behavioral Synthesis Process

Understanding Behavioral Synthesis

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Chapter 3 discusses the steps performed during behavioral synthesis. Whilethis chapter discusses some topics that are not essential to using behavioralsynthesis tools, a good understanding of these steps will provide insight intothe results produced by behavioral synthesis.

3.1 The Behavioral Synthesis Process

3.2 Internal Representations

3.3 Resource Allocation

3.4 Scheduling

Scheduling ConceptsASAP / ALAP SchedulingOther Scheduling Methods

3.5 Register Allocation

Lifetime AnalysisRegister Sharing

3.6 Binding

3.7 Data Path and State Machine Extraction

3.8 Netlisting

Scheduled DesignFinal Design

3.9 Summary

4. Data Types

Chapter 4 discusses the data types that are supported by behavioralsynthesis and how those data types are translated into a gate-level netlist.The job of any synthesis tool is to ultimately translate all data types to thosedata types that can represent wires.

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Table of Contents

4.1 Synthesis Considerations

4.2 bit I biCvector Types

4.3 boolean Type

4.4 std_loglc I std_loglc_vector I signed I unsigned Types

4.5 Integer Type

4.6 Enumerated Type

4.7 Record Type

4.8 Array Type

4.9 Types Not Supported for Synthesis

4.10 Summary

5. Entities, Architectures, and Processes

Chapter 5 discusses the fundamental building blocks of a VHDL description.Designers writing RTL code utilize these building blocks differently thandesigners writing behavioral code.

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5.1 The Entity Declaration 57

Ports With Abstract Types 58Wrapper Models 60

5.2 The Architecture Specification 64

5.3 Processes 65

Specifying Clock Edges 69Timing Diagrams 70Scheduling Assumptions 73

5.4 Summary 76

6. Loops

Chapter 6 discusses the role of loops in behavioral descriptions. Unlike RTLsynthesis tools, behavioral synthesis tools support FOR loops with bothconstant and non-constant bounds, WHILE,- loops, and infinite loops.Behavioral synthesis methodologies encourage the use of loops to allowdesigners to describe algorithms at a higher level of abstraction.

6.1 Loops In RTL Design

6.2 Loop Constructs and State Machines

6.3 The EXIT Statement

Specifying a Synchronous Reset

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vIII Understanding Behavioral Synthesis

Simulating the Reset ConditionComplex Reset SequencesUsing an Attribute to Specify a Reset SignalSpecifying an Asynchronous Reset

6.4 Types of Loops

Infinite LoopsWHILE LoopsFOR Loops

6.5 The NEXT Statement

6.6 Scheduling Loops

Clock Cycles and Control StepsMinimum Execution Time

6.7 Loop Unrolling

Complete UnrollingPartial UnrollingWhen to Unroll

6.8 Summary

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7.1/0 Scheduling Modes

Chapter 7 explains I/O scheduling mode terminology, as defined forbehavioral synthesis. I/O modes allow the user to determine the relationshipbetween the timing of the behavioral description and the synthesized design.

7.1 Overview of Scheduling Modes

7.2 Cycle-Fixed SchedUling Mode

Scheduling a Simple DesignTesting Designs Scheduled in Fixed I/O ModeScheduling Conditional Branches in Fixed I/O ModeScheduling Loops in Fixed I/O ModeAdvantages and Disadvantages of Fixed I/O Mode

7.3 Superstate-Fixed SchedUling Mode

Scheduling a Simple DesignTesting Designs Scheduled in Superstate I/O ModeScheduling Conditional Branches in Superstate I/O ModeScheduling Loops in Superstate I/O ModeAdvantages and Disadvantages of Superstate I/O Mode

7.4 Free-Floating Scheduling Mode

Scheduling a Simple Design

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Testing Designs Scheduled in Free 1/0 ModeAdvantages and Disadvantages of Free 1/0 Mode

7.5 Summary

8. Pipelining

Chapter 8 explains how pipelining can be used to increase the throughput ofa design. Pipelining increases the throughput of a design usually at the costof area, but this is not always necessary if the design is thoroughly analyzed.The use of pipelined components and the pipelining of loops are considered.

8.1 Types of Pipelining

8.2 Pipelined Components

Design BenefitsDesign Flow Benefits

8.3 Loop Pipelining

Scheduling a Pipelined LoopLatency and Initialization IntervalNEXT and EXIT Statements in a Pipelined LoopDependencies in a Pipelined LoopSimulating a Pipelined LoopRestrictions on Pipelined Loops

8.4 Summary

9. Memories

Chapter 9 discusses how arrays can be mapped to memory. Multi­dimensional arrays can be used in behavioral descriptions to manipulategroups of data in a direct, easy-to-understand manner. Arrays can bemapped to a variety of types of memories. This allows the designer to makeintelligent decisions about an appropriate memory to include in a design.

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9.1 Memories in RTL Design 155

9.2 Mapping Arrays to Memory 155

Mapping Indices to Addresses 156Synchronous Memory 160Asynchronous Memory 163Memory Ports 166Data Dependencies 167

9.3 Summary 172

x Understanding Behavioral Synthesis

10. Functions, Procedures, and Packages

Chapter 10 discusses the role of functions, procedures, and packages inbehavioral design. When placed in a package, functions and procedurespromote reuse, as subprograms in packages can be used in multipledesigns. Functions can also be used to simulate the behavior of complexblocks that will be mapped to pre-constructed components during synthesis.

10.1 Subprograms 173

10.2 Functions 174

Mapping to an Operator 174Preserving a Function 176

10.3 Procedures In

10.4 Packages 178

10.5 Summary 180

11. Handshaking

Chapter 11 discusses pre- and post-scheduling simulation issues. A designthat has been validated at the behavioral level must also be validated afterscheduling. The correlation between I/O read and write operations inbehavioral designs and scheduled designs is discussed. A simplehandshaking protocol is introduced.

11.1 Communication With External Models

Scheduling AssumptionsSynchronizing Communication With Fixed I/O

11.2 Handshaking

Full vs. Partial HandshakingInput HandshakingOutput HandshakingScheduling Issues

11.3 Interprocess Communication

11.4 Summary

12. Reusable Test Benches

Chapter 12 discusses how to design a test bench that can be used with abehavioral design, a scheduled RTL design, as well as the resultingoptimized gate-level design. The test bench uses the handshaking principalsintroduced in Chapter 11.

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12.1 Objectives 197

12.2 VOTiming 198

12.3 Interface Type Considerations 199

12.4 Test Bench Structure 202

The ENTITY Declaration 202Instantiating the Design 203Clock Generation 204Reset Generation 204Input and Output Processes 205

12.5 Messages 210

Assertion Statements 210Text I/O 210

12.6 Summary 211

13. Coding For Behavioral Synthesis

Chapter 13 incorporates the discussion of the previous chapters into codingstyles for Behavioral Synthesis. While not defining a set of "hard-and-fast"rules, this chapter does develop a set of gUidelines would should allow adesigner to successfully evaluate a particular piece of behavioral code andunderstand how it will be processed by a behavioral synthesis tool.

13.1 Overview 213

13.2 Entities, Architectures, and Processes 214

Specifying Clock Edges 215Resets 216

13.3 Data Types 218

bit / biCvector Types 219boolean Type 219std_logic / std_logic_vector / signed / unsigned Types 219Integer Type 223Enumerated Type 224Record Type 224Array Type 224Types Not Supported for Synthesis 225

13.4 Coding Style and I/O Scheduling Mode 225

13.5 Fixed I/O Scheduling Mode 225

Conditional Statements 227Loops 232

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13.6 Superstate VO Scheduling Mode

Conditional StatementsLoops

13.7 Free Scheduling Mode

13.8 Summary

14. Case Study: JPEG Compression

Understanding Behavioral Synthesis

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Chapter 14 discusses the implementation of a JPEG compression algorithm.The JPEG algorithm represents a compression standard developed forgrayscale and color continuous-tone still images. At the heart of the JPEGalgorithm is a discrete cosine transform (OCT) which is common in video andaudio processing algorithms. This chapter discusses the details of thealgorithm itself and the synthesis issues that should be considered in orderto produce quality results.

14.1 Introduction 245

14.2 The Algorithm 245

Algorithm Overview 246Processing an Entire Image 247The Discrete Cosine Transform 247Quantization 249Zigzag Sequence 250Run-Length / Entropy Encoding 251

14.3 The Environment 252

14.4 Compression Results 254

14.5 Behavioral Description 254

Memories 254Handshaking 255Matrix Multiplication 255

14.6 Behavioral Synthesis 255

Bounding the Design Space 256Exploring Other Architectures 260

14.7 Summary 262

Table of Contents

15. Case Study: FIR Filter

Chapter 15 discusses the design and implementation of a Finite ImpulseResponse (FIR) digital filter. Digital filtering is an important aspect of mostDSP-oriented designs. This filter can be easily described using a behavioralcoding style and the results of behavioral synthesis are easily understood.Various implementations are considered, including two pipelinedarchitectures.

15.1 Introduction

15.2 The Algorithm

15.3 Behavioral Description

Tap CoefficientsFiltering

15.4 The Environment

15.5 Behavioral Synthesis

Bounding the Design SpacePipelining the Design

15.6 Summary

16. Case Study: Viterbi Decoding

Chapter 16 discusses the implementation of a Viterbi decoding algorithm.The Viterbi decoding algorithm is used to decode convolution codes and isfound in almost every system that receives digital data which might containerrors. This chapter discusses the details of the algorithm itself and thesynthesis issues that should be considered in order to produce qualityresults.

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16.1 Introduction 273

16.2 The Algorithm 273

Convolution Codes 274Trellis Diagram 275Viterbi Decoder 276

16.3 Behavioral Description 278

16.4 The Environment 279

16.5 Decoding Results 280

16.6 Behavioral Synthesis 281

Bounding the Design Space 281Pipelining the Design 283

16.7 Summary 284

xiv Understanding Behavioral Synthesis

Appendix A: JPEG Source Code 285

Appendix B: FIR Filter Source Code 293

Appendix C: Viterbi Source Code 297

Glossary 301

References and Resources 309

CD-ROM 311

CD-ROM Contents 311

CD-ROM License Agreement 312

Index 313

Preface

Today's designs are creating tremendous pressures for digital designers. Not only mustthey compress more functionality onto a single Ie, but this has to be done on shorterschedules to stay ahead in extremely competitive markets. To meet these opposingdemands, designers must work at a new, higher level of abstraction to efficiently makethe kind of architectural decisions that are critical to the success of today's complexdesigns. In other words, they must include behavioral design in their flow.

For any design, there are a multitude of possible hardware architectures the design teamcould use to achieve their goals. Finding a suitable architecture demands adisproportionate amount of time from even the most experienced designer. When usingonly logic synthesis tools, an RTL description of that architecture must be created in ahardware description language (HDL) with thousands of lines of handcrafted code. Thedesigner must specify all the details in the code, including the logic states and thecorresponding operations performed during those states. Unfortunately, defining anarchitecture and creating RTL code consume so much time, the designer cannot afford tomake any architectural changes, forcing the designer to adopt one architecture and hopefor the best.

To raise architectural design above these time-consuming details of the RTL level,behavioral design tools were introduced a few years ago. These tools allow the designerto describe system functionality much more efficiently at the behavioral level, usingdescriptions typically 5-10 times smaller than an RTL description.

A behavioral description defines the algorithm to be performed with few or noimplementation details. Designers direct behavioral synthesis tools to generate alternatearchitectures by modifying constraints (such as clock period, number and type of datapath elements, and desired number of clock cycles). Behavioral synthesis tools take abehavioral description and automatically schedule the operations into clock cycles. Thetools automatically create the state machine that is implied when the calculation of analgorithm takes multiple clock cycles. The final output is RTL code which describes thedata path elements, the finite state machine, and the memory or registers. This RTLcode is ready for logic synthesis.

The biggest challenge to adopting behavioral design is changing the mindset of thedesigner. Instead of describing system functionality in great detail, the designer outlinesthe design in broader, more abstract terms. The ability to easily and efficiently considermultiple design alternatives over a wide range of cost and performance is an extremelypersuasive reason to make this leap to a higher level of abstraction. Designers that learnto think and work at the behavioral level will reap major benefits in the resultant quality ofthe final design.

But such changes in methodology are difficult to achieve rapidly. Education is essentialto making this transition. Many designers will recall the difficulty transitioning fromschematic-based design to RTL design. Designers that were new to the technology often

xvi Understanding Behavioral Synthesis

felt that they had not been told enough about how synthesis worked and that they werenot taught how to effectively write HDL code that would synthesize efficiently.

This book attempts to address these issues for behavioral synthesis. The intendedaudience is the designer who will be using (or is considering using) behavioral synthesis,the manager (or others) who will be working with those designers, or the engineeringstudent who is studying leading-edge design techniques.

This book is not a theoretical treatise on behavioral synthesis technology nor is it areference manual for a particular tool. Using this book, a designer will understand whatbehavioral synthesis tools are doing (and why) and how to effectively describe theirdesigns so that they are appropriately synthesized.

The book was developed based on the capabilities and features of behavioral synthesistools that are available today. Certain limitations or inefficiencies that are described inthis book willli~<ely go away as such tools evolve.

Although behavioral descriptions can be written in both VHDL and Verilog®, this bookfocuses entirely on using VHDL for creating behavioral descriptions. Books that attemptto simultaneously address design issues for both VHDL and Verilog® rarely do service toeither language. It seemed best that each language should be discussed separately.VHDL was selected first.

The book assumes a working knowledge of the VHDL language and of RTL synthesisconcepts. Books that can provide background knowledge on these topics are listed inthe References and Resources section of this book.

With the benefits of today's behavioral synthesis tools, behavioral design will become amainstay of IC design in the near future. New interactive behavioral synthesis tools thatare capable of quickly processing even the largest designs will make this possible. Sincethese tools are easily integrated into existing flows, they are particularly attractive todesigners under pressure to create viable designs on tight schedules. Behavioral designwill soon become a widespread practice throughout the design community.

Acknowledgements

This is the second printing of this book. This reprint was edited by Andrew Guyler. Anumber of paragraphs in chapters 6 and 9 have been reworded for clarity andconsistency. The book has been reviewed by the Monet Engineering team to check thedescriptions and examples for consistency with the Monet Behavioral Synthesis product.In addition various typographical errors have been corrected, throughout the book,including correction of figure numbers in Chapter 6.

Many people were involved in the creation both the first and second prints. We would liketo acknowledge the efforts of those individuals who helped in this creation.

First, we would like to thank John's wife, Deborah Layne, who carefully read the firstdrafts of the material and helped identify the conceptual "leaps" that needed furtherexplanation.

Thanks to Aaik van der Poel for providing the material for Chapter 1, and to Rick Nixonfor providing the opportunity for John to spend time on the first print of the book.

We would also like to extend thanks to other present and past members of the Monetteam who took time to review the contents of the book. In particular we would like tomention Michael Bohm, David Burnette, Peter Gutberlet, Kenneth Larsen, Lev Markov,Shiv Prakash, Todd Selden, Ken Steele, Andres Takach, and Mark Wallace.

A special thanks needs to go to David Burnette, who created an introductory workshopon behavioral synthesis. This workshop created a structured approach to the introductionof behavioral synthesis concepts and examples to illustrate concepts in behavioralsynthesis which have been used in this book.

David can be contacted at david_burnete@mentor.com

Finally, our thanks to Carl Harris of Kluwer Academic Press for his encouragement andsupport.

About the Editor

Andrew Guyler is currently the Engineering Manager for the Monet Behavioral Synthesisproject. Andrew joined Mentor Graphics in 1993. There he has managed a number ofsoftware engineering groups inclUding VHDL Simulation, Design For Test, Floorplanning,Synthesis Interfaces, and High-Level Synthesis. He was a member of the VHDL 1993Language Design Team, and has continued involvement with standards activities.Andrew's career in EDA began In 1983 when he joined Cirrus Computers Limited (later tobe acqUired by GenRad) where he worked on the Hilo and HiTest tool suites.

He holds a B. S. in Mathematics from the University of Nottingham.

Andrew can be contacted at andrew_guyler@mentor.com

xviii Understanding Behavioral Synthesis

About the Author

John Ellio" began his career in EDA in 1988 at Trimeter Technology Incorporated, one ofthe first synthesis-related start-up companies, which was purchased by Mentor Graphicsin 1989. After working at Mentor in various development, marketing, and applicationpositions both here and in Europe, he worked in the Consulting organization at Synopsys,Inc. and returned to Mentor Graphics in 1996. Since returning to Mentor Graphics, hehas worked on teams focused on FPGA design flows, internet technology, and behavioralsynthesis. John left Mentor Graphics in 1999.

He holds a B. S. in Electrical Engineering and a B. A. in Philosophy from the University ofPi"sburgh, where he was a Chancellor Scholar.