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UH30OSD

TARGET SPECIFICATION

OCTAL INTELLIGENT SQUIB DRIVER

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20-May-03Rev. 1.1

This copyrighted document is property of STMicroelectronics and isdisclosed in confidence. It may not be copied, disclosed to others or used

for manufacturing without the prior written consent of STMicroelectronics

EIGHTSQUIBDEPLOYMENTDRIVERS(1.2A/2msAND1.75A/4ms);DEPLOYMENTCURRENTANDTIMEPROGRAMMABLE VIASPI

CAPABILITYTODEPLOYWITH1.47A(2.14A)UNDER40V(21V)LOAD-DUMPCONDITIONANDTHELOWSIDEFETSHORTEDTO1V.

5.5MHZ SPIINTERFACEWITHMESSAGEVALIDATION 4CHANNELSOFDISCRETE/SERIALLOGICARMING

INTERFACEPROGRAMMABLEVIASPI

DEPLOYMENTDRIVERSELF-DIAGNOSTICS:- SHORTTOBATTERY/GROUND ANDOPENCIRCUIT- SQUIBRESISTANCEMEASUREMENT- SHORTBETWEENCHANNELSDETECTIONS- HIGHANDLOWSIDEFETTESTS- GROUNDLOSSDETECTION

-40CTO+85COPERATINGAMBIENTTEMPERATURE 4KVESDCAPABILITYONALLOUTPUT-DRIVERPINSAND

2KVONALLOTHERS

DESCRIPTION

The UH30OSD is an Octal Intelligent Squib DriverASIC in 44pin Thin Quad Flat Pack (TQFP) packagedesigned using ST proprietary BCD4 technology. It isdesigned to deploy airbag squibs and providediagnostics for each of the deployment drivers. Each ofthe eight drivers is sized to deliver 1.2A or 1.75A min for2ms or 4ms. The deployment current and time areprogrammable via SPI.

The device has full diagnostic capability via SPI on the

deployment drivers. It provides short to battery andground protection, open circuit protection, individualsquib resistance measurement, capability to detectshorts between channels, tests for high and low sideFETs and ground loss detection.

The device has individual control pins for each of thedrivers, including a separate ground pin. It also featuresarming inputs that act as a fail-safe mechanism toprevent inadvertent deployment.

MULTIPOWER BCD4 TECHNOLOGY

SHx

ISENSE

GND0

H S D

L S D

SLx

GNDx

x = 0 to 7 (8 modu les)

DIAGNOSTICS

RESET

S P I

MISO

MOSI

SCLK

CS

TEST/DEN

VDDVRM

IREF

For x = 1 to 7

ISENSE

BLOCK DIAGRAM

FSxx

VRx

FSxx / FSyy

TQFP44 10 x 10mm

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This copyrighted document is property of STMicroelectronics and isdisclosed in confidence. It may not be copied, disclosed to others or usedfor manufacturing without the prior written consent of STMicroelectronics

ValueSymbol Parameter

min maxUnit

VDD Supply Voltage -0.3 +6.5 V

VIN Discrete Input Voltage -0.3 +6.5 V

VRM Supply Voltage for Resistance Measurement -0.3 +40 V

VRx Reserve Voltage for Loop Channels (x = 0 to 7) -0.3 +40 V

SHx, SLx Squib High Side and Low Side Drivers output (x = 0 to 7) -1 +40 V

Tj Junction Temperature +150 C

Tstg Storage Temperature -40 +150 C

SQH0 1

SQL0 2

GND0 3

ARMCLK/ARM45 4

ARMOUT/ARM67 5

ARMEN/ARM23 6

ARMIN/ARM01 7

TEST/DEPEN 8

GND7 9

SQL7 10

SQH7 11

33 SHLH3

32 SQL3

31 GND3

30 SCLK

29 MOSI

28 MISO

27 VDD

26 IREF

25 GND4

24 SQL4

23 SQH4

44VRES0

43VRES1

42SQH1

41SQL1

40GND1

39VRMEAS

38

GND2

37

SQL2

36SQH2

35VRES2

34VRES3

12VRES7

13VRES6

14SQH6

15SQL6

16GND6

17CS

18GND5

19SQL5

20SQH5

21VRES5

22VRES4

PIN CONNECTIONS(top view)

ABSOLUTE MAXIMUM RATINGS

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Pin Nbr Pin Name Descript ion I/O type

1 SH0 High Side Driver Output for Channel 0 Output








2 SL0 Low Side Driver Output for Channel 0 Output








44 VR0 Reserve Voltage for Loop Channel 0 Input




22 VR4 Reserve Voltage for Loop Channel 4 Input21 VR5 Reserve Voltage for Loop Channel 5 Input



FSIN Fail Safe Serial Mode Data Input Input7

FS01 Fail Safe Input Signal for Channels 0 and 1 Input

FSEN Fail Safe Serial Mode Data Enable Input6


FSCLK Fail Safe Serial Mode Clock Input Input

4 FS45 Fail Safe Input Signal for Channels 4 and 5 Input

FSOUT Fail Safe Serial Mode Data Output Output5


3 GND0 Power Ground 0 -



DEVICE PIN OUT

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Device Pin Out (continued)

Pin Nbr Pin Name Descript ion I/O type






TEST Test Input Pin Input8

DPEN Deployment Enable Input

17 CS SPI Chip Select Input

30 SCLK SPI Clock Input

29 MOSI SPI Data In Input

28 MISO SPI Data Out Output

26 IREF External Current Reference Resistor Output

27 VDD VDD Supply Voltage Input

39 VRM Supply Voltage for Resistance Measurement Input

DC ELECTRICAL CHARACTERISTICS(-40C < Tj < 95C, 4.9V < VDD< 5.1V, 6.5V < VRES< 40V,7.0V < VRMEAS< 26.5V unless otherwise specified)

General IC Parameters

Symbol Parameter Test Condi tion Min. Typ. Max. Unit

VRSTVDDInternal Reset

voltageLower VDDVoltage untildeployment drivers are disabled

4.2 4.7 V

IDD VDDSupply current Normal or shorted SQL or SQH(Shorted to -1V)

5 mA

IDD VDDSupply current Deployment TBD mA

VIH Input threshold voltageMOSI, SCLK, CS, ARMx, DEPEN Input Logic 1 2.0 V

VIL Input threshold voltageMOSI, SCLK, CS, ARMx, DEPEN Input Logic 0 0.8 V

ILKGInput leakage current

MOSI, SCLKVIN= VDD 1 A

ILKGInput leakage current

MOSI, SCLK0V < VIN< VIH -1 A

VTEST HTEST Input threshold

VoltageLogic 1 TBD V

VTEST L TEST Input thresholdVoltage Logic 0 TBD V

IPDInput pull down currentARMx, CS, DEPEN

VIL< VIN< VDD 10 50 A

VOHOutput high Voltage

MISOIOH< 800A (out of the part)

VDD-0.8

V

VOL Output Low Voltage IOL < 1.6mA (into the part) 0.4 V

Iz Tristate Current MISO 0V < MISO < VDD -10 10 A

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Deployment Drivers DC Parameters


ISQH_LKG SQH Leakage currentVRMEAS=VDD=VSQH=0V,VRESx=36V

50 A

ISQH_STG SQH Leakage current VRMEAS=18V, VDD=5V,VSQH= -1V

-5 MA

ISQL_LKG SQL Leakage currentVRMEAS=VDD= 0V, VSQL=18V(not during diagnostic)

-10 10 A

ISQL_STG SQL Leakage currentVRMEAS=18V, VDD=5V,VSQL= -1V

-5 A

ISQL_STB SQL Leakage currentVRMEAS=18V, VDD=5V,VSQL= 18V

5 A

IPD SQL Pulldown current VSQLx = 1.8V - VDD 500 700 A

IRES VRESx Bias currentVRMEAS=18V, VDD=5V,SQH shorted toSQL, VRESx=36V

10 A

VSGth Short to GND threshold VDD=5.0V 1.9 2.1 V

VSBth Short to B+ threshold VDD=5.0V 3.9 4.1 V

VOCth Open Circuit threshold VDD=5.0V 1.9 2.1 V

VLDth FET Test load detect 100 300 MV

ID_SRCResistance meas.

current sourceVDD=5V, 7.0V

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Deployment Drivers AC Characteristics


tPOR POR De-glitch timer 5 20 s

tONFET turn on time

ARMx & DEPEN pins asserted.time from CS falling edge to 90%of IFINAL.

150 s

tSETTLEFET settling time

ARMx & DEPEN pins asserted.time from CS falling edge to 90%to 110% of IFINAL.

300 s

tPULSE Pulse Stretch Timer See table 0 60 ms

tP_ACC Puse Stretch TimerAccuracy

-20 20 %

tGLITCH Pulse Stretch De-glitchtimer

5 25 s

tDEPLOY Deployment time6.9V

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SPI Port AC characteristics


fOP Operating Frequency DC 5.5 MHztSCK SCLK period 181 ns

tLEAD Enable Lead Time 62 ns

tLAG Enable Lag Time 50 ns

tSLCKHS SCLK High Time 65 ns

tSLCKLS SCLK low Time 65 ns

tSUS MOSI Input Set-up time 20 ns

tHS MOSI Input Hold time 20 ns

tA MISO Access time 66 ns

tDIS MISO disable time Measured with minimalcapacitance (see fig. Xxx) 100 ns

tVS MISO Output valid time 45 ns

tHO MISO Output Hold timeMeasured with minimalcapacitance

0 ns

tRO Rise time Design information only 30 ns

tFO Fall time Design information only 30 ns

tCSN CN Negated time 100 ns

SPI Timing diagram

MISO Disable Time Measurement loading

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Arming Serial Mode AC character istics

Symbol Parameter Test Condit ion Min. Typ. Max. UnitfOP Operating Frequency DC 2.0 MHz

tARMCLK ARMCLK Period 500 ns

tLEAD Enable Lead Time 250 ns

tLAG Enable Lag Time 100 ns

tARMCLK_HS ARMCLK high time 220 ns

tARMCLK_LS ARMCLK low time 220 ns

tSUS ARMIN Input Set-up time 30 ns

tHS ARMIN Input Hold time 10 ns

tA ARMOUT Access time 125 nstVS ARMOUT Output valid time 190 ns

tHO ARMOUT Output Hold time 10 ns

tRO Rise time Design information only 30 ns

tFO Fall time Design information only 30 ns

tARMEN_N ARMEN Negated time 200 ns

Arming Serial Mode timing diagram

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Package Outline

uh30

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