UC San Diego / VLSI CAD Laboratory Learning-Based Approximation of Interconnect Delay and Slew...

UC San Diego / VLSI CAD Laboratory

Learning-Based Approximation of Interconnect Delay and Slew Modeling in Signoff Timing Tools

Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath and Jyoti WadhwaniVLSI CAD LABORATORY, UC San Diego

15th ACM/IEEE System-Level Interconnect Prediction Workshop

June 2nd, 2013

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Outline Motivation Learning-based Interconnect Modeling Correlation Methodology with Signoff Timer Experimental Results Conclusions and Future Works

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Motivation Incremental static timing analysis (iSTA) is the backbone of

post-layout design optimization– Using Signoff Timer – Using Internal Timer

Gate Sizing/Vt-Swapping

Post-Layout

Signoff

Post-Layout Optimizer

Iterative invocation Runtime increase

TimingDiscrepancy

iSTA

Internal Timer

iSTA

Signoff Timer

Runtime increase Less accuracy

An accurate internal timer is needed

STA

Signoff Timer

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Motivation Challenges in matching signoff timer

– Error propagation along paths– Error accumulation with netlist changes

Error propagation on paths

Error(internal timer – signoff timer)

Error # logic depth along path

# cell change

Netlist change

Error accumulationwith netlist change

Our goal: minimize the error

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Our Work We minimize divergence ‘d’ between internal and

signoff timers Two basic techniques

– Learning-based modeling of wire delay and slew– Offset-based timing correlation

We achieve small divergence ‘d’

runtime

accu

racy Signoff

Timerd

Internal Timer

d

Learning-based modeling

Offset-based timing correlation

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Preliminary: Delay and Slew Delay : 50% of input transition to 50% of output transition Slew : 10% to 90% of transition Gate delay and slew: little divergence between timers

– Lookup table-based method is used not in our scope Wire delay and slew: challenging to match signoff timer

– Wire delay and slew models in signoff timer are unknown

DelaySlew50%

10% 90%

-8-

Error Distribution of Analytical Models Existing analytical models

Elmore (EM)

[Elmore98]

D2M [Alpert00

]

PERI [Kashyap02

]

Lognormal Slew (LnS) [Alpert03]

Wire slew80%

80%

80%

80%

Regression

EM/LnS: overestimateD2M/PERI: underestimate

Classification

Hard cases cannot be estimated by any

single model

Hard cases Hard cases

Hard cases Hard cases

Wire delay

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Why Classification? Data points in each class have stronger linear fit

between measured and estimated values after classification

Estimated values

Mea

sure

d va

lues

Estimated values Estimated values Estimated values

Mea

sure

d va

lues

Mea

sure

d va

lues

Mea

sure

d va

lues

𝐂𝐥𝐚𝐬𝐬𝟏 :𝜶≤𝜶𝟎 Class 2: 𝐂𝐥𝐚𝐬𝐬𝟑 :𝜶≤𝜶𝟐

𝜶 :𝑪𝒍𝒂𝒔𝒔𝒊𝒇𝒊𝒆𝒓

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Classification Our “alpha” is chosen empirically Alpha reflects degree of significance of ramp

input on delay metric [Kashyap02]

𝜶=( 𝟐𝒎𝟐−𝒎𝟏𝟐

𝟐𝒎𝟐−𝒎𝟏𝟐+

𝑻 𝟐

𝟏𝟐 )𝟓 /𝟐

Model 1 Model 2Model 1

Model 2 Model 3

Wire slewWire delay

: wire input slewm1 : first moment m2 : second moment

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Learning-based Interconnect Modeling Our methodology

– Classification + Least-Squares Regression (LSQR)

Collect training data

LSQR

Classification

𝜶<𝜶𝟏

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Learning-based Interconnect Modeling Exhaustive search for the best regressor(s) and

classifier(s)– Increasing the number of regressors/classifiers

improves the accuracy until a certain point

The number of regressors

The

num

ber o

f cla

ssifi

ers

0

1

2

1 2 3

20ps

23ps 21ps

15% -8%-30%

16ps14ps-12%

-33%

14ps

0%

Maximum absolute wire delay error

The number of regressors

The

num

ber o

f cla

ssifi

ers

0

1

2

1 2 3

73ps

46.8ps

46.5ps-36% -0.0%

-23%

36ps 33ps-8%

-29%

31.5ps

-4.5%-11%

32ps-1.5%

Maximum absolute wire slew error

Experimental results with all testcases (ISPD-2013)

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Learning-based Interconnect Modeling Learning-based models for wire delay and slew

𝑊𝐷𝑀𝐿=𝑎1 ∙𝛼 ∙𝐸𝑀+𝑎2 ∙𝛼 ∙𝐷2𝑀+𝑎3 ∙𝐸𝑀𝑊𝑆𝑀𝐿=√𝑏1 ∙𝐸𝑀2+𝑏2 ∙𝐿𝑁𝑆

2+𝑇2

, , : regression coefficients for wire delay model, : regression coefficients for wire slew model: wire input slew; degree of significance of ramp input

: delay metrics for wire; LNS: slew metric for wire

Wire delay modeling

Class 1: -1.72 2.35 0.96Class 2: -1.05 1.27 1.02Class 3: -2.72 1.41 2.50

Wire slew modeling

Class 1: -3.44

2.07

Class 2: -2.39

1.59

Class 3: -1.88

1.30

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Static Timing Analysis Timing slack is calculated by STA

Endpoint (primary output, input of FF) timing slack errors are reported for evaluation

Calculate slew

Calculate delay

Calculate AAT/RAT

Calculate slack

3 4

56

11 1215/15

/12/11/6

/5

/6/5/2

/0/0 /0 /0

/0

/2AAT/ RAT / slack = RAT - AAT

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Correlation with Signoff Timer Use timing information from signoff timer to

compensate the difference (error) between internal and signoff timer

Previous work: [Moon10] Endpoint slack offset-based correlation– Can match slack in critical paths– May not be accurate when critical paths change

iSTA

Signoff Timer

iSTA

Internal Timer

Request timing information

offset = signoff timer – internal timer

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Correlation with Signoff Timer Offset is calculated at each STA stage

Correlated timing (slew/delay/AAT/RAT/slack) = timing values from internal timer + offset

Calculate slew

Calculate delay

Calculate AAT/RAT

Calculate slack

Slew Delay AAT/RAT Slack

offset = signoff timer – internal timer

Slew offset

Delayoffset

AAT/RAToffset

Slack offset

Signoff timer

Internal timer

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Correlation Method vs. Quality Maximum absolute endpoint slack error for each

correlation method AAT/delay/AAT+slew/delay+slew correlations give 10X more

accuracy during netlist changes compared to slack correlation [Moon10]

(ps)

0.0%

2.5%

5.0%

7.5%

10.0%

12.5%

15.0%

17.5%

20.0%

22.5%

25.0%

27.5%

30.0%

020406080

100120140160180 SLK AAT DELAY AAT_TRAN DLY_TRAN

% of changed cells

Experimental results with fft testcase (ISPD-2013)

0.0%

2.5%

5.0%

7.5%

10.0%

12.5%

15.0%

17.5%

20.0%

22.5%

25.0%

27.5%

30.0%

0

2

4

6

8

10

12

14

% of changed cells

AAT, delay, AAT+slew, delay+slew correlation

slack correlation

10X

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Timer in Post-Layout Optimizer Internal timer for a post-layout optimizer

Correlate()

Netlist change

iSTA()

# cell change > N?

Offset

yes

no

invoke signoff timer

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Experimental Environment Technology : Liberty from ISPD-2013 Gate Sizing Contest Testcases : ISPD-2013 testcases

Signoff tool : PrimeTime© F-2011.06-SP3-7

Benchmark #cells #nets #PI #FFs #pins #POpci_bridge32 30603 30763 160 3359 87813 201

fft 32766 33792 1026 198410535

5 1984matrix_mult

156440

159642 3202 2898

459946 1600

edit_dist12666

512922

7 2562 566137460

6 12

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Error between Internal and Signoff Timer Maximum absolute endpoint slack error for all (delay, slew)

pairs Correlation-based approach can improve accuracy (delay: D2M, slew: ML) shows the best result

without correlation

(ps)

0.0%

2.5%

5.0%

7.5%

10.0%

12.5%

15.0%

17.5%

20.0%

22.5%

25.0%

27.5%

30.0%

0

50

100

150

200

250

300

(EM,PERI) (D2M, PERI) (D2M, ML) (ML, S2M) (ML, PERI) (ML, ML)

% of changed cells

0

50

100

150

200

250

300

0.0% 5.0% 10.0% 15.0% 20.0% 25.0% 30.0%% of changed cells

with correlation

Testcase: fft (ISPD-2013)

with correlation(ps)

0.0%

2.5%

5.0%

7.5%

10.0%

12.5%

15.0%

17.5%

20.0%

22.5%

25.0%

27.5%

30.0%

0

5

10

15

20

25

30

% of changed cells

(delay: D2M, slew: ML) 10X

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Conclusions and Future Works Learning-based methodology can improve accuracy for

endpoint timing slack estimation AAT/delay/AAT+slew/delay+slew offset-based

correlation methods can achieve 10X accuracy improvement for timing slack estimation

Future works– Enhance model robustness across different libraries

and testcases– Minimize the overhead of correlation methodology

with a given accuracy– Application: industry-strength gate sizing optimizers

Thank You!

UC San Diego / VLSI CAD Laboratory Learning-Based Approximation of Interconnect Delay and Slew...

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