uC-04-68K Signal REV - MWFTR - Learning Environment · 2012. 5. 7. · Microsoft PowerPoint -...
Transcript of uC-04-68K Signal REV - MWFTR - Learning Environment · 2012. 5. 7. · Microsoft PowerPoint -...
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EECE416 Microcomputer Fundamentals
68000 Processor1. Chip Signal Description
2. Instruction and Programming
Dr. Charles Kim
Howard University
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68000 Microprocessor
64 pins32- bit Data and Address Registers16- bit Data Bus24- bit Address Bus (16MB)14 Addressing ModesMemory- Mapped Input/ OutputProgram Counter(PC)5 Main Data Types- L, W, B, b, BCD7 interrupt levelsClock speeds: 4MHz to 12.5MHzSynchronous and asynchronous data transfers
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PIN and PACKAGE
DIP
PLCC
PLCC Socket
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BLOCK Diagram
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Core Structure
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Internal Structure - Registers
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Connecting with Peripherals
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68000 Single Board Computer (SBC)
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68000 Single Board Computer- block diagram
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SIGNAL DESCIRPTION1. ADDRESS BUS (A23–A1)
23-bit, unidirectional, three-state bus capable of addressing 16 Mbytes of data.
2. DATA BUS (D15–D0)bidirectional, three-state busgeneral-purpose data path of 16 bits widetransfer data of either word or byte length.
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Signal Description3. ASYNCHRONOUS BUS CONTROL
Address Strobe (~AS).⌧This three-state signal
indicates that the information on the address bus is a valid address.
Read/Write (R/~W).⌧This three-state signal defines
the data bus transfer as a read or write cycle.
Upper And Lower Data Strobes (~UDS, ~LDS).Data Transfer Acknowledge (~DTACK).⌧This input signal indicates
the completion of the data transfer.
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Memory DecodingMemory Bus
ControlData (Bi-directional)Address (Unidirectional)
Address Bus BufferingFan Out74LS244 Octal line driver/receiver
Data Bus BufferingR/W for DirectionFan Out74LS245 Octal Bus Transceiver
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Memory AccessingREAD AND WRITE CYCLE
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Memory Address DecodingHow Much Memory?How Many Address Lines?1K 10 lines32K 15 lines
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Memory DecodingQ: 64K Word (or 128 KB) of RAM, with it’s starting address at $480000A: 128KB 17 lines
Range: $480000 - $49FFFFUDS and LDS for A0 line.
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Memory Decoding ExampleQ: 16K Word EEPROM with starting address at $300000.A: 32KB 15lines
$300000 - $307FFF
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Memory Decoding - multibankQ: 256KB RAM composed of eight 32KB RAMsAddress Range:
00000 – 07FFF08000 – 0FFFF10000 – 17FFF18000 – 1FFFF20000 – 27FFF28000 – 2FFFF30000 – 37FFF38000 – 3FFFF
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SIMM (single in-line memory module)Circuit of RAM
4MB Memory at the base address of 800000 using 1MB SIMMs
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Memory Map for ROM and RAM
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Memory Decoding with Byte/Word Access
Size of ROMSize of RAMMemory MapByte/Word Access
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Can You Draw a Memory Map of this?
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How about Intel 80386 case?
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Data Organization in Memory
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Data/Address Organization in Memory
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Big-EndianWords are stored with the lower 8- bits in the higher of the two storage locationsAs opposed to little- endian (lower-order byte stored in the lowest addr) processors, like the Intel 80x86 family
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Signal Description
4. BUS ARBITRATION CONTROL
Bus Request (~BR)
Bus Grant (~BG)
Bus Grant Acknowledge (~BGACK)
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Signal Description5. INTERRUPT CONTROL (IPL0,IPL1,IPL2)
These input signals indicate the encoded priority level of the device requestingan interrupt.Level seven, which cannot
be masked, has the highest priority; level zero indicates that no interrupts are requested. IPL0 is the least significant bit of the encoded level, and IPL2 is the most significant bit.
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Signal Description
6. SYSTEM CONTROLBus Error (~BERR)Reset (~RESET)⌧The processor assertion of
~RESET (from executing a ~RESET instruction) resets all external devices of a system without affecting the internal state of the processor.
Halt (~HALT)⌧An input to this bidirectional
signal causes the processor to stop bus activity at the completion of the current bus cycle.
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Signal Description
7. M6800 PERIPHERAL CONTROL
Enable (E)Valid Peripheral Address (~VPA)Valid Memory Address (~VMA)
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Signal Description
8. PROCESSOR FUNCTION CODES (FC0, FC1, FC2)
9. CLOCK (CLK): 8MHz
10. POWER SUPPLY (VCC and GND)