uart harish

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U N D E R T H E G U I D E N C E O FM S . P P R U T H V I

UART IMPLEMENTATION

By

HARISH MADUPU114513M.Tech. I SEM

EI



WHAT AND WHY?

The UART (universal asynchronous receiver andtransmitter) module provides asynchronous serialcommunication with external devices such as

modems and other computersThe UART can be used to control the process of breaking parallel data from the PC down into serialdata that can be transmitted and vice versa for

receiving data.The UART allows the devices to communicate without the need to be synchronized

HARISH MADUPU 114513



The Complete Block




Transmitter Pins

Mclkx16 => Master input clock for internal baudrate generation




Clock division

There should be a clock divider running at 16 times the baud rate driving the UART modules.The transmitter and receiver modules with a clock divider inside runs 16 times slower than the clock signal

sent to it.If for example, you want to transmit at 33.6 kbps and theFPGA board runs at 25.175 MHz then:Baud rate x 16 = 33600 x 16 = 537600Clock division ratio = 25175000 / 537600 = 46Clock divisor = 46 / 2 = 23Therefore, the clock divider used to clock the UART would have a divisor of 23. This would give atransmission rate of about 34.2 kbps.




Transmitter Pins

Reset => Master reset




Transmitter Pins

Txrdy => Indicates new data has been written tothe transmitter




Transmitter Pins

Write => Active low strobe signal, used for writing data in to transmitter




Transmitter Pins

data (7 down to 0) => Bi-directional data bus forsending/receiving data across the UART




Transmitter Pins

Tx => Transmitter serial output. Held high whenno transmission occurring and when resetting




Transmission Format

This implementation of the UART transmits in blocks of 11 bits




In the transmission of a sequence the active low start bit indicates to the receiving UART that a new sequence of data is on its way

The parity can be set as even or odd and is used toindicate whether or not there has been an error inthe received data bitsThe data is transmitted LSB first




Receiver Pins

Parityerr => Indicates whether a parity error wasdetected during the receiving of a data frame




Receiver Pins

Framingerr => Indicates if the serial data format sentto the rx input did not match the proper UART dataformat




Receiver Pins

Overrun => Indicates whether new data sent in isoverwriting the previous data received that has not been read out yet.




Receiver Pins

Rxrdy => Indicates new data has been receivedand is ready to be read out.




Receiver Pins

Read => Active low strobe signal, used forreading data out from the receiver.




Receiver Pins

Rx => Receiver serial input. Pulled-up when notransmissions taking place




Implementational Architecture




Process of Transmission…

transmitting data through the UART begins by firstchecking the txrdy line. A high txrdy signal indicatesthat new data can be written to the transmitter

To write to the transmitter place the data to betransmitted on the data line.The data is then latched into the UART's transmitmodule by a leading low signal to the write line.

The next data sequence can be latched once thetxrdy line goes high again.




Process of Transmission…

while not transmitting, the data line must not bedriven but left floatingto avoid dealing with tri-state buffers, modify the

UART module by giving it separate parallel inputand output ports.




Transmitter Entity

Pi => data (7 downto 0)Clk => Mclkx16 Wrt => Write




Initializing Transmitter…

Txrdy signal will be high for every 16 clock cycles.




Transmit Data Serially

Start ,parity and stop bits are added to data andtransmitted serially




Transmitter Output




Process of reception…

The process of receiving data through the UART begins by waiting for the rxrdy line to go high. A high rxrdy indicates that data has been received

and is ready to be read out.To read the data out from the UART's data lineassert a low signal to the read line. This will latch thereceived data from the receiver to the data line

allowing you to read it.




Process of Reception…

The parityerr , framingerr , and overrun linesindicate any problems with the current received dataThe next data received can be read out once rxrdy

goes high again.




Receiver Entity




Expected results

Receiver output


uart harish

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