TVLSI12

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 8, AUGUST 2012 1487

Buried Silicon-Germanium pMOSFETs:Experimental Analysis in VLSI Logic Circuits

Under Aggressive Voltage ScalingFelice Crupi, Massimo Alioto, Senior Member, IEEE, Jacopo Franco, Paolo Magnone, Ben Kaczer,Guido Groeseneken, Fellow, IEEE, Jérôme Mitard, Liesbeth Witters, and Thomas Y. Hoffmann

Abstract—In this paper, the potential of Silicon-Germanium(SiGe) technology for VLSI logic applications is investigatedfrom a circuit perspective for the first time. The study is basedon experimental measurements on 45-nm SiGe pMOSFETs witha high- /metal gate stack, as well as on 45-nm Si pMOSFETswith identical gate stack for comparison. In the reference SiGetechnology, an innovative technological solution is adopted thatlimits the SiGe material only to the channel region. The resultingSiGe device merges the higher speed of the Ge technology withthe lower leakage of the Si technology. Appropriate circuit- andsystem-level metrics are introduced to identify the advantagesoffered by SiGe technology in VLSI circuits. Analysis is performedin the context of next-generation VLSI circuits that fully exploitcircuit- and system-level techniques to improve the energy effi-ciency through aggressive voltage scaling, other than low-leakagetechniques. Analysis shows that the SiGe technology has moreefficient leakage-delay and dynamic energy-delay trade-offs atnominal supply, compared to Si technology. Moreover, it is shownthat the traditional analysis performed at nominal supply actuallyunderestimates the benefits of SiGe pMOSFETs, since the speedadvantage of SiGe VLSI circuits is further emphasized at lowvoltages. This demonstrates that SiGe VLSI circuits benefit fromaggressive voltage scaling significantly more than Si circuits,thereby making SiGe devices a very promising alternative to Sitransistors in next-generation VLSI systems.

Index Terms—Aggressive voltage scaling, digital circuits,emerging technologies, energy efficiency, power-delay trade-off,Silicon-Germanium, VLSI.

Manuscript received July 06, 2010; revised February 02, 2011; accepted June10, 2011. Date of publication July 22, 2011; date of current version June 14,2012.F. Crupi is with the Dipartimento di Elettronica, Informatica e Sistemistica

(DEIS), Università della Calabria, 87036 Rende, Italy.M. Alioto is with the Dipartimento di Ingegneria dell’Informazione (DII),

Università di Siena, 53100 Siena, Italy, and also with the Berkeley WirelessResearch Center, Electrical Engineering and Computer Science Department,University of California, Berkeley, CA 94704-1302 USA (e-mail: [email protected]; [email protected]).J. Franco and G. Groeseneken are with the Interuniversity Microelectronics

Center (IMEC), 3001 Leuven, Belgium, and also with the Department ofElectrical Engineering (ESAT), Katholieke Universiteit Leuven, 3001 Leuven,Belgium.P. Magnone is with the Advanced Research Center on Electronic Systems for

Information and Communication Technologies E. De Castro (ARCES), Univer-sità di Bologna, 40125 Bologna, Italy.B. Kaczer, J. Mitard, L. Witters, and T. Y. Hoffmann are with the Inter-

university Microelectronics Center (IMEC), 3001 Leuven, Belgium.Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TVLSI.2011.2159870

I. INTRODUCTION

T WO major technological breakthroughs have enabledthe enhancement of the performance and the energy

efficiency of sub-100-nm CMOS VLSI circuits [1], [2]. Thefirst one was the introduction of the strain engineering sincethe 90-nm technology node, which allowed for dramaticallyboosting the performance thanks to the higher channel mobility.The second one was the introduction of the high-k metal gatestack since the 45-nm technology node, which is highly ben-eficial in terms of energy efficiency thanks to the suppressionof the gate leakage. In order to sustain the trends indicatedby the ITRS roadmap, other technological breakthroughs areexpected below the 22-nm technology generation. A possibletechnological solution is the use of high-mobility material asreplacement of Si for the device channel. Germanium-basedand III-V materials are currently under extensive investigationby the device community while the circuit and system com-munity is waiting for response. Consequently, the results onhigh-mobility materials available in the literature focus on thedevice features and do not provide enough information on thesuitability for VLSI implementations.Energy efficiency issues are progressively pushing for more

aggressive voltage scaling and finer granularity to improveperformance-per-watt (e.g., laptop computers, portable mediaplayers) [3]–[5]. Clearly, the energy efficiency benefits mostfrom ultra-dynamic voltage scaling (UDVS) when performanceexhibits a low degradation under a given voltage reduction,whereas dynamic and leakage power exhibit a large reduc-tion [6]–[8]. In particular, the performance/power reductionobtained with UDVS is strongly dependent on the adopted tech-nology and the design approach at circuit and system level [9],[10]. This means that the assessment of emerging technologiesas candidate replacements of Si devices for next-generationVLSI circuits must be carried out under the realistic scenariowhere UDVS and low-leakage techniques are extensivelyemployed [11].Recently the same authors proposed a novel evaluation

methodology that aims to fill this gap between device char-acterization and VLSI systems by extracting circuit- andsystem-level features from pure on-wafer experimental mea-surements of a newly developed technology. This methodologywas applied to Germanium pMOSFETs very recently [12]. Thismeasurement-based methodology permits to perform an earlyassessment of the technology well before having a complete

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1488 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 8, AUGUST 2012

design kit. This approach does not require 2-D/3-D devicesimulations, which are not well calibrated for semiconductorsdifferent from Si. Our analysis in [12] showed that althoughVLSI circuits with Ge pMOSFETs overcome their Si counter-parts in terms of speed, some technological issues need to besolved especially for reducing the junction leakage.In this paper, we adopt and extend the above approach to

buried SiGe channel pMOSFETs [13]–[18]. An interestingstudy on the potential advantages of SiGe devices for VLSI cir-cuits based on theoretical simulations has been reported in [19].However, experimental analysis of nanometer SiGe transistorswould be more reliable and hence preferable to simulations,which are based on simplifying assumptions and do not ac-count for process non-idealities. In this paper, the potential ofSiGe technology for VLSI logic circuits is explored throughan experimental evaluation at 45-nm technology generation.In particular, two main goals will be pursued. The first is tounderstand the speed advantage offered by SiGe technologyin the context of VLSI circuits that fully exploit circuit- andsystem-level techniques to improve the energy efficiency (e.g.,UDVS, power gating). The second purpose is to show that theSiGe technology offers an excellent leakage-delay trade-off,since it can merge the higher speed of the Ge technology withthe lower leakage of the Si technology.This paper is structured as follows. SiGe pMOSFETs are

reviewed in Section II, where details of the fabrication of theconsidered devices are provided. Various figures of merit forperformance at circuit level are introduced in Section III tocompare SiGe and Si technologies from a speed perspective.In Section IV, this performance improvement is traded off forlower power consumption, and the efficiency of dynamic-en-ergy delay and leakage-delay trade-off is analyzed under theadoption of aggressive voltage scaling. Finally, conclusions aredrawn in Section V.

II. ADOPTED SIGE TECHNOLOGY AND BASIC PROPERTIES OFSIGE PMOSFETS

Devices were fabricated at IMEC using 300 mm (100) Siwafers. Fig. 1(a) and (b) shows the cross-sectional sketchand image of the final device. A thin compressively strained

layer is epitaxially grown onto a relaxed Si buffer.This strain effect is expected to be beneficial for the mobility[20]. On top of this SiGe layer, a thin Si cap is grown.A detailed description of the epi-process can be found else-

where [21], [22]. The Si cap is needed to avoid SiGe oxidationcausing an increase of interface defects during gate stackfabrication which starts with a very thin wet chemical oxide.On top of this interfacial layer (IL), 2 nm of aredeposited using atomic layer deposition (ALD). Finally a metalgate is deposited. Due to the valence band offset between theSiGe and the Si [see Fig. 1(c)] inversion channel holes are con-fined in the SiGe layer, which therefore behaves as a quantumwell for holes. This causes the Si cap thickness to lower theinversion capacitance as compared to the accumulation capac-itance. It is then necessary to report the capacitance-equiva-lent thickness in inversion , which was estimated to be1.65 nm. Channel width and physical gate length were 90 and45 nm, respectively.

Fig. 1. (a) Cross-sectional TEM image of SiGe pMOSFET. (b) Cross-sectionalsketch. (c) Band diagram in inversion. Channel holes are confined in the SiGequantum well due to valence band offset toward the Si layers. The Si cap addi-tionally displaces channel holes, therefore lowering the inversion capacitance.

For comparison purposes, we characterized a second set ofstandard Si channel devices with identical dimensions and gatestack. was estimated as 1.31 nm for these devices. It isworth to emphasize that, although having the same gate stack, Sidevices show a lower as compared to the of the SiGechannel devices: as mentioned above, this is due to the impactof the thin Si cap acting as an additional displacement for holesin the latter case.The device measurements were done at wafer-level using

a semiconductor characterization system based on multipleKeithley 2602 instruments. For the typical investigated ,the ITRS roadmap [1] indicates that the supply voltages arein the range –1.2 V based on the technology re-quirements (high-performance or low-power). In this work, wechoose the intermediate value 1 V. The SiGe and Sidevices have different threshold voltages, 0.147 Vand 0.357 V, respectively, as found by applying themaximum transconductance method [23]. Since the thresholdvoltage in the SiGe process is not optimized and is significantlydifferent with respect to Si devices, in order to perform a faircomparison, we shifted the I-V curves in such a way to equalizethe threshold voltages 0.33 V for both SiGeand Si devices.1

In Fig. 2 we report the drain current as a function ofgate voltage overdrive measured in Si andSiGe pMOSFETs at (a) low and (b) high . Theon-current achieved for 1 V and

667 mV for the Si (SiGe)device is 684 A m (705 A m), hence at first glance theon-current advantage of SiGe devices is negligible. However,this result is not representative of practical cases, and a more

1For example, this can be easily done by adjusting the work function of thegate by selecting a proper metal or by inserting a cap layer between the high-kdielectric and the metal gate.

CRUPI et al.: BURIED SILICON-GERMANIUM PMOSFETS 1489

Fig. 2. Measured drain current versus gate voltage overdrive in Si and SiGepMOSFETs at (a) 50 mV and (b) at 1 V. The on-current im-provement observed at low is strongly reduced at high . Si and SiGepMOSFETs exhibit the same sub-threshold slope (see insets).

fair performance comparison will be presented in the nextsection. On the other hand, at low the SiGe on-currentimprovement is significantly higher (1.41 ), and reaches1.78 after normalizing by . This observation suggests amobility enhancement up to about 80%. It is worth noting thatthe reduction of the speed advantage at higher voltages is acommon property of all high-mobility materials. The physicalreason is that at high longitudinal fields the carrier velocitytends to saturate and the speed advantage of high-mobilitymaterials is significantly reduced. In the following section wewill show how the improvement in several speed figures ofmerit at circuit and system level is actually between the speedimprovement at high voltages and that of low voltages.As highlighted in the insets of Fig. 2, SiGe devices exhibit the

same sub-threshold slope (SS) values as Si pMOSFETs. It is im-portant to underline that the SiGe pMOSFETs used in this workdo not suffer from the high junction leakage of Ge devices re-ported in [12], thanks to the proposed architecture which limitsthe use of SiGe material only to the channel layer. Moreover,the drain-induced barrier lowering (DIBL) coefficients of theSiGe and Si technologies are very close as well (see Table I).Note that the slightly higher measured in SiGe pMOS-FETs is simply because equalizing the extracted with themaximum transconductance method does not guarantee exactlythe same in devices with the same SS, and also because ofthe strong dependence of on the . From a more prag-matic perspective, since the main leakage parameters (SS andDIBL coefficient) are almost equal for SiGe and Si devices, weconclude that the leakage in SiGe pMOSFETs is actually verysimilar to that of Si devices. These observations bring us to theconclusion that the proposed buried SiGe pMOSFETs merge thehigher speed of the Ge technology with the lower leakage of theSi technology.

TABLE IDEVICE PARAMETERS OF SiGe AND Si pMOSFETs

TABLE IIFIGURES OF MERIT EXPRESSING THE ADVANTAGES OF SiGe

OVER Si pMOSFETs

As a further advantage, we have recently reported that theproposed SiGe devices exhibit remarkably reduced negative-bias temperature instability and lower 1/f noise with respect totheir silicon counterparts [17], [18].

III. SPEED POTENTIAL OF VLSI CIRCUITS WITH SIGEPMOSFETS UNDER AGGRESSIVE VOLTAGE SCALING

In this section, we evaluate the performance improvementoffered by the SiGe pMOSFET for a reference inverter gate(see Section III-A) and for more complex logic gates containingstacked transistors (see Section III-B). In both cases, we assumethat the load is dominated by the gate capacitance (i.e., the con-sidered logic gate is driving nearby cells). All comparisons areperformed by equalizing the threshold voltage 0.33 Vand the supply voltage for both SiGe and Si technologies. Themain results are summarized in Table II.

A. Analysis of Reference Inverter Gate

The speed benefits brought by SiGe devices can be intuitivelygrasped by inspecting Fig. 3, where the ratio betweenthe on-current and gate capacitance of SiGe normalized to theSi counterpart is plotted as a function of voltages and

- . The normalization of the drain current for the gatecapacitance has been simply obtained by multiplyingthe drain current for the capacitance-equivalent thickness ininversion . From this figure the largest speed im-provement (up to 1.91) is observed at low , whereas asignificantly smaller improvement (down to 1.28) is obtainedat high . In the following, practical cases where a large


Fig. 3. Ratio of between SiGe and Si pMOSFETs as a function of thebias voltages, and . The large speed improvement observed atlow (up to 1.91) is strongly reduced at high (down to 1.28). The speedimprovement observed at low and high is due to differencesin the DIBL behavior.

benefit can be achieved will be identified and discussed byintroducing appropriate figures of merit.An extremely simple figure of merit expressing the speed ad-

vantage of SiGe over Si is

(1)

where the on-current is defined as the MOSFET currentwhen . To better understand the impactof UDVS, the figure of merit in (1) obtained from experimentalmeasurements was plotted in Fig. 4(a) versus . This figureclearly shows that is always greater than one andtends to increase at low voltages, i.e., SiGe circuits have a largerperformance advantage when the supply voltage is aggressivelyscaled. In particular, the speed improvement in (1) is 1.30 at

1 V and 1.41 at 600 mV. It is worth empha-sizing that since this speed improvement is a consequence ofreducing the longitudinal electric field (roughly proportional to

), it emerges when we reduce the supply bias for a fixedchannel length , as in the case of circuits which exploit UDVStechniques. On the other hand, this advantage does not apply tothe case of the reduction associated with the technology(i.e., channel length) scaling, because in this case the longitu-dinal field is almost the same.The figure of merit in (1) is based on the evaluation of the

on-current at maximum voltage, hence it is not necessarily re-alistic since transistors actually experience large voltage varia-tions during the output transition of a generic logic gate. As amore rigorous measure of speed, let us evaluate the inverter gatedelay by using the actual on-current that is delivered by the tran-sistor during the output transition. In particular, assuming thatthe load is dominated by the input capacitance of the subsequentlogic gates, the load capacitance can be expressed as ,being the input (gate) capacitance of a reference logic gate(e.g., a minimum inverter) and the equivalent number ofdriven transistors (it accounts for both the fan-out and the size ofthe transistors of the loading gates). By modeling the transistoras a current source delivering a current

(being the current delivered by a

Fig. 4. Advantage of SiGe pMOSFETs with respect to Si devices in terms of(a) on-current, (b) delay time, and (c) rise time as a function of for differentnumbers of stacked devices . In all cases, the speed improvement of SiGepMOSFETs increases with decreasing and with increasing . As ex-pected, is larger than , which is slightly larger than

.

minimum-sized transistor, and the driving strength ofthe considered cell), the gate delay can be expressed as

(2)

To fairly compare a generic SiGe and Si logic gate, let us assumethe same driving strength in (2), as well as the same fan-out andsize of the loading gates (i.e., the same ). Hence, the resultingfigure of merit that evaluates the speed advantageof SiGe over Si technology results to

(3)which is plotted in Fig. 4(b) versus . Observe that all pa-rameters in (3) can be derived directly from device measure-ments, as required by our evaluation approach. As expectedfrom the larger speed advantage of SiGe devices at lower ,the value increases at lower supply voltage andis slightly higher than the corresponding value. Inparticular, SiGe technology offers a 1.3 speed advantage at

1 V and a 1.44 speed improvement at 600


mV. This means that SiGe technology offers a significant speedadvantage at nominal , and its performance tends to experi-ence a smaller degradation when is scaled down, comparedto Si technology. This is a very nice feature of SiGe circuits inthe context of next-generation VLSI systems with UDVS, andis again explained by the greater SiGe mobility enhancement atlow longitudinal fields.As a further interesting aspect related to the performance of

VLSI circuits that is traditionally neglected, let us compare therise time of SiGe and Si inverters. This comparison gives infor-mation on the speed improvement in the output transition of alogic gate. For example, the rise time is very important in thecase of local clock buffers (i.e., driving the clock of a clock do-main), since their rise time defines the local clock slope, whichstrongly impacts the energy-delay trade-off in clock domains[24]. To comparatively evaluate the rise time of SiGe and Sicircuits, let us resort to a procedure that is similar to that usedto derive (3), which leads to the following figure of merit ex-pressing the advantage of SiGe over Si

(4)

where it was considered that the transistor current determinesthe output transition from 10% to 90% of the supply voltage.(4) is plotted in Fig. 4(c) versus for the reference tech-nologies. From this figure, the rise time benefits from the adop-tion of SiGe technology even more than the gate delay. Thiscan be intuitively explained by considering that the rise timeis affected more by currents at low voltages, since the outputvoltages varies up to 90% of , instead of 50%. More quan-titatively, SiGe technology exhibits a rise time improvementby 1.45 at 1 V, and an even better improvement isachieved at lower voltages, reaching a remarkable 1.56 at

600 mV. This means that in general SiGe inverters havesignificantly sharper transitions compared to Si counterparts,other than having a faster response (i.e., lower delay). In turn,sharper output edges in SiGe circuits keep the delay of subse-quent gates and their short-circuit power smaller, other than per-mitting to downsize buffers for a targeted signal slope (therebyreducing their dynamic and leakage consumption, which is ben-eficial in the local distribution of the clock within a clock do-main [24]).

B. Extension to Complex Gates

In general, transistor stacking in complex gates leads toa degradation of the on-current. Since the proposed SiGepMOSFETs show the same leakage behavior (in terms of SSand DIBL) of their Si counterparts, the following comparativeanalysis is focused on the on-current degradation associatedwith the transistor stacking. Since stacked transistors were notavailable for direct measurements, we applied an appropriatenumerical procedure which allows for extracting the bias pointof the stacked transistors from measurements of as a func-tion of , , and on a single pMOSFET [12]. Asshown in Fig. 4(a), a significantly lower degradation associatedwith the transistor stacking is observed in SiGe pMOSFETs. Inparticular, the speed improvement at 1 V is 1.30, 1.50,

and 1.62 for a number of stacked transistors 1, 2,and 3, respectively. This improvement is clearly a consequenceof the reduction in when a larger number of stackedtransistors is adopted. An even larger advantage is obtained byconsidering the joint effect of bias supply voltage reductionand transistor stacking. For example, the speed improvementreaches 1.70 at 600 mV and . As shownin Figs. 4(b) and (c), this advantage further increases if weconsider the figures of merit and ,instead of the simplistic figure of merit . For example,the reaches a remarkable 1.74 at 600 mVand , i.e., SiGe technology has a 74% speed im-provement over Si technology.

IV. ENERGY/POWER-DELAY TRADE-OFF IN SIGE VLSICIRCUITS UNDER AGGRESSIVE VOLTAGE SCALING

In Section III, it was shown that SiGe circuits exhibit asignificant speed advantage over Si circuits at same thresholdvoltage and supply voltage. In this section, this performanceimprovement is traded off for lower consumption, and SiGeand Si leakage are compared at iso performance in the contextof systems with aggressive voltage scaling. The resultingadvantage in terms of dynamic and leakage consumption isdiscussed in Sections IV-A and IV-B, respectively. The mainresults are summarized in Table II.

A. Dynamic Energy-Delay Trade-Off and Voltage Scaling

Let us consider the case where the performance improvementoffered by SiGe technology is traded off for lower power con-sumption by reducing the SiGe supply voltage to achieve thesame gate delay as the Si counterpart, assuming both technolo-gies have the same threshold voltage as in Section III. The re-sulting supply voltage of the SiGe circuit leading tothe same gate delay as the Si counterpart powered by voltage

(i.e., such that ) is plotted in Fig. 5.As expected, from this figure the SiGe circuit voltageis typically 20–30% lower than at same performance(slightly higher for circuits with a higher number of stackedtransistors). More in detail, the SiGe voltage reduction tends tobe smaller when is closer to the threshold voltage, sincethe delay becomes more sensitive to voltage reductions.The above discussed SiGe voltage reduction at iso-perfor-

mance is clearly beneficial in terms of dynamic energy. Morespecifically, assuming again that the capacitance at the output ofan inverter is dominated by the gate capacitance, the dynamicpower can be expressed as . Similarly to thederivation of (3), let us adopt the figure of merit thatexpresses the dynamic power at iso-performance (or energy) ad-vantage of SiGe compared to Si

(5)

where is the resulting supply voltage of the SiGe cir-cuits matching the same delay as the Si counterpart poweredwith a supply . As shown in Fig. 6, SiGe technology al-lows a remarkable dynamic power saving that increases by in-creasing . More quantitatively, the dynamic energy is re-duced by a factor 1.64 (1.71) at 600 mV and 1.98 (2.21)


Fig. 5. Supply voltage of SiGe pMOSFETs required to match the gate delayof the Si counterpart as a function of supply voltage of Si pMOSFETs for dif-ferent numbers of stacked devices . The SiGe supply voltage reduction

increases when increasing and .

Fig. 6. Advantage of SiGe in terms of dynamic energy versus Si supply voltage(SiGe supply set tomatch performance) for different numbers of stacked devices

.

at 1 V for . The stronger re-duction at high supply voltages could appear contradictory tothe higher improvement observed at lower supplyvoltage. However, this trend can be explained by consideringagain that the delay becomes more sensitive to voltage reduc-tions when the voltage is reduced. Anyway, the above resultsclearly show that SiGe circuits benefit from aggressive voltagescaling muchmore than Si counterparts, as . Thisconsiderable improvement in the energy efficiency is highlybeneficial in today’s and future systems-on-chip operating in apower limited regime [25]. As additional benefit of the reducedsupply voltage of SiGe circuits, a significant improvement intheir reliability is expected [17]. It is worth noting that a 4- to6-fold reduction in the dynamic power of SiGe devices was re-ported in a previous study based on theoretical simulations [19].This higher value could be ascribed to the higher bias voltageof 2.5 V used in [19].

B. Leakage-Delay Tradeoff and Voltage Scaling

The reduced supply voltage enabled by SiGe circuits atiso-performance can also provide a significant reduction inleakage power. In general, the leakage power in a technologyis meaningfully expressed by where is thesubthreshold leakage current of a minimum-sized inverter,evaluated at and . The resulting figure of

Fig. 7. Advantage of SiGe in terms of leakage power versus Si supply voltage(SiGe supply set to match performance).

merit that evaluates the leakage power reduction ofSiGe over Si technology results to

(6)

Assuming the scenario where SiGe and Si devices havethe same threshold as in Section III and the SiGe supply isscaled to match the Si performance (as discussed at the be-ginning of Section IV-A), the resulting figure of merit in (6)is plotted in Fig. 7. From this figure, SiGe technology allowsfor a considerable reduction of leakage power, which is evenlarger than the dynamic power saving and ranges from 1.65to 3.36 when ranges from 600 mV to 1.2 V. Thisreduction is in part due to the leakage reduction resultingfrom the voltage reduction through the DIBL effect [i.e., thefactor in (6)], and in part to the voltagereduction itself [i.e., the factor in (6)]. Morespecifically, the ratioranges from 1.45 to 2.55 (from 1.14 to 1.32), hence the leakagepower reduction is mainly due to the leakage current reduction(thanks to DIBL effect) rather than the voltage reduction itself.Observe that the leakage power reduction in Fig. 7 increases byincreasing for the same reasons that were discussed inthe previous subsection. The above results permit to evaluatethe intrinsic advantage in terms of leakage of SiGe technologyin VLSI circuits, as no low-leakage technique was accountedfor. However, practical applications always require the adop-tion of techniques to keep leakage under control. In particularpower gating is the most popular technique, since it is effectiveand can be easily integrated in automated design flows [5]. Inpower gating schemes, a sleep transistor with high thresholdis introduced to cut off a circuit from its power rail duringthe standby mode [5]. To compare the effectiveness of thistechnique in SiGe and Si circuits, we made two assumptions.First, the (higher) threshold of the sleep transistor was set sothat the intrinsic leakage of the sleep transistor is lower thanthat of transistors within logic gates by a decade (i.e., thethreshold voltage of the sleep transistor is increased by a valuecorresponding to the subthreshold slope in V/dec, as comparedto transistors in logic gates with standard threshold). Second,the width of the sleep transistor was sized to keep itsmaximum voltage drop (which degrades the effective supplyvoltage seen by logic gates) in active mode to 5% of .


Fig. 8. Leakage reduction when sleep transistors are used to drive 100inactive pMOSFETs as a function of the simultaneously active gates .SiGe devices allow a larger leakage reduction (by a factor 1.4) with respect totheir Si counterparts.

Clearly, the maximum voltage drop depends on the current thatis drawn by the logic gates, which is in turn set by the maximumnumber of logic gates that switch simultaneously. Intuitively,power gating is expected to be more effective in SiGe circuits,as compared to Si counterparts. Indeed, SiGe sleep transistorshave a significantly greater driving capability compared toSi counterparts, especially considering that their source-drainvoltage is quite low (a few percentage points of ). Hence,SiGe sleep transistors can be made smaller compared to Sicounterparts under the same voltage drop requirement, therebyreducing the overall leakage.To achieve quantitative results, we assumed for simplicity

that a sleep transistor is connected to 100 minimum-sized in-verters (with width ). Then, we repeated the sleep tran-sistor sizing and leakage calculations by progressively varyingthe number of simultaneously switching gates from 10to 50. In each case, the procedure described in [12] was adoptedto evaluate leakage. Analysis showed that must be 5.9(8) times larger than to keep the voltage drop onthe SiGe (Si) sleep transistor below the 5% of . The smallerarea of SiGe sleep transistors is justified by the above qualitativeconsiderations. The resulting leakage reduction offered by SiGecompared with Si technology is plotted in Fig. 8 versus .From this figure, power gating in SiGe circuits is more effectivein reducing leakage by a factor 1.4 with respect to Si devices,and this advantage is basically independent of . Thisadvantage adds up to the considerably lower intrinsic leakagepower of SiGe technology that was discussed above.

V. CONCLUSION AND REMARKS

In this work, we have analyzed the potential of high-mobilitySilicon-Germanium (SiGe) pMOSFETs from the perspectiveof VLSI logic circuits exploiting aggressive dynamic voltagescaling. The study is based on experimental measurementsperformed on 45-nm SiGe pMOSFETs with a high- /metalgate stack having capacitance-equivalent thickness in inversionof 1.65 nm and, for comparison purposes, also on 45-nm SipMOSFETs with identical gate stack. Thanks to an innovativetechnological solution that limits the SiGe material only to thechannel region, the proposed buried SiGe pMOSFETs exhibitthe same leakage as their Si counterparts, thus overcoming the

main problem of conventional Ge pMOSFETs which sufferfrom excessively high junction leakage [12].This study brings us to two main conclusions. The first one

is that by evaluating the speed performance at the maximumsupply voltage, as is typically done in the early assessment ofa new technology, the benefits of SiGe pMOSFETs are stronglyunderestimated. Indeed, SiGe technology offers a 30% speedimprovement at nominal voltage, and an even higher advan-tage at lower supply voltages (44% at 600 mV). Hence, SiGeVLSI circuits benefit from ultra-dynamic voltage scaling muchmore than Si circuits. This is a key advantage from the perspec-tive of next-generation VLSI systems with aggressive dynamicvoltage scaling. It is worth noting that the higher speed advan-tage at lower voltages is a common property of all high-mo-bility materials. The reason is that at high longitudinal fieldsthe carrier velocity tends to saturate and the speed advantagesof high-mobility materials are significantly reduced. Further-more, SiGe buffers generatemuch sharper edges (by up to 56%),which is beneficial from both the performance and consumptionpoint of view (for example, this is very useful for local clockbuffers).Interestingly, SiGe pMOSFETs show a lower on-current

degradation when considering staked transistors. Therefore,an even larger advantage is obtained by considering the jointeffect of bias supply voltage reduction and transistor stacking.For example, the speed improvement reaches 1.74 at600 mV and . From a design perspective, this meansthat synthesis tools will tend to use high fan-in SiGe standardcells more frequently than Si technology. As a consequence,the composition of SiGe standard cell libraries is expectedto be different from Si libraries, as higher fan-in cells mustbe included to take full advantage of the above feature. Themore frequent adoption of high fan-in cells is well known to beadvantageous from an energy efficiency point of view [26].The second conclusion is that SiGe technology offers a re-

markably better power-delay trade-off for VLSI circuits withrespect to their Si counterparts. In addition to the above-men-tioned SiGe speed advantages obtained at similar leakage con-ditions, it was shown that SiGe technology exhibits a significantpower saving at iso-performance by appropriately reducing theSiGe supply voltage. For example, the dynamic (static) powersaving is 1.98 (2.95 ) at 1 V. As a further interestingfeature, leakage suppression through power gating with SiGepMOSFETs is more effective than in Si circuits by a factor 1.4,as the former technology tends to reduce the size of sleep tran-sistors under the same requirements.To our knowledge, the reported advantages of the buried

SiGe pMOSFETs for VLSI logic circuits overcome the onesreported for other high-mobility technologies (like Ge tech-nology), which suffer of excessive leakage penalty, thussuggesting that SiGe pMOSFET is a promising candidate forthe next generations of CMOS VLSI circuits.

REFERENCES

[1] “International Technology Roadmap for Semiconductors,” [Online].Available: http://public.itrs.net

[2] H.-S. P. Wong, “Beyond the conventional transistor,” IBM J. Res. De-velop., vol. 46, no. 2/3, pp. 133–168, 2002.


[3] A. Chandrakasan, W. Bowhill, and F. E. Fox, Design of High-Perfor-mance Microprocessor Circuits. New York: IEEE Press, 2001.

[4] A. Chandrakasan et al., “Technologies for ultradynamic voltagescaling,” Proc. IEEE, vol. 98, no. 2, pp. 191–212, Feb. 2010.

[5] S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOSTechnologies. New York: Springer, 2006.

[6] B. Calhoun and A. Chandrakasan, “Ultra-dynamic voltagescaling (UDVS) using sub-threshold operation and local voltagedithering,” IEEE J. Solid-State Circuits, vol. 41, no. 1, pp.238–245, Jan. 2006.

[7] M. E. Sinangil, N. Verma, and A. Chandrakasan, “A reconfig-urable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp.3163–3173, Nov. 2009.

[8] M.-E. Hwang, A. Raychowdhury;, K. Keejong, and K. Roy, “A85 mV 40 nW process-tolerant subthreshold 8 8 FIR filter in130 nm technology,” in Proc. IEEE Symp. VLSI Circuits, 2007,pp. 154–155.

[9] Z. Bo, D. Blaauw, D. Sylvester, and K. Flautner, “Theoretical andpractical limits of dynamic voltage scaling,” in Proc. DAC, 2004, pp.868–873.

[10] M.-E. Hwang, T. Cakici, and K. Roy, “Process tolerant adaptive -ratiomodulation for ultra-dynamic voltage scaling,” in Proc. DATE, 2007,pp. 1–6.

[11] M. Agostinelli, M. Alioto, D. Esseni, and L. Selmi, “Leakage-delaytradeoff in FinFET logic circuits: A comparative analysis with bulktechnology,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.16, no. 2, pp. 232–245, Feb. 2010.

[12] P. Magnone, F. Crupi, M. Alioto, B. Kaczer, and B. De Jaeger, “Un-derstanding the potential and the limits of Germanium pMOSFETs forVLSI circuits from experimental measurements,” IEEE Trans. VeryLarge Scale Integr. (VLSI) Syst., 10.1109/TVLSI.2010.2053226 .

[13] N. Collaert, P. Verheyen, K. DeMeyer, R. Loo, andM. Caymax, “High-performance strained Si/SiGe pMOS devices with multiple quantumwells,” IEEE Trans. Nanotechnol., vol. 1, no. 4, pp. 190–194, Dec.2002.

[14] N. Collaert, P. Verheyen, K. De Meyer, R. Loo, and M. Caymax, “In-fluence of the Ge-concentration and RTA on the device performanceofstrained Si/SiGe pMOS devices,” in Proc. Eur. Solid-State DeviceRes. Conf., 2002, pp. 263–266.

[15] P. Majhi, P. Kalra, R. Harris, K. J. Choi, D. Heh, J. Oh, D.Kelly, R. Choi, B. J. Cho, S. Banerjee, W. Tsai, H. Tseng, andR. Jammy, “Demonstration of high-performance PMOSFETs using

quantum wells with high- /metal-gate stacks,”IEEE Electron Device Lett., vol. 29, no. 9, pp. 99–101, Sep. 2008.

[16] S. H. Lee, P. Majhi, J. Oh, B. Sassman, C. Young, A. Bowonder, W.-Y.Loh, K.-J. Choi, B.-J. Cho, H.-D. Lee, P. Kirsch, H. R. Harris, W. Tsai,S. Datta, H.-H. Tseng, S. K. Banerjee, and R. Jammy, “Demonstrationof pMOSFETs with CHANNELS,HIGh , and controlled Short Channel Effects(SCEs),” IEEE Electron Device Lett., vol. 29, no. 9, pp. 1017–1020,Sep. 2008.

[17] J. Franco, B. Kaczer, M. Cho, G. Eneman, and G. Groeseneken, “Im-provements of NBTI reliability in SiGe p-FETs,” in Proc. Int. Reliab.Phys. Symp., 2010, pp. 1082–1085.

[18] J. Franco, B. Kaczer, G. Eneman, J. Mitard, A. Stesmans, V. Afanas’ev,T. Kauerauf, P. J. Roussel, M. Toledano-Luque, M. Cho, R. Degraeve,T. Grasser, L.-Å. Ragnarsson, L. Witters, J. Tseng, S. Takeoka, W.-E.Wang, T. Y. Hoffmann, and G. Groeseneken, “6 EOT Si0.45Ge0.55pMOSFET with optimized reliability : Meeting theNBTI lifetime target at ultra-thin EOT,” in IEDM Tech. Dig., 2010, pp.70–73.

[19] A. Sadek, K. Ismail, M. A. Armstrong, D. A. Antoniadis, and F. Stern,“Design of Si/SiGe heterojunction complementary metal-oxide-semi-conductor transistors,” IEEE Trans. Electron Devices, vol. 43, no. 8,pp. 1224–1232, Aug. 1996.

[20] C. Claeys, E. Simoen, S. Put, G. Giusi, and F. Crupi, “Impact strainengineering on gate stack quality and reliability,” Solid-State Electron.,vol. 52, pp. 1115–1126, 2008.

[21] R. Loo, C. Walczyk, P. Verheyen, R. Rooyackers, F. E. Leys, G. En-eman, D. Shamiryan, P. P. Absil, T. Delande, A. Moussa, H. Bender,C. Drijbooms, L. Geenen, M. Caymax, J. W. Weijtmans, R. Wise, V.Machkaoutsan, P. Tomasini, C. Arena, J. McCormack, S. Passefort,H. Sorada, A. Inoue, B. C. Lee, S. Hyun, S. Jakschik, and S. Godny,“Selective epitaxy of Si/SiGe to improve pMOS devices by recessedsource/drain and/or buried SiGe channels,” ECS Trans., vol. 3, no. 7,pp. 453–465, 2006.

[22] A. Hikavyy, R. Loo, L. Witters, S. Takeoka, J. Geypen, B. Brijs, C.Merckling, M. Caymax, and J. Dekoster, “SiGe SEG growth for buriedchannel p-MOS devices,” ECS Trans., vol. 25, no. 7, pp. 201–210,2009.

[23] D. K. Schroder, Semiconductor Material and Device Characteriza-tion. New York: Wiley, 1998.

[24] M. Alioto, E. Consoli, and G. Palumbo, “Flip-flop energy/performanceversus clock slope and impact on the clock network design,” IEEETrans. Circuits Syst. I, Reg. Papers, vol. 57, no. 6, pp. 1273–1286, Jun.2010.

[25] B. Nikolic, “Design in the power-limited scaling regime,” IEEE Trans.Electron Devices, vol. 55, no. 1, pp. 71–83, Jan. 2008.

[26] Low-Voltage/Low-Power Integrated Circuits and Systems, E. Sánchez-Sinencio and A. G. Andreou, Eds. Piscataway, NJ: IEEE Press, 1999.

Felice Crupi received the M.S. degree in elec-tronic engineering from the University of Messina,Messina, Italy, in 1997 and the Ph.D. degree fromthe University of Firenze, Firenze, Italy, in 2001.Since 2002, he has been with the Dipartimento

di Elettronica, Informatica e Sistemistica, Univer-sità della Calabria, Rende, Italy, as an AssociateProfessor of electronics. Since 1998, he has beena repeat Visiting Scientist with the InteruniversityMicro-Electronics Center (IMEC), Leuven, Bel-gium. In 2000, he was a Visiting Scientist with

the IBM Thomas J. Watson Research Center, Yorktown Heights, NY. Hismain research interests include reliability of CMOS devices, modeling andsimulation of CMOS devices, electrical characterization techniques for solidstate electronic devices, the design of ultra low noise electronic instrumentationand the design of extremely low power CMOS circuits. He has authored andcoauthored over 70 papers published in peer-reviewed journals and over 50papers published in international conference proceedings. His publicationshave been cited more than 700 times and his h-index is equal to 14 (Scopus’ssource).Prof. Crupi serves or served as a technical program committe member of the

IEEE International Electron Devices Meeting (IEDM), and the IEEE Interna-tional Reliability Physics Symposium (IRPS). He has been the Coordinator ofinternational research projects in the field of semiconductor devices and circuits.

Massimo Alioto (M’01–SM’07) was born inBrescia, Italy, in 1972. He received the Laureadegree in electronics engineering and the Ph.D.degree in electrical engineering from the Univer-sity of Catania, Catania, Italy, in 1997 and 2001,respectively.In 2002, he joined the Dipartimento di Ingegneria

dell’Informazione (DII), the University of Siena,Siena, Italy, as a Research Associate and in the sameyear as an Assistant Professor. In 2005, he was ap-pointed Associate Professor of Electronics, and was

engaged in the same faculty in 2006. In the summer of 2007, he was a VisitingProfessor at EPFL, Lausanne, Switzerland. In 2009–2011, he held a VisitingProfessor position with BWRC, UCBerkeley, Berkeley, CA, investigating onnext-generation ultra-low power circuits and wireless nodes. In 2011, he alsoholds a Visiting Professor position with University of Michigan, investigatingon technique for resiliency in near-threshold processors and ultra-low powercircuits. Since 2001 he has been teaching undergraduate and graduate courseson advanced VLSI digital design, microelectronics and basic electronics.He has authored or co-authored 170 publications on journals (60, mostlyIEEE Transactions) and conference proceedings. Two of them are among themost downloaded TVLSI papers in 2007 (respectively, 10th and 13th). He isco-author of the book Model and Design of Bipolar and MOS Current-ModeLogic: CML, ECL and SCL Digital Circuits (Springer, 2005). His primaryresearch interests include ultra-low power VLSI circuits and wireless nodes,sub- W cryptographic circuits, ultra-low standby power SRAMs, highlyefficient on-chip power converters for sub- W operation, modeling/design ofvariability-tolerant low-leakage VLSI CMOS circuits, circuit techniques foremerging technologies. He is the director of the Electronics Lab at Universityof Siena (site of Arezzo).Prof. Alioto is a member of the HiPEAC Network of Excellence. He is

the Chair of the “VLSI Systems and Applications” Technical Committee ofthe IEEE Circuits and Systems Society, for which he was also DistinguishedLecturer in 2009-2010 and member of the DLP Coordinating Committee in2011–2012. He is regularly invited to give talks and tutorials to academicinstitutions, conferences, and companies throughout the world. He serves or


has served as a member of various conference technical program committees(ISCAS, ICCD, PATMOS, ICM, ECCTD, CSIE) and Track Chair (ISCAS,ICCD, ICECS, ICM). He was Technical Program Chair of the conference ICM2010. He serves as Associate Editor of the IEEE TRANSACTIONS ON VERYLARGE SCALE INTEGRATION (VLSI) SYSTEMS, as well as of the Microelec-tronics Journal, the Integration–The VLSI journal, the Journal of Circuits,Systems, and Computers, the Journal of Low Power Electronics and Applica-tions and the ACM Transactions on Design Automation of Electronic Systems.He was Guest Editor of the Special Issue “Advances in Oscillator Analysisand Design” of the Journal of Circuits, Systems, and Computers (2010), andTechnical Program Chair for the ICM 2010 Conference.

Jacopo Franco received the B.Sc. andM.Sc. degreesin electronic engineering from the University of Cal-abria, Calabria, Italy, in 2005 and 2008, respectively.He is currently pursuing the Ph.D. degree in the re-liability group of imec and at the Katholieke Univer-siteit Leuven, Leuven, Belgium, on the topic “Inter-face stability and reliability of Ge and III-V transis-tors for future CMOS applications”.His M.Sc. thesis was developed at imec, Leuven,

Belgium, and it is related to reliability issues in ad-vanced Silicon and Germanium MOSFETs. He has

authored or co-authored over 30 publications.Mr. Franco was a recipient of the IEEE SISC Ed Nicollian Award for the Best

Student Paper in 2009.

Paolo Magnone received the B.S. and M.S. degreesin electronic engineering from the University of Cal-abria, Rende, Italy, in 2003 and 2005, respectively,and the Ph.D. degree in electronic engineering fromthe University of Reggio Calabria, Italy, in 2009.In the period 2006–2008, he joined for one

year the Interuniversity MicroElectronics Center(IMEC), Leuven, Belgium, within the “AdvancedPROcess Technologies for Horizontal Integration”Project (Marie Curie Actions), where he workedon parameters extraction and matching analysis of

FinFET devices. He was a Postdoctoral Researcher with the University ofCalabria from 2009 to 2010. He is currently with the ARCES Center, Univer-sity of Bologna. His research interests include the electrical characterization,electrothermal simulation and modeling of semiconductor devices, and thenumerical simulation of photovoltaic silicon solar cells.

Ben Kaczer received the M.S. degree in physicalelectronics from Charles University, Prague, CzechRepublic, in 1992 and the M.S. and Ph.D. degrees inphysics from The Ohio State University, Columbus,in 1996 and 1998, respectively.He is a Senior Reliability Scientist with IMEC,

Leuven, Belgium. In 1998, he joined the reliabilitygroup of IMEC, Leuven, Belgium, where his activ-ities have included the research of the degradationphenomena and reliability assessment of SiO2,SiON, high-k, and ferroelectric films, planar and

multiple-gate FETs, circuits, and characterization of Ge/III-V and MIM de-vices. He has authored or co-authored over 250 journal and conference papers.Dr. Kaczer received the OSU Presidential Fellowship and support from Texas

Instruments, Inc. for his Ph.D. research on the ballistic-electron emission mi-croscopy of SiO2 and SiC films. He was a recipient of three Best and one Out-standing Paper Awards at IRPS and the Best Paper Award at IPFA. He has pre-sented invited papers and tutorials at several international conferences. He hasserved or is serving at various functions at the IEDM, IRPS, SISC, INFOS, andWoDiM Conferences. He is currently serving on the IEEE T. Electron Dev. Ed-itorial Board.

Guido Groeseneken (F’05) received the M.Sc.degree and the Ph.D. degree in applied sciencesfrom the KU Leuven, Belgium, in 1980 and 1986,respectively.In 1987, he joined the R&D Laboratory, IMEC,

Leuven, Belgium. He is responsible for research inreliability physics for deep submicrometer CMOStechnologies and in nanotechnology for post-CMOSapplications. From October 2005 until April 2007, hewas responsible for the Post CMOS Nanotechnologyprogram within IMEC’s core partner research pro-

gram. Since 2001, he is a Professor with the KU Leuven, where he is ProgramDirector of the Master in Nanoscience and Nanotechnology and coordinatinga European Erasmus Mundus Master Program in nanoscience and nanotech-nology. He has made contributions to the fields of non-volatile semiconductormemory devices and technology, reliability physics of VLSI-technology, hotcarrier effects in MOSFET’s, time-dependent dielectric breakdown of oxides,Negative-Bias-Temperature Instability effects, ESD-protection and -testing,plasma processing induced damage, electrical characterization of semiconduc-tors and characterization and reliability of high k dielectrics. Recently he hasalso interest in such as carbon nanotubes for interconnect applications, tunnelFET’s for alternative nanowire devices, etc.Dr. Groeseneken became an IMEC Fellow in 2007. He has served as a

technical program committee member of several international scientific con-ferences, such as IEDM, ESSDERC, IRPS, SISC, and EOS/ESD Symposium.He has authored or co-authored over 500 publications in international scientificjournals and in international conference proceedings, 6 book chapters, and 10patents in his fields of expertise.

Jérôme Mitard received the Ph.D. degree in micro-electronic engineering from the Polytechnic Univer-sity School of Marseille, Marseille, France, in 2003.For three years, he acted as an STMicroelectronics

assignee with “Commissariat Energie Atom-ique–Laboratoire d’électronique et de technologiede l’information”, Grenoble, France, where he wasdeeply involved in the electrical characterizationof hafnium-based dielectrics with metal gate forsub-70-nm complementary metal–oxide–semicon-ductor (CMOS) technologies. After his Ph.D. in

microelectronics at Micro and Nanotechnologies Campus Center, Grenoble,France, he joined the Interuniversity MicroElectronics Center (IMEC), Leuven,Belgium, as a device researcher, where he is currently working on the integra-tion of high-mobility substrates for the sub-22-nm CMOS node.

Liesbeth Witters received the B.Sc. and M.Sc.degrees in chemical engineering from KatholiekeUniversiteit Leuven, Leuven, Belgium and ENSPM,Paris, France in 1992 and 1993, respectively.From 1994 to 1995, she did graduate research

work at the Civil Engineering Department, Uni-versity of California, Irvine. In 1995, she joinedRockwell Semiconductor Systems, later Conexant,in Newport Beach, CA, where she worked as aCMP Process Development Engineer. In 2001, shejoined IMEC, Leuven, Belgium, as a BiCMOS

Process Integration Engineer. Since 2004 she has been working on differentapplications in the CMOS Process Integration Department.

Thomas Y. Hoffmann received the Ph.D. degreefrom Lille University, Villeneuve d’Ascq, Lille,France, in 2000.He joined Intel Corporation’s Research and De-

velopment Group, Hillsboro, OR, as a TechnologyComputer-Aided Design Engineer for sub-90-nmtechnologies. In 2004, he moved to Intel’s Tech-nology Development Group as a Device Engineerfor 45-nm process development. In 2005, he joinedInteruniversity Microelectronics Center, Leuven,Belgium, to lead the electrical characterization

group for advanced silicon technologies. In 2009, he became the Director ofthe Front-End-of-Line Logic and Dynamic Random Access Memory DevicesResearch Program. He has authored or coauthored approximately 50 technicalpapers for publication in journals and presentations at conferences.

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