TVLSI 04 Sleep Switch

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRA TION (VLSI) SYSTEMS, VOL. 12, NO. 5, MAY 2004 485 Sleep Switch Dual Threshold Voltage Domino Logic With Reduced Standby Leakage Current Volkan Kursun , Student Member, IEEE, and Eby G. Friedman , Fellow, IEEE Abstract—A circuit tec hnique is pr esented for re duc ing the subth res hold leakage ener gy consu mpti on of domi no logic cir cuits. Slee p switc h trans istor s are propose d to place an idle dual thresh old voltage domino logic circuit into a low leakage state. The circuit technique enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current by strongly turning off all of the high threshold volta ge trans istor s. The slee p switc h cir cuit techn ique signi fic antly red uces the subthres hold leakage energy as comp are d to both stand ard low-t hre shold volta ge and dual thre shold volta ge domi no logic circuits. A domino adder enters and leaves a low leakage sle ep mod e wit hin a single clo ck cycle. The energy ove rhead of the circui t tech nique is low , justi fying the acti vatio n of the proposed sleep scheme by providing a net savings in total power consumption during short idle periods. Index T erms— Domi no carr y looka head adder, domin o logi c, dual threshold voltage CMOS techn ologi es, dynamic cir cuit s, high speed, idle mode , longe r batte ry life , low power, multipl e threshold voltage CMOS, reduced standby leakage energy, sleep mode, sleep switch, subthreshold leakage current. I. INTRODUCTION T HE POWER consu med in high- perfo rman ce micr oproc es- sor s has inc reased to le ve ls tha t impos e a fun dament al lim- itation to increasing performance and functionality [ 1]–[3]. If the current trend in increasing power continues, high performance microprocessors will soon consume thousands of watts. The power density of a high performance microprocessor will exceed the power density levels encountered in typical rocket nozzles within the next decade [2]. The generation, distributi on, and diss ipat ion of powe r are at the fore front of curre nt probl ems faced by the integrated circuit industry [ 1]–[5]. Dynamic swi tch ing po wer , the domina nt component of the total power consumed in current CMOS technologies, is quadr atic ally reduced by lowering the supp ly vol tage . Lowe ring the supply voltage, however, also degrades circuit speed due to reduced transistor currents. Threshold voltages are scaled to reduce the degradation in speed caused by supply voltage scal ing whil e main tain ing the dynamic powe r consu mpti on within acceptable levels [ 1]–[5]. At reduced threshold voltages, howeve r, subthreshold leakage currents increase exponentially . As dep ict ed in Fig. 1, sub thr eshold leakage po wer is soo n Manuscript received January 8, 2002; revised May 7, 2003. This work was supp ortedin part by the DARP A/IT O underAFRL Contr act F296 01-0 0-K- 0182, in part by the New Yo rk State Office of Science, Technology and Academic Re- search Center for Advanced Technology—Electronic Imaging Systems and the Microelectronics Design Center, and by grants from Xerox Corporation, IBM Corporation, Lucent Techno logies Corporation, and Eastman Kodak Company . The autho rs are with the Depa rtmentof Electr ical and Compu ter Engin eerin g, University of Rochester, Rochester, NY 14627-0231 USA. Digital Object Identifier 10.1109/TVLSI. 2004.82619 8 Fig. 1 . Power trends of high perf ormance microprocessors. expected to dominate the total power consumed by a CMOS circuit [1], [ 2], [ 5]. Energy efficient circuit techniques aimed at lowering leakage currents are, therefore, highly desirable. Domino logic circuit techniques are extensively applied in high performance microprocessors due to the superior speed and area characteristics of domino CMOS circuits as compared to sta ti c CMOS cir cui ts [7]–[14]. A dua l thr esh old vo lta ge (du al- ) circu it techni que was pro pos ed in [ 9] for reducing the subthreshold leakage energy consumption of domino logic cir cui ts. The techni que pro pos ed in [9] uti liz es bot h hig h and low threshold voltage transistors. High threshold voltage (high- ) trans istors ar e employ ed on t he noncri tical prec harge paths. Altern atively , low threshold v oltage (l ow- ) transist ors are employed on the speed critical evaluation paths. Gating all of the inputs of the first stage of a domino pipeline is proposed to place the idle domino gates into a low leakage state [ 9]. The energy and delay overhead for entering and leaving the sleep mode, however, has not been addressed in [ 9]. Due to the additional gates at the inputs, significant dynamic switching energy is consumed to activate the sleep mode with the technique described in [9]. Additional ener gy is dissipated to precharge all of the dynamic nodes while reactivating a domino logic circuit at the end of an idle period. In order to justify the use of addi- ti onal circ ui tr y to pl ac e a dual- circ ui t into a low leakage st at e, the total energy consumed to enter and leave the standby mode mus t be sig nif ica ntl y less tha n thesavi ngs in the st and by lea kag e energy . Gating all of the inputs of the first stage of a domino circuit in a domino pipeline also increases the circuit area and active mode power. Furthermore, the circuit performance during the active mode is degraded due to the additional gates at the inputs. A circuit technique with low delay and energy overhead 1063-8210/04$20.00 © 2004 IEEE

TVLSI 04 Sleep Switch

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