TSMC 40ULP/LP EFLX™-100 CORE PRODUCT BRIEF 40ULP/LP EFLX™-100 CORE PRODUCT BRIEF ... DDH and V...
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TSMC 40ULP/LP EFLX™-100 CORE PRODUCT BRIEF December 2016. Copyright 2014-2016 Flex Logix™ Technologies, Inc. The EFLX™-100 is an embedded FPGA IP core, for implementing reconfigurable logic, containing 120 Look-Up-Tables (LUTs: each is a dual 4-input LUT with 2 independent outputs and 2 bypassable flip flops) in Reconfigurable Building Blocks (RBBs), patented interconnect network, multiple clocks & scan: reconfigurable at any time. Target specs: EFLX™-100 Logic Core EFLX™-100 DSP Core The EFLX-100 core is available in 4 different VT configurations and 2 nominal voltages: each optimized for different performance-to-power requirements for different target applications. Target specs for EFLX-100 based on GDS for TSMC 40ULP: Configuration Bit Cell and Static Logic: select a VT RBB and DSP logic: select a VT 16-bit Counter MHz TT, 85C Deep Sleep Mode Leakage μW Core Sleep Mode Leakage μW 0.9V 1.1V TT, 85C, 0.9V eHVT eHVT 110 190 0.5 1.5 eHVT SVT 180 270 0.5 1.5 HVT HVT 110 190 1.5 4.5 HVT SVT 180 270 1.5 4.5 Inquire for EFLX-100 TSMC 40LP specs: GDS is compatible Name EFLX™-100 Core Technology TSMC 40nm ULP/LP CMOS Metal Utilization 5 metal layers Nominal Supply Voltage (V) 0.9V & 1.1V Junction Temperature (°C) −40 to 125 Leakage Power (μW) for EFLX-100 core with eHVT Bit Cell Deep Sleep Mode 0.5μW Sleep Mode 1.5μW (at 85°C, 0.9V, TT) 16-bit Counter Frequency (MHz) 110 – 270 MHz depending on VT/Vdd chosen (TT, 85C, 0.9 or 1.1V) Area (mm 2 ) 0.13 Clock Inputs 1 to 8 Data I/O (optional flops) 152 inputs and 152 outputs Logic Core DSP Core Dual 4-input LUTs with 2 independent outputs 120 88 Total flip flops (ex DSP) 544 480 DSP MACs 0 2 EFLX Array Size 1×1 to 5x5 Design-for-Test Support Yes LUT Utilization >90% AXI/JTAG soft IP Yes, if requested TSMC 40LP Compatibility Yes (inquire for 40LP specs) RBB DSP RBB Logic RBB Logic IO IO IO IO RBB Logic RBB Logic RBB Logic IO IO IO IO
Transcript of TSMC 40ULP/LP EFLX™-100 CORE PRODUCT BRIEF 40ULP/LP EFLX™-100 CORE PRODUCT BRIEF ... DDH and V...
TSMC40ULP/LPEFLX™-100COREPRODUCTBRIEF
December2016.Copyright2014-2016FlexLogix™Technologies,Inc.
The EFLX™-100 is an embedded FPGA IP core, for implementing reconfigurable logic,containing120Look-Up-Tables (LUTs:each isadual4-input LUTwith2 independentoutputsand 2 bypassable flip flops) in Reconfigurable Building Blocks (RBBs), patented interconnectnetwork,multipleclocks&scan:reconfigurableatanytime.Targetspecs:
EFLX™-100LogicCore
EFLX™-100DSPCore
TheEFLX-100coreisavailablein4differentVTconfigurationsand2nominalvoltages:eachoptimizedfordifferentperformance-to-powerrequirementsfordifferenttargetapplications.
TargetspecsforEFLX-100basedonGDSforTSMC40ULP:
ConfigurationBitCellandStaticLogic:selectaVT
RBBandDSPlogic:selectaVT
16-bitCounterMHz
TT,85C
DeepSleepModeLeakageμW
CoreSleepModeLeakageμW
0.9V 1.1V TT,85C,0.9V
eHVT eHVT 110 190 0.5 1.5eHVT SVT 180 270 0.5 1.5HVT HVT 110 190 1.5 4.5HVT SVT 180 270 1.5 4.5InquireforEFLX-100TSMC40LPspecs:GDSiscompatible
Name EFLX™-100Core
Technology TSMC40nmULP/LPCMOS
MetalUtilization 5metallayers
NominalSupplyVoltage(V) 0.9V&1.1V
JunctionTemperature(°C) −40to125LeakagePower(μW)forEFLX-100corewitheHVTBitCell
DeepSleepMode0.5μWSleepMode1.5μW(at85°C,0.9V,TT)
16-bitCounterFrequency(MHz) 110–270MHzdependingonVT/Vddchosen(TT,85C,0.9or1.1V)
Area(mm2) 0.13
ClockInputs 1to8
DataI/O(optionalflops) 152inputsand152outputs
LogicCore DSPCoreDual4-inputLUTswith2independentoutputs 120 88
Totalflipflops(exDSP) 544 480
DSPMACs 0 2
EFLXArraySize 1×1to5x5
Design-for-TestSupport Yes
LUTUtilization >90%
AXI/JTAGsoftIP Yes,ifrequested
TSMC40LPCompatibility Yes(inquirefor40LPspecs)
RBBDSP
RBBLogic
RBBLogic
IO
IO
IO IO
RBBLogic
RBBLogic
RBBLogic
IO
IO
IO
IO
TSMC40ULP/LPEFLX™-100Core ProductBrief|December2016 www.flex-logix.compage2
December2016.Copyright2014-2016FlexLogix™Technologies,Inc.EFLXandFlexLogixaretrademarksofFlexLogix™Technologies,Inc.
The EFLX-100 Core comprises of three major blocks: thereconfigurable building blocks (RBBs) of Logic/DSP types, theinterconnectnetwork,andtheuserI/Os.EFLXfeaturesfullconnectivityinside thecore,andprovidesadditional interconnectsat theboundarytoconcatenatemultiplecoresviatheexpandablenetworkI/Os.
TheEFLX-100userI/Oconfigurationisshownbelowleft.TheEFLX-100controlpinsareshowbelowright.
Eachcorehasaninternalpowergrid(VDDHandVSS)whichcanbeconnectedtothecustomer’sdigitalSoCpowergrid.Thecorehaspowercontrolpinsforpower-onandpowergating.ThecoreincludesconfigurationbitswhichareconfigurableviaAXI,JTAGorourcustomserialinterface.Oneachsideofthecore,thereare2inputclocksand2outputclockswhichconcatenateinEFLXarrays.
TheEFLXcoreisavailablenow.Validationinsiliconisinprocessforall10EFLXcorevariationsinTSMC40ULP.InformationisavailableunderNDAtodoextensiveevaluationandchiparchitecturetradeoffs.Contactinfo@flex-logix.com.
EFLX-100
UserClock
UserClock
UserClock
5
Config.(Au
x.)
3
DFT(Au
x.)
PowerCtrl
22
Config.
DFT
2Po
werCtrl
2
UserClock
6Config.
PowerCtrl
DFT3
EFLX-100~438
µmactual= 1output
&1inputs
UserI/Os:60inputpins+60outputpins
UserI/Os:16inpu
tpins+
16outputpins
UserI/Os:60inputpins+60outputpins
= 1outputs&1inputsUs
erI/Os:16inpu
tpins+
16outputpins ~298umactual
DeliverablesandEDADesignViewsFront-endDesignview(withNDA) Back-endDesignViews(withLicense)
EncryptedVerilogModel VerilogModelLIB GDS-IILEF CDL/Spicenetlist
Detaileddatasheet&DSPUser’sGuide IntegrationguidelinesSiliconevaluationreport Integrationassistanceasneeded
EFLXCompilerevaluationversion EFLXCompilerbitstreamgenerationversion Testvectors
RBBRBB
IOB
煑
煑IOB
Interconnects
Expa
ndableNetworkI/Os
UserI/Os
EFLXFPGACore
UserI/Os
