Trends of Programmable Logic Industry and Its Growth in Asia-Pacific PROFIT Dec 22, 2009

Xilinx Confidential – Internal

Fai Yeung

VP APAC Sales & Marketing

Trends of Programmable Logic Industry and Its Growth in Asia-Pacific

PROFITDec 22, 2009

Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx

Common Challenges

Programmable Imperative!

“Differentiate or Die”

Lowest TCOGreen

Accelerated Time to Market

“Fickle MarketDemands Shorter Life Cycle

Spiraling Complexity Capped EngineeringBudgets


The Time for Programmables is Now!

Financial

Constraints

Technology

InnovationMarketForces

Programmable Imperative!Programmable Imperative!


Key Market Trends

Rapid consumer-driven change

Hyper-connectivity

Fickle, fragmented markets

Time-to-market and flexibility: Key attributes for success


Continued Rise of ASIC/ASSP Development Costs

Process Nodes (nm)

Rising costs at advanced process nodes

$5 $10 $14$21

$40

$75$9

$12

$9

$10

$12

$13

$0.1$0.1$1

$3

$6$5

$0

$20

$40

$60

$80

$100

$120

180-nm 130-nm 90-nm 65-nm 45-nm 32-nm

Design Cost Mask Cost Yield Ramp-up

($M) IC Cost by Process Node

$10.1M

$16.1M$24M

$34M

$61M

$100M

Source: Chartered and Synopsys


WW ASIC Design Starts22% Decline in 2009

"More likely, we will see a large percentage of these questionable designs not hit any production and die a slow death by indefinite push-outs”

Bryan Lewis, Gartner Analyst


Tier 1 Semiconductor Company Challenges

Source: GSA

Manufacturing transition: Fabbed Fablite Fabless

Target market rationalization and consolidation

Pursuing ultra high volume applications

300mm Fab Costs:45nm = $3B32nm - $10B


Tier 2 ASSP Vendor Challenges

10

Minim

um M

arket Size ($M

)

$100

$200

$300

$400

$500

Profitability and business model under severe pressure29 /115 companies followed by GSA, have market cap < cash

Narrow Focus to high volume

applications

Process Nodes (nm)

$5 $10 $14$21

$40

$75$9

$12

$9

$10

$12

$13

$0.1$0.1$1

$3

$6$5

$0

$20

$40

$60

$80

$100

$120

180-nm 130-nm 90-nm 65-nm 45-nm 32-nm

Design Cost Mask Cost Yield Ramp-up

($M) IC Cost by Process Node

$10.1M

$16.1M$24M

$34M

$61M

$100M

Source: Chartered and Synopsys


Tier 3 Startup Challenges: Funding has Vanished

Round-A funding (dollar amount) declined 82% from 2000 and 2007

*Through Q308, only 2 chip companies received Round-A funding, totaling $12M

$0

$200

$400

$600

$800

$1,000

2000 2001 2002 2003 2004 2005 2006 2007 2008

0

10

20

30

40

50

60

Funding ($M)

# of Deals

Source: GSA


What FPGA Means to Systems Customers

Do more with less

Reduce risk profile

Focus on core competencies

Avoid big bets on ASIC design starts

Improve engineering productivity

Differentiate or die


FPGA Technology Innovation

Financial

Constraints

MarketForces

CostPowerBandwidthApplication-ready

Technology

Innovation



Introducing Virtex-6 and Spartan-6 FPGA Families

Delivering customer breakthrough performance, power and cost benefits to push programmability beyond the tipping point

40nm/45nm in production CY10Next gen technology coming

Deliver up to 60% lower system cost

Cut power consumption by 65%

Reduce development time by 50%

Achieve over 1Tbps IO bandwidth


The Growing ASIC/ASSP Application GapM

arke

t S

ize

Application Market Segments + 100s More

AS

IC /

AS

SP

Cla

ss A

pp

licat

ion

s

Traditional FPGA Class Applications

UnderservedApplications


0%

20%

40%

60%

80%

100%

2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012

NewGrowth

Xilinx Growth Opportunity Ahead

ASSP

ASIC

Source: iSuppli, March 2008


APAC Growth Trend

Industrial/ScientificMedical

Green IT

Cloud Computing Security Infrastructure

Consumer

Surveillance

3G/LTEWired

Intelligent VideoVideo Analytics


The future of FPGA has never been brighter

Technology causes ASSP development costs continue to rise as it lowers the power and cost of FPGA – Advantage FPGA

No Differentiation with ASSP – Advantage FPGA

Multi- Core is non-deterministic and very difficult to program, FPGA tools are getting faster and easier ( C to Gates) – Advantage FPGA– Multi-Core may drive more FPGA deployment (acceleration and load

leveling) - Advantage FPGA

DSP’s need accelerators and lag the market need – Advantage FPGA



The Time for Programmables is Now!

Important

Urgent Possible


Thank You


Semiconductors Power the Information Revolution

Integrated Circuit by Jack Kilby

Moore’s Law by Gordon Moore

FPGA by Ross Freeman

2009 National Inventors Hall of Fame

FPGA inventorXilinx Co-Founder


Xilinx Historic Revenue

$1,906$1,809$1,872

$1,645$1,586

$1,300

$1,124$1,149

$-

$250

$500

$750

$1,000

$1,250

$1,500

$1,750

$2,000

2001 2002 2003 2004 2005 2006 2007 2008

Calendar Year

$ M

illio

ns


16%7%

46%

31%

Revenue by Geography Revenue by End Market

35%

35%

21%

9%

North America

Europe

Japan Asia Pacific

Consumer& Auto

Communications

DataProcessing

Source: Xilinx, Inc.

Industrial& Other

Xilinx Revenue BreakdownQ3 Calendar Year 2009


25 Years of XilinxGreat assets: foundation for a bright future

Great key customer relationships

Diversified customers and markets

Excellent financial scorecard50%

MarketShare

Cash &Investments

$2B

Operating Cash Flow:

$581MFinancialStability

7%

16%33%

44%

Communications

Industrial and Other

Consumer and Automotive

Data processing

Cisco

Sony

Huawei

HarmanBecker

Trends of Programmable Logic Industry and Its Growth in Asia-Pacific PROFIT Dec 22, 2009

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