Trends and Perspectives in deep-submicron IC design

Bram Nauta

MESA+ Research InstituteUniversity of Twente,

Enschede, The Netherlands

University of Twente IWORID 2002

Outline

• IC Technology trends

• Analog v.s. digital circuits

• How to design circuits in new technologies?

• Conclusion

IC Technology Trends

4004

8086

80286

80386

80486 P5(Pentium)

P6(Pentium Pro)

Pentium IIMerced

Doubling every 1.9 year

2.75 year

Moore’s Law Number of Transistors 80x86 Processors

The ”ITRS" Roadmap

98 2000 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 201299 2001

Advanced research (materials, architecture,..)

180

(nm)

150

130

100

200 300

300

300

300

400450

400450

Volume Production

Integration/Pilot

Basic steps/Modules

Volume Production

Volume Production

Volume Production

Basic steps/Modules 70

50

30

Precompetitive

today

Supply Voltage: Vdd

0.0

0.5

1.0

1.5

2.0

2.5

3.0

250 180 130 90 60 40 30

Technology Node (nm)

Su

pp

ly V

olt

ag

e (

V)

Minimum Maximum

Why Low Voltage?• Low power digital• No breakdown

today 2012

Threshold voltage: VT

Vdd

Vss

Ion Ioff

0 VT VDD

large Ion

small Ioff

ON OFF

Id

Vgs

VT dilemma

• Sub-threshold leakage becomes problem– low Idd during standby & test -> high VT

– fast switching -> low VT

• dual VT

• Triple well (tune VT with voltage)

Transistor speed: cut-off frequencylog [Id/Ig]

Frequencyovgg

mt CC

gf

2

1

ft is about the intrinsic transistor, not interconnectft is a measure for the speed of (analog) circuits

IdIg

0

ft

cut-off frequency

Example 30 nm Devices [Intel]

30 nm physical gate length 0.8 nm conventional SiO2(N)

mass production in 2009

Interconnect: > 6 metal layers

[Intel]

Transistor gate length 70 nm Metal-1 width 180 nm

Analog v.s. Digital Circuits

Power dissipation for analog processing

C

Vdd

0V t

Vsignal

Vpp

1/f

Idd

Vsignal

[vittoz]

N

SfTk

V

VP

pp

dd ....8min

[Vittoz, ISCAS 1990]

independent of technology

Power dissipation for digital processing

•1 bit extra -> 6dB more S/N

•operations/sec ~ n2. fsig

t

Vsignal

2n

1/f

P 300 fsig

10 SN-------

è øç ÷æ ö

log 1.76–

6-----------------------------------------------------------

è øç ÷ç ÷ç ÷ç ÷ç ÷æ ö2

Etr =

S/N in dB

depends on technology

[Vittoz, ISCAS 1990]

Energy per transition:

2

2

1ddwiretr VCE

Vdd

Idd

Cwire

Etr=10pJ for 4um 5V CMOSEtr=1pJ for 1um 3V CMOS (1990)Etr=0.1pJ for 0.18um 1.8V CMOS (2000)????? ????? (2020)

downscaling lowers digital dissipation

Signal/Noise [dB]

Pow

er d

issi

patio

n

analog

digital

IC Technology scaling

• Optimized for digital – digital = main chip area

– minimize Etr

– minimize cost per transistor

• Analog “has to live with this”– It cannot die

How to design circuits in new technologies?

Analog

• High voltage options for I/O & EEPROM– “old” transistors available in new technology

• Use the low VT – needed for digital speed anyway

• “non ideal” device behavior – gate leakage, non square law, – no real problem, better models needed

• Nominal Vdd drops – no stacking

psrr, cmrr, noise

Change analog circuits

Vdd=Vgs + Vds

Analog

• matching of MOSFETS– becomes better for same W.L

– new technology: VT drops linear with Vdd

• 1/f noise– tends to increase for minimum size MOS

f

N

ft ft ft

1/f noise Reduction: switched bias technique

Constant Bias

n-MOSFET

VON

VT

What about the Low-Frequency noise ?

VOFF

Switched Bias [Periodically switching the MOSFET “off”]

LF noise spectrum(constant DC gate bias)

Expected noise spectrum of switched bias [6 dB below] (for 50% duty cycle)

Nois

e P

ow

er(

dB

)

Frequency(log scale)Switching frequency

Measured noise spectrum of switched bias [>>6dB below](for 50% duty cycle)

1/f noise Reduction: switched bias technique

analog RF: passives components

• Inductors– many metal layers + high ohmic substrate – high Q possible

top view

analog RF: passives components

• C: use fringe caps!

cross section view

Switched opamp technique

Vsig+Vgs > Vdd

Vsig Vsig

Vgs

[Peluso, JSSC, july 97]

Vdd Vdd

Analog: strategy• Exploit the speed:

– feedback @ high frequencies– noise canceling– dynamic element matching– sigma delta AD converters @ high frequencies

• Use digital for analog– always digital on the chip– use this for: calibration, digital filtering

Digital

• transistor switching speed = no issue

• low voltage but still too high power !!!

• leakage -> dual VT

– but which VT where?

• how to manage complexity? – 100M transistors

• interconnect is speed bottleneck

interconnect 1980

substrate

interconnect 1995

substrate

interconnect 2005

substrate

Digital / interconnect

• bottleneck = wires– repeaters, synchronizers– globally asynchronous &

locally synchronous

• use analog for digital– 3D microwave techniques – “nano modems” ( more than just 1 and 0)

High-voltage digital I/O

• “high voltage” by design:

5.5V I/O in 2.5V technology ! [Annema, JSSSC,March 2001]

substrate bounce

substrate

Lbondwire

ground

Vdd

substrate bounce

substrate

Lbondwire

ground

Vdd

substrate bounce

substrate

Lbondwire

ground

Vdd

substrate bounce

• Even 100% digital chip has problems

• Decouple supply in digital ( 30% area!)– locally!

• Use package with low inductance

• Make very robust analog designs

Conclusion

conclusions

• Technology scaling > 10 years

• Scaling of analog and digital circuits fundamentally different

• problems can be solved by design

• Digital for analog and analog for digital