Towards wafer-scale monolithic CMOS integrated pixel ... · Vienna Conference on Instrumentation,...

Towards wafer-scale monolithic CMOS integrated pixel detectors for X-ray photon counting

G-ray Medical, Switzerland

Jorge Neves

Outlook

• New semiconductor process technology for monolithic CMOS pixel detectors

• Low-temperature covalent wafer bonding

• Detector development

• Specifications

• Pixel architecture/ block diagram

• Readout system

• Detector commissioning

• Detector characterization: preliminary results

• Ongoing developments

Vienna Conference on Instrumentation, 18-22 Feb 2019 ©2019 G-RAY MEDICAL – Jorge Neves 2

• Low-temperature covalent wafer bonding

• Realized at a 200 mm wafer scale

• Absorber materials• Si, GaAs, CdTe, epitaxial SiGe

• Advantages• CMOS compatible

• X-ray direct conversion

• Photon counting capability

• Large-area detectors

• No bump bonding

• Applications• Scientific, industrial, medical

New semiconductor process technology for monolithic CMOS pixel detectors

Concept of a backside illuminated detector with p-njunction at bonded interface between thinned CMOSreadout wafer and absorber wafer.

PCT Application number: IB2015/002385 | Inventor: Hans von KänelApplicant: G-ray Switzerland SATitle: Monolithic CMOS integrated pixel detector, and systems and methods for particle detection and imaging including various applications

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Low-temperature covalent wafer bonding

Standard surface activation involves dry etching for oxide removal. Consequences: Surface amorphization Poor electrical properties

G-ray modified processSputtering for surface cleaning replaced by HF-dip and soft ion bombardment for hydrogen removal

G-Ray

Hydrogen

removal

G-Ray

Hydrogen

removal

Wet chemical pre-

treatment

Post annealing &

post-Bond Metrology

• IR-and C-SAM measurements

• HRTEM-Analysis• EDX-analysis• I-V characterization

high vacuum (1x10-8mbar)


Covalent wafer bonding

• Unique modified EVG 580 ComBond® system

• Enhanced plasma module for atomic-scale wafer surface cleaning

Top wafer - Si

Bottom wafer - Si

Electrical conductivity across bonded Si-Si interfaces:Evolution towards ohmic behaviour through mild annealing at CMOS compatible temperatures

Bo

nd

ing

stre

ngt

h >

1.3

J/m

2

Oxi

de-

free

bo

nd

ing

inte

rfac

e


Detector development

Date CMOS chip Active area Pixel size # Pixels Purpose Detector series

Q3-2017 Novipix 1.6 x 1.6 mm2 100 µm2 256 Proof-of-concept: CMOS pixel architecture

-

Q4-2018 BigNovipix 2.4 x 3.0 cm2 100 µm2 72‘000 Proof-of-concept: Large-area wafer bonded detector

latenium™ Evaluation kit (L & H)

Q4-2019 XENIA 5.0 x 5.0 cm2 50 µm2 1‘000‘000 Commercial product latenium™ L1 & H1 series

Novipix CMOS: 16 x 16 pixels, 100 µm pitch BigNovipix CMOS: 240 x 300 pixels, 100 µm pitch


Detector specifications

• 2.4 x 3.0 cm2 active area

• 100 µm pixel pitch

• 240 x 300 pixel array: 72’000 pixels

• Dark current compensation: up to 1µA / pixel

• 2 discriminators with 12-bit counters per pixel

• Parallel 12-bit interface for data readout

• Programmable region-of-interest for readout

• Sequential acquisition/ readout with 2 thresholds

or continuous mode with 1 threshold

• 1.8V single power supply

• 587 wire bond pads


• LFoundry 150 nm CMOS process

• Starting material: n-type wafer, 1 kΩcm

• Retrograde p-well to emulate standard wafer doping at surface

• Deep N-WELL implant for charge collection

• X,Y = 22 µm, gap = 2.5 µm

• Reticle size chip 2.6 x 3.2 cm2

• Dedicated 8 inch full mask

• CMOS chip tape-out: Q1 2018

Detector specifications


Pixel architecture/ block diagram

• Programmable charge amplifier sensitivity : 8/13 µV/e-

• Leakage current compensation up to 1 µA

• Programmable shaping time: 40/70 ns

• 6-bit in-pixel DAC for threshold calibration

• Binary counter instead of grey counter


Readout systemFunctional overview


TE-0

72

0

Readout systemSoftware/ hardware partitioning

Xilinx Zynq®-7000 SoC


Readout system Experimental test setup at G-ray


CMOS wafer pre/ post-processing

• Planarization of CMOS stack

• Oxide-to-oxide bonding of CMOS stack to a carrier wafer

• Back thinning CMOS wafer

• Clean surface preparation and low-temperature covalent bonding of CMOS wafer to sensor wafer

• Removal of carrier wafer

• Pad access on front side

• Backside metallization: central pads/ guard rings

• Wafer dicing

• PCB die attach, wire bonding, encapsulation

Detector Commissioning

In real life, it's not that easy !

Al backside metallization

1 mm

450 µm

100 µm


Detector CommissioningWire bonding


Detector characterization

Analog/ digital output with injected test pulses

• Programmable charge amplifier sensitivity : 8 / 13 µV/e-

• Programmable Shaping time: 40 / 70 ns


Detector characterizationu

nca

libra

ted

ca

libra

ted

odd columns stimulated no stimulation

Discriminators threshold calibration• Calibration done row by row or for all the pixel array in simultaneous• 6-bit in-pixel DAC

Row 1 Threshold scan: S-curves

3000 injected pulses


CMOS (7.3 µm)

glued substrate

Si 16 µm 1 kΩcm

Si 400 µm > 5 kΩcm

Bonding interface

Detector characterization

Bonding interface - scanning electron microscopy (SEM) images


X-ray Detector characterization

• Microfocus X-ray tube (from VISCOM), XT9160 TXD

@ Empa Dübendorf – Center for X-ray Analytics

• W anode, 20-140 kVp, 1µm focal spot size, cone beam

• Uniform X-ray illumination @ 40kV, 180uA

• Flood image: 20 sec exposure

595 pixels (0.83%)89 pixels (0.13%)



Pb-phantom with diverging lines: 5 lines/mm resolved



Other contrast patterns

Aluminum object with holes and variable thickness

Set of overlapping aluminum plates

?

?


• Front-end amplifier Gain, Noise, Sensitivity, Dynamic Range, Linearity (analog output)

• Depletion voltage (absorber), High-Voltage leakage

• Quantum Efficiency (DQE)

• Energy Calibration/ Energy resolution

• Pixel Threshold Scans (S-curves)

• Threshold Calibration, fine-tuning

• Count Rate Performance: frame rate, readout dead time, minimum exposure time

• Spatial Resolution (PSF, LSF, spatial distortions)

• Contrast Tranfer Function (CTF)

• Modulation Transfer Function (MTF)

• Normalization correction (flat-field correction algoritm)

• Cross-talk, charge sharing (fluorescence)

• Temperature dependence

• etc ...

Detector characterization – ongoing !


Outlook: Ongoing developments

Scaling Hetero-Epitaxy from Layers to Three-Dimensional CrystalsH. von Känel, et al., Science 335, 1330 (2012)

• Pixelated SiGe absorber with potential for super resolution• Epitaxial SiGe crystals on Si pillars• Space-filling but isolated SiGe crystals


Summary

• New semiconductor process technology for low-temperature covalent wafer bonding.

• CMOS compatible process for monolithic integrated pixel detectors.

• Demonstrated for Si-Si wafer bonding, and being exploited for GaAs, epitaxial SiGe, CdTe.

• Large-area monolithic CMOS pixel detector demonstrator successfully developed .

• X-ray detector characterization ongoing.

• Epitaxial SiGe growth ongoing.


Acknowledgements

• Pierre-François Rüedi

• Riccardo Quaglia

• Armin Klumpp

• Andreas Drost

• Philippe Pasquet

• André Rubbia

• Sebastien Murphy

• Johannes Wüthrich

• Marco Hagting

• Harry van Essen

• Robert Zboray

• Thomas Luethi

• Antonia Neels

• Yadira Arroyo

• Adolfo Fucci

• Alberto Lucci

• Abigail Vouillamoz

• Andy Roselli

• Hans von Känel

• Manolis Choumas

• Nasser Rasek

• Naomi Vouillamoz

• Patrick Scherrer

• Philippe le Corre

• Franco Bressan

• Zoltan Cziegler


Coming soon! Order today your

Contact: [email protected]

latenium™ Evaluation kit !


mailto:[email protected]

Visit us: http://www.g-ray.ch

Contact us:

G-ray Switzerland Rouges-Terres 61CH-2068 Hauterive (NE)SWITZERLAND

[email protected]

Thank you !

http://www.g-ray.ch/

mailto:[email protected]

Towards wafer-scale monolithic CMOS integrated pixel ... · Vienna Conference on Instrumentation,...

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