Toshiba VCR Training M-653

8/13/2019 Toshiba VCR Training M-653

1/31

TOSHIBA AMERICA CONSUMER PRODUCTS, INC.

NATIONAL SERVICE DIVISION

TRAINING DEPARTMENT

1420-B TOSHIBA DRIVE

LEBANON, TENNESSEE 37087

PHONE: (615) 449-2360

FAX: (615) 444-7520www.toshiba.com/tacp

VIDEO CASSETTE

RECORDER

TECHNICAL TRAINING MANUAL

M-653

NTDVCR06

1997

ELECTRICAL


2/31

CONTENTS

1. POWER SUPPLY CIRCUIT ................................................... 1-1

1-1. Outline ............................................................................. 1-1

1-2. Circuit Operation .............................................................. 1-11-2-1. Input Filter Circuit .................................................... 1-11-2-2. Primary Side Rectifier and Smoothing Circuit ......... 1-11-2-3. Switching Circuit ..................................................... 1-2

1-2-4. Current Limiter Circuit ............................................. 1-21-2-5. Snubber Circuit ....................................................... 1-21-2-6. Voltage Control Circuit ............................................ 1-31-2-7. Secondary Rectifier Circuit ..................................... 1-31-2-8. ON/OFF 9V Circuit.................................................. 1-41-2-9. EVER 5V ................................................................. 1-41-2-10. ON/OFF 5V Circuit ................................................ 1-4

2. KEY DISPLAY CIRCUIT ........................................................ 2-1

2-1. Microcontroller Unit .......................................................... 2-1

2-2. Display Unit ...................................................................... 2-22-3. Key Matrix Unit ................................................................. 2-2

2-4. Infrared-Red Receiver Unit .............................................. 2-2

2-5. Interface Unit .................................................................... 2-2

2-6. Resonator Circuitry .......................................................... 2-2

2-7. Reset Circuitry ................................................................. 2-2

3. SERVO CIRCUIT ................................................................... 3-1

3-1. Cylinder Servo Circuit ...................................................... 3-13-1-1. Cylinder Rotation Detection Signal (FG/PG) ........... 3-13-1-2. SW Pulse Generation Circuit .................................. 3-13-1-3. Phase Detection Control (APC) and

Speed Detection Control (AFC) .............................. 3-2

3-1-4. Cylinder Control Output Circuit ............................... 3-23-1-5. fH Correction Circuit................................................ 3-23-1-6. Pseudo V Output Circuit .......................................... 3-23-1-7. Motor Drive System ................................................ 3-2

3-2. Capstan Servo Circuit ...................................................... 3-33-2-1. FG Pulse Generation/FG Amplifier/

FG Schmidt Circuit .................................................. 3-3

3-2-2. CTL Signal Recording ............................................. 3-33-2-3. Phase Detection Control (APC) and

Speed Detection Control (AFC) .............................. 3-33-2-4. Capstan Control Output Circuit ............................... 3-33-2-5. SP/LP/SLP Mode and Video System Detection ...... 3-43-2-6. Edit Recording ........................................................ 3-4

3-3. CAM Logic ....................................................................... 3-4

3-4. Viss Function ................................................................... 3-53-4-1. Operation of Analog Amplifier in lC501(TMP90CN72EDF).................................................. 3-5

4. LOGIC CIRCUIT .................................................................... 4-1

4-1. System Control ................................................................ 4-1

5. PIF CHANNEL SECTION CIRCUIT ...................................... 5-1

5-1. Outline ............................................................................. 5-1

5-2. Antenna Input Output Circuit ............................................ 5-2

5-3. Tuner, Channel Selection Circuit ...................................... 5-25-3-1. Channel Selecting Operations ................................. 5-25-3-2. Frequency Synthesizer Circuit ................................ 5-3

5-4. PIF Circuit ........................................................................ 5-35-4-1. PLL Complete Sync Detection System ................... 5-3

5-5. MTS (Multi-channel TV Sound) Detector .......................... 5-4

5-5-1. Outline .................................................................... 5-45-5-2. Operation ................................................................ 5-4

6. VIDEO CIRCUIT .................................................................... 6-1

6-1. Outline ............................................................................. 6-16-1-1. Background ............................................................. 6-1

6-2. Signal Flow ...................................................................... 6-16-2-1. EE Mode ................................................................. 6-16-2-2. Y Signal Record Path .............................................. 6-16-2-3. Color Signal Record Path ........................................ 6-2

6-2-4. Y Signal Playback Path ........................................... 6-36-2-5. Color Signal Playback Path ..................................... 6-4

6-3. Control Signal for Head Signal Amplifier .......................... 6-4

7. AUDIO CIRCUIT .................................................................... 7-1

7-1. Hi-Fi Audio Circuit ............................................................ 7-17-1-1. Outline of Hi-Fi Audio Circuit ................................... 7-17-1-2. EE Mode ................................................................. 7-17-1-3. Recording Circuit .................................................... 7-27-1-4. Playback Circuit ...................................................... 7-3

7-1-5. Dropout Correction Circuit ....................................... 7-3

7-2. Conventional Audio Circuit ............................................... 7-47-2-1. EE Mode ................................................................. 7-47-2-2. Record Circuit ......................................................... 7-4

7-2-3. Playback Circuit ...................................................... 7-4


3/31

1 1

1. POWER SUPPLY CIRCUIT1-1. OutlineThe power supply circuits adopts a switching power

supply circuit of RCC self-excited type. Main key

components include a 10 pins transformer and a

switching transistors (BUL26XI/ 2SC4907), the

secondary side has three rectifier circuits and output

lines for KDB supply. In addition, it is stabilized by aseries of regulator which are enough power to be

supplied to each circuit.

The block diagram is shown in Fig. 1-1-1.

Fig. 1-2-1 Fig. 1-2-2

Fig. 1-1-1

1-2. Circuit Operation

1-2-1. Input Filter CircuitThe input filter circuit consists of four capacitors and a

line filter (T801) as shown in Fig. 1-2-1, and the noise

input/output from the AC cord is suppressed.

1-2-2. Primary Side Rectifier and SmoothingCircuit

The primary side rectifier and smoothing circuit rectify

the output from the input filter circuit with diodes D802

D805, and supply DC voltage approximate 320V to

the switching circuit after smoothing with the capacitor

C805.

MainFuse

Voltage in

MainFilter Bridge diode

SwitchModeTransformer

SwitchingTransistor

Snubber Circuit

RectifierSmoothing

ControlCircuit

Feedback Loop

RectifierSmoothing

RectifierSmoothing

OutputSupplyVoltage

F801

C801

T801

C804

C802

C803

D802

C805+

D804

D803D805

Approx. 320V


4/31

1 2

1-2-3. Switching CircuitThe switching circuit is configured as shown in Fig. 1-

2-3. When AC power turns on, the start-up current

flows to the base of Q801 through R802, and Q801

turns ON. And then the collector current flows to

Q801 through the winding LPof T802.

The electromotive force generated in the LNof T802 by

the current flow in the winding LPflows the drivecurrent on the base of Q801 through D807 and R804,

thereby the positive feedback is applied to Q801 and

Q801 turns ON quickly. The collector current soon

saturates and becomes constant. At this time, the

electromotive force of the winding LNdisappears and

the counter electromotive force generates, and then

Q801 turns OFF after the base of Q801 becomes reverse

bias through R804 and C807. This operation is

repeated.

Fig. 1-2-3

1-2-4. Current Limiter CircuitThe current limiter circuit protects Q801 by detecting

the emitter current of Q801 by R810, adding it to the

base of Q803, and limiting operation by decreasing

base voltage of Q801, when the power plug is

inserted to an AC outlet.

1-2-5. Snubber CircuitThe snubber circuit is shown in Fig. 1-2-4. The A

portion of the waveform is suppressed as shown in Fig.

1-2-5.

The A portion is suppressed by D806 turning ON and

charging to C806, and it discharges from C806 passing

through R803.

L801 and C812 are for absorbing the switching noise of

D806.

Fig. 1-2-4

Fig. 1-2-5

R810

DC in

C809

R809 R808

C808

Q803 Q802

LN

LP

D807

C807R804Q801

R802

T802

PrimaryGND

Feedback

DC in

D806

C806

T802

C812

L801

R803

Q801

Q801Collector voltage

A


5/31

1 3

1-2-6. Voltage Control CircuitThe voltage control circuit is shown in Fig. 1-2-6. It

stabilizes the secondary side output 5.6V.

Assuming that 5.6V output increases, also the voltage

increases since the voltage divided into R821 and R822

is applied to the base of Q825, and then diode of Q804

turns ON and the transistor of Q804 turns ON since VBE

of Q825 becomes higher. And ICflows through R806and turns ON Q802.

Q801 turns OFF, and the output voltage which is

increased by cutting the output is reduced since the base

current of Q801 is cut off when Q802 turns ON.

C808, C810, R807, and R808 are for the phase correc-

tion.

Fig. 1-2-7

Another rectifier circuits also produce DC voltage by

rectifying with diodes and smoothing with capacitors.

Fig. 1-2-6

1-2-7. Secondary Rectifier CircuitThe secondary side rectification and smoothing circuits

are provided and each supplies a DC voltage of 4.6V,

EVER 37V, 26V (Vkk), & EVER 14V respectively.

5.6V

DC in

T802

Q801

Q804

Q825

Q802

C823+

+

R810

R808

C808 R807

R804

D807

R806

C810

C828 D831 R822

R821

R824

D822

14V

R823

+

+

+

RF825

RF828

RF826

T802

D825

D827

D826

C822

C825

C827

C826

F (+)

F ( )

EVER + 37V

26VKK


6/31

1 4

1-2-8. ON/OFF 9V CircuitThe ON/OFF 9V circuit is shown in Fig. 1-2-8. It turns

ON with LOW when the power ON/OFF signal from

the microcomputer is supplied to Q842.

When the POWER ON/OFF signal is HIGH, the 9V

voltage is not output since Q842 turns ON and Q841

turns OFF due to the base of Q841 is 0V.

Fig. 1-2-8

1-2-9. EVER 5VThe EVER 5V is shown in Fig. 1-2-9. The base bias is

applied to Q844 from EVER 14V and then the output

EVER 5V.

1-2-10. ON/OFF 5V CircuitThe ON/OFF 5V circuit is shown in Fig. 1-2-10. The

base bias is applied to Q843 when the ON/OFF 9V

started up, and then the ON/OFF 5V is output.

Fig. 1-2-9

DC 14V ON/OFF

9V

Q842

POWERON/OFFSIGNAL

37V

R842 R841

+C842

Q841

D841

D842

DC 5.6V ON/OFF

5V

ON/OFF9V

R844

+C844

Q843

D843

D844

5.6VEVER 5V

EVER 14V

R845

Q844

D845

Fig. 1-2-10


7/31

2 1

2. KEY DISPLAY CIRCUITThe basic functional units of the Key Display Circuit

(thereafter shall be called KDB) comprise of a

microcomputer, display unit, key matrix unit, infrared

receiver unit and interface unit. Other supportive

circuitries are resonator circuitry and reset circuitry.

The KDB circuit reads key input data from tact-switches

on the VCR and the KDB microcomputer (also

referenced as display microcomputer) serially transfers

these data to the Main microcomputer (which is also

known as servo/logic microcomputer). Input data sent

from the remote controller is received by the remote

sensor and directly processed by the Main

microcomputer. The fluorescent display tube isemployed to display information on time, timer

recording, channel selection, etc.

The microcomputer itself contains CPU core, ROM,

RAM, input/output ports, vacuum fluorescent tube driver

circuit (24 bit), 4-bit A/D conversion input (4 channel)

and serial interface with 8-bit buffer. It is running at a

speed of 8 MHz, which means it has an instruction

execution time of 1.0 s. Its supply voltage can be

anything between 4.5 V to 5.5V.

2-1. MicrocomputerTMP47C416F is a CMOS 4-bit single chip microcom-

puter.

It has a ROM size of 4k x 8bit and RAM area of 256 x

4bit. It comes with 44 pins and in plastic flat package

(QFP).

Table 2-1-1 Display microcomputer

MICROCOMPUTER ROM RAM PACKAGE

TMP47C416F-H877 4096 x 8 bit 256 x 4 bit QFP44

Fig. 2-1-1 Block diagram

EEPROMST24C02B1

Tuner

TMLH2X006A

MTSPC1852

Hi-Fi ICTA1246F

TMP90CS74DF-6621

Main Microcomputer(60k MASK)

IR Receiver

pin (12)KEYIN 4

pin (11)KEYIN 3

pin (10)KEYIN 2

pin (9)KEYIN 1

CH UP

REC

CH DOWN

POWER

STOP REW

PLAY

EJECT FF

TEST 2 TEST 1

Key MatrixSimultaneous approved key

TMP47C416F-H877

Display Microcomputer(4k MASK)

Universal VFD

SIO

A/D CONVERSION PWM

IIC


8/31

2 2

2-2. Display UnitThe display tube (here onwards will also be known as

VFD for Vacuum Fluorescent Display) employs a

dynamic drive system which sequentially lights up each

digit by using grid pulse and segment pulse signals sent

from the display microcomputer. The VFD is a vacuum

fluorescent tube and of triode type. Its operation is

based on negative power supply. The filament voltagesF (+) and F (-) are supplied by the power circuit to drive

the fluorescent display.

2-3. Key Matrix UnitThe display microcomputer has 4 channels of 4-bit A/D

conversion input (KEYIN1, KEYIN2, KEYIN3 and

KEYIN4) and these are formed into key matrix to be

used for VCR key inputs. The display microcomputer

then scans in operating key and for each read in key, it is

compared and decoded data is sent to main system via

serial transmission.

2-4. Infrared Receiver UnitThe infrared receiver includes a photodiode which

detects infrared radiation from remote controller with a

carrier frequency of 38 kHz. The demodulated infrared

signal received is then decoded by the servo

microcomputer and when the remote control code is

identified, the function associated is processed.

2-5. Interface UnitTwo microcomputers are used in the VCR and data

communications between them (Main and KDB micro-

computers) are carried out through serial transmission.

Serial data input from Main microcomputer to KDB

microcomputer and serial data out from KDB microcom-

puter to Main microcomputer are pins SIO. M_D and

SIO. D_M respectively. These data are transferred

according to the serial clock (SIO. CLOCK) and strobe

(SIO. STROBE) pins.

2-6. Resonator CircuitryAlthough the display microcomputer is capable of

operating in dual clock mode, only high-frequency

oscillation circuit is implemented in the VCR application.

The system clock is obtained from the high-frequency

clock and is generated by the 8 MHz ceramic resonator

(XX 01).

2-7. Reset CircuitryWhen a logic low signal is sent (via pin 55 of Main

microcomputer IC501) to the RC circuit, an active low

reset pulse is generated and applied to the display

microcomputer. Once the logic signal goes high, the

reset operation is released and the internal state is

initialized. The display microcomputer then starts

executing its instruction stored in the ROM area.

Fig. 2-5-1 KDB-MAIN microcomputers interface

SIO.STROBE

24

23

25

26

SIO.M_D

SIO.D_M

SIO.CLOCK

96

54

97

95

ICX01

KDB microcomputer

IC501MAIN microcomputer


9/31

3 1

3. SERVO CIRCUITThe servo circuit controls the cylinder motor and the

capstan motor. Control systems performing a central

role and used in a conventional servo IC are incorpo-

rated in a single servo-microcomputer. The motor

controls are processed via software programmed into

its on-chip 40K ROM.

The one chip microcomputer (IC501,TMP90CN72EDF-6621) used in the system control

has a role to switch the mechanism and electronic

circuits to operation modes and to monitor the

operation status of the mechanism in each mode.

Since these operations must be made in synchroniza-

tion with the cylinder motor and the capstan motor in

many cases, the operations are closely related to the

servo ICs. The servo microcomputer integrates the

servo control functions and the system control

functions into a chip and the operations can be

processed with software inside the chip and it features

as follows. Higher control accuracy flexibly applicable to

transient response.

Automatic adjustments for various circuits.

Reduction of external circuit components.

Each circuit configuration in terms of function will be

given in Table 3-1-1.

Table 3-1-1 Configuration of servo circuit

(Head assembly)

Fig. 3-1-1 shows the head mounting locations on the

cylinder. As can be seen from the illustration, two

video heads are mounted on the cylinder. Moreover,

Hi-Fi audio heads are mounted in addition to the

video heads and the phase is 60 from the video head

center.

3-1. Cylinder Servo Circuit

3-1-1. Cylinder Rotation Detection Signal (FG/PG)In a conventional system, a rotation speed detection signal

(FG pulse) and a rotation phase detection signal (PG

pulse) are separately detected. But in the newly devel-

oped cylinder motor, the rotation phase detection signal is

superimposed on the rotation speed detection signal,

thereby detecting both the speed and phase in one line.A hall element (Z662) detects variations of magnetism

varied by rotation of the magnets mounted at outside of

the cylinder motor rotor. This variation is translated into

an amplified voltage and waveform shaped by an ampli-

fier inside the cylinder driver IC (IC503, TB6515AP).

The processed signal (pulses) is fed back via pin 1 of the

driver IC.

As can be seen from Fig. 3-1-2, the rotation detection

signal consists of 1REF + 8FG pulses per one rotation,

and the REF is used to detect the rotation phase and 8FG

rotation speed. The sampling frequency in the speed

system is:

30Hz x 8FG = 240Hz

When the servo is locked (30Hz).

3-1-2. SW Pulse Generation CircuitThe cyilnder rotation detection signal enters pin 47 of

IC501, servo microcomputer. Inside IC501, the REF

signal is detected and the SW pulse is created at a position

delayed by the PG-adjusted data from rising edge of next

FG. PG-adjusted data is obtained through PG adjustment

where C-sync from pin 70 of IC501 is used as reference

signal. The video SW pulse is necessary for all VCR, andHiFi SW is needed for reading of HiFi track. The relation

of the SW pulses is shown in Fig. 3-1-2.

SB

SA

CH1 CH2

Direction of rotation

Rotor REF phase

(OnlyHiFim

odels)

60

NOITCNUF TIUCRIC

ovreSrednilyC

tupniGP/GF

tuptuolortnocMWP

ylppusrewoprotoM

ovreSnatspaC

gnipahsmrofevawGF

gnipahsmrofevaweslupTLC

tuptuolortnocMWP

ylppusrewoprotoM

noitarenegegatlovecnerefeR

rehtO noitcetedlangisgnikcartotuA

Fig. 3-1-1 Head assembly (Top view)


10/31

3 2

Fig. 3-1-2 SW pulse timing chart

3-1-3. Phase Detection Control (APC) andSpeed Detection Control (AFC)

Both the phase and speed detection are carried out

inside the servo microcomputer IC501. In the

phase detection, the REF signal entering into pin

47 is compared with the reference signal in their

phases. In the record mode, a V sync signal

extracted from the video signal and divided into a

half is used as the reference signal. In the playback

mode, an internal reference signal (30Hz) devel-

oped from the microcomputer clock (16 MHz) is

used as the reference signal. This is the only

difference in the record and playback modes in the

cylinder servo. In the speed detection, speedvariations are detected at a sampling rate of 8FGs

(240Hz) per one rotation.

3-1-4. Cylinder Control Output CircuitResultant voltage from the phase detection and the

speed detection passes through comb filters, AFC

and APC mixing filter, DC correction filter and

outputs as a PWM (Pulse Width Modulation) square

pulse of about 42 kHz at pin 100 of IC501. The

signal is output at about 50% duty under the servo

locked stably.The PWM output passes through a PWM carrier

(About 42 kHz), smoothing filter (R519, C529, R520,

C530) and enters pin 11 of IC503. The voltage is

compared with a reference signal inside the IC and

used to control the motor. That is, when the PWM

output of H period is long, the motor is accelerated

and decelerated when short. In the stop status, the

output develops L.

Video SWPulse

Video SWPulse 6.5H

1REV

PG DELAY

REF 1 2 3 4 5 6 7 8 REF

Video signalP920

C.SYNCIC501 pin70

VIDEO SW PulseP506 pin3orIC501 pin89

PG/FG Pulse

IC503 pin1orIC501 pin47

HiFi SW PulseIC501 pin91

CH1 CH2

SA SBSB

CH2

3-1-5. fH Correction CircuitSince a tape runs rapidly under the cue/review mode, it

is necessary to adjust rotation speed of the cylinder

corresponding to the tape speed to maintain the relative

speed between the cylinder and the tape. IC501

automatically adjusts the cylinder speed according to

the tape speed under cue/review mode to make the fH

correction.

3-1-6. Pseudo V Output CircuitTo prevent V sync disturbance on the screen under

special playback modes, a pseudo V signal is

superimposed on the video signal. In this case, a phasecontrol signal for these signals is output as a 3 state

value signal at pin 76 of IC501, servo microcomputer.

This signal is in synchronization with the SW pulse of

the video heads and H output for the pseudo V insertion

period. In a superimposing period, the signal shows L

level. These signals are always sent to the video circuit

and control the video signals.

3-1-7. Motor Drive SystemIn a conventional cylinder motor, three hall elements

detect phases of the rotator magnets and a coil to be

powered is determined by identifying input status of

three hall elements. In the motor employed this time,

voltages are applied to three phase coils as a

synchronous motor at a starting period, and when the

motor is started once, a single hall sensor detects the

varying magnetic field due to the motion of the cylinder

rotor. A drive switching signal is thus developed and the

phase switching is carried out by a counter present

inside the IC. Moreover, PG/FG signals are developed

inside the IC by using the signal detected by the hall

element, thus working as conventional type pattern FG

and PG coils.


11/31

3 3

3-2. Capstan Servo Circuit

3-2-1. FG Pulse Generation/FG Amplifier/FGSchmidt Circuit

The FG pulse is a signal always obtained from the

capstan motor as a speed feedback signal for the

capstan. The FG pulse is obtained by detecting

magnetism developed outside the rotor using reluc-

tance elements. That is, FGA and FGB separated by90 in phase are obtained. From this 2 phase shifted

FG, a reverse rotation of the motor can be detected.

They are also used in the intermittent slow operation,

repeating the start and stop.

The FGA pulse is used for the speed detection of the

capstan, auto braking in the slow mode, and the tape

remain detection. The FGA first enters the servo

circuit through pin 6 of P502 and amplified in the

amplifier of pins 40-42 of IC50l, waveform shaped

inside IC50l, and used as a speed feedback signal.

On the other hand, the FGB pulse enters the servo

circuit through pin 4 of P502, amplified in the

amplifier at pins 42-44 of IC501, and waveform

shaped inside IC501. The FGB is used for detecting

auto braking in the slow mode.

The braking control is carried out by detecting phases

of the FGA and FGB pulses inside IC501. The

number of FG pulse is 360 per one rotation of the

motor, and the frequency is about 1079 Hz in SP

mode, 360 Hz in SLP mode when the servo is lockedunder normal playback mode and record mode.

3-2-2. CTL Signal RecordingIn the record mode, a 30 Hz CTL signal is created

from a composite sync signal entering pin 70 of

IC501 main microcomputer and a REC CTL signal is

developed at pin 33. The duty of CTL signal is 60%

in the H period. This signal flows into the CTL head

and recorded on the CTL track of the video tape in a

saturated level. The phase of the CTL signal record-

ing (amount of ACE Head position shift) is set to:

25.36ms from CH1 (the rising edge of SW pulse)

in SP mode.

21.42ms from CH1 (the falling edge of SW pulse)

in SLP mode.

3-2-3. Phase Detection Control (APC) and SpeedDetection Control (AFC)

The phase detection and speed detection are carried out

inside the servo microcomputer IC501. In the record

phase detection, a 30 Hz signal obtained by dividing the

FG signal entering pin 41 (amplified/waveform shaped

inside IC501) is compared with a phase of the REF signal

synchronized with 30Hz signal (obtained by dividing theV sync extracted from the video signal). On the other

hand, in playback phase detection, a CTL signal entering

pin 33 is amplified/waveform shaped inside IC501, and

then compared with a phase of the reference signal

obtained by tracking-delaying the REF signal.

For speed detection, the FG signal entering pin 41 of

IC501 is amplified/waveform shaped inside IC501 and

then compared in the speed detection circuit.

In the capstan which differs in that the target speed

varies considerably depending on operation modes andthe wide dynamic range, speed detection and phase

detection are carried out by dividing the FG and CTL in

the search mode.

3-2-4. Capstan Control Output CircuitResultant outputs in the phase detection and speed

detection enter the microcomputer, pass through comb

filters, AFC+APC mixing filter, DC correction filter and

correct in gain. Thus processed signal is used as a PWM

(Pulse Width Modulated) rectangular waveform signal at

pin 99 of IC501. With the servo stably locked, theoutput pin 99 develops the PWM output at a duty of 50%.

The PWM output passes through a smoothing filter circuit

(R514, C523, R515, C524) and enters the capstan unit

through pin 9 of P502 with the reference signal at pin 5 of

P502, and compared inside the drive IC, thus controlling

the motor. When the H period is long at the PWM output

terminal, the control is carried out to increase the motor

speed and when the H period is short the motor speed is

decreased. In the STOP mode, the output shows a L

output.

Forward or reverse rotation of the capstan motor is

controlled by transferring a CAP F/R signal developed at

pin 53 of IC501 to the drive IC through pin 7 of P502.

That is, when pin 7 of P502 is L, the capstan motor rotates

in clockwise direction and H in counterclockwise direc-

tion.


12/31

3 4

3-2-5. SP/LP/SLP Mode and Video SystemDetection

SP/LP/SLP mode playback is possible with NTSC

(3.58/4.43) system. The current playback tape speed

is displayed through VFD (Vacuum Fluorescent

Display) on the front panel or superimpose OSD on

the screen. In playback, SP/LP/SLP mode is identi-

fied by number of capstan FG pulses within one CTLcycle. The corresponding I2C data to/from the video

IC is output through pins 67/72 (common) while the

I2C clock is through pin 88 of IC501.

3-2-6. Edit RecordingEdit recording without picture disturbance at pictures

jointed is carried out by performing a train of

operations. That is, the capstan motor is reverse

rotated by a specific amount as soon as the REC

pause button is pressed, process in the servo micro-

computer is set to the edit mode as soon as the pause

is released, and then the recording is started againafter making a phase matching with the CTL signal at

the previously recorded part. In edit recording, the

microcomputer counts the FG pulse number and

controls so that the same number of FG pulse is

obtained in rewinding the tape and matching the

phase, thereby minimizing the overlap writing.

3-3. CAM LogicThe mechanical position of the tape motion and

threading mechanism is given by the cam gear through

signal lines CAM A, CAM B and CAM C.

When the loading motor rotates the cam gear, the me-

chanical contacts are mode in CAM A, CAM B and CAM

C. The combination of these three sensors (ON/OFF

signal) provide the microcomputer with the current statusof the mecha-deck.

Table 3-3-1

CAM A

CAM B

CAM Pos.

CAM C

VI fV eIV dIII cIII a b

Fig. 3-3-1 Cam position chart

MODE

SLOT IN,SLOT OUT,POWER OFF

LOADING,UNLOADING

REVIEW

PLAY, REC,STILL, CUE,STOP (Drum ON),REC PAUSE, SLOW

STOP (Drum OFF)

FF, REW

CAM CCAM B CAM APOSITION

H L L I

H L H II

L H H III

L H L IV

L L H V

L L L VI


13/31

3 5

P.CTLLOGIC

RTGMM

38

PDM 39

46CTL OUT

PDP

37

36

33

32

35

34

5bitD/A

CONV.

SWBIAS

SWPLAY

DQ1-5

SWREC

RECPATTERN

GENERA

TOR

5

RECAMP

AVCC1 CTLBIASAMP

AGND1

44

41

43

42

40

C-FGLOGIC

AVCC1

AGND1

+ -

+ -

+

+

FGB

CAP REF

4

FGA

+

CTL I/O2

3

1 CTL BIAS

+

+

PHSPDUP

CTLAMP1

CTLAMP0

CTLAMP2

SWSHORT

P502

FROMCAPSTANMOTOR

C520

1 50V

R5101.8k

C521100p

R51156k

C52247 6.3V

C5181 50V

R5081.8k

C519100p

R50956k

CFGAAMP

CFGBIN

CFGA IN

CFG BIASAMP

C51247 F16V

R5014.7k

R502820

C5112200pF

CBIAS

R/PCTL

C BIAS IN

R504220k

C515150pF

R505680k

R503470CNFB

C51347 6.3V

33k

10k

PLAYAMP

10k

10k

PDM

C5170.47

PDPC516

R5071M

R5061M

+ -

CAMP0

CAMP1

W701A

CFGB AMP

0.47

GND

6

5

R5131K

CTLHEAD

3-4. Viss Function

3-4-1. Operation of Analog Amplifier in lC501(TMP90CS74DF-6621)

IC501 (TMP90CS74DF-6621) is a newly developed

control microcomputer and contains control signal

amplifiers, schmidt circuit, control re-trigger function

in intermittent slow playback, 2 phase capstan FG

amplifier, etc.

Playback Mode

Fig. 3-4-1 shows analog amplifiers and peripheral circuit

in IC501 (TMP90CS74DF Series). Each capstan FG

enters pins 41, 43 of IC501, passes through an inverted

amplifier, inverted schmidt, and enters the servo as a speed

feedback signal.

Fig. 3-4-1 Analog amplifiers and peripheral circuit in IC501


14/31

3 6

One end of the control head (pin 1 of W701) is biased

at a specific level by pin 32 of IC501. The CTL

signal from pin 2 of W701 enters pin 33 of IC501

and amplified a built-in OP-Amp. The amplifier

output developed at pin 35 of IC501 (0 output

terminal) and the gain is determined by a resistor

connected between pin 35 of IC501 (0 output

terminal) and pin 37 of IC501 (negative feedbackterminal).

The amplifier gain is peak-detected inside the

microcomputer and the schmidt operation is started

at a position of 50% peak. The peak detection is

controlled by detecting a peak of the amplifier output

and by varying voltage applied to capacitors C516,

C517 at PDP terminal (pin 38 of IC501) and PDM

terminal (pin 39 of IC501). Amount of leakage of the

capacitors at PDP terminal and PDM terminal is

determined by R506 and R507. Furthermore, AMP0,

AMP1, AMP2 and SW SHORT switches are providedinside the microcomputer to switch the CTL amplifier

gain according to a mode used.

Since the CTL signal is used in a wide dynamic range

over the SLP playback and FF/REW, if the FF/REW

operation is carried out with the gain set in the

playback mode, a waveform distortion will occur and

the duty of CTL will vary.

To prevent this, above switches inside the

microcomputer are used to change the gain. In this

case, the amplifier output develops at the amplifier 1

output terminal (pin 36 of IC501) and the amplifier

gain is determined by a resistor R504 connected

between the amplifier 1 output terminal (pin 36 of

IC501) and the negative feedback terminal (pin 37 of

IC501). The reproduced signal is sent to the logic

circuit inside the IC, processed in the schmidt circuit,

and the waveform shaped output develops at the CTL

output terminal (pin 46 of IC501). This signal is fed

to the capstan phase control circuit and the CTL duty

cycle detection circuit inside the microcomputer.


15/31

4 1

4. LOGIC CIRCUIT4-1. System ControlIn the VCR, complex mechanism, video, audio, servo

circuits, etc. must be operated in specified timings

matched each other. The system control circuit

performs entire controls for the VCR.

An automatic stop function is also provided to protect

important tape if a trouble occurs on the complex

mechanism and the electrical circuits.

For this purpose, status of each part of the mechanism

is always monitored with various sensor switches, and

the microcomputer controls collectively the unit so that

the best condition is kept.

Moreover, the microcomputer controls signal

switchings for each circuit according to the mechanism

status.

Fig. 4-1-1 System control block diagram

M

FG B

M

PG/FG

FG AactivePOWER FAILURE

ABNORMALPOWER OFF ON( )

I2C BUS

Remote

control

Remote

Main microcomputer Loading motor control

(Voltage, direction)Loading motor drive M Loading motor

Cassette-out/REC-inhibition

Detection of cassette-out

position & broken safety tab

Cassette-in SWREC-inhibition

Mode sensor

(Detecting of mechanical mode position)Cam SW

Key matrix Front button

input

Reset signalReset circuit

Tape start sensorStart sensor Tape

Tape end sensorEnd sensor

Abnormal reel rotation

FF/REW speed controlTake up

Abnormal reel rotation

FF/REW speed controlSupply

T reel

sensor

S reelsensor

POWER ON/OFF

REC mute

TV/VTR

AUDIO

VIDEO

Tape end

LED

Current control

Capstan motor control

(Speed direction) Capstan

motor driveCapstan motor

FG.A pulse

FG.B pulse

CTL pulse

(Linear time counter)

REC control

Control

Cylinder motor control Cylinder

motor driveCylinder motor

PG/FG pulse

SMHCH

VCR

SERIAL

TRANSMISSION

MODEDATA

ICX01DISPLAY

MICROCOMPUTER

KEYDATA


16/31

5 1

5. PIF CHANNEL SECTION CIR-CUIT

5-1. OutlineThis circuit selects a desired broadcasting wave among

ground wave TV signals sent from antennas, develops

stabilized video and audio signals, and sends them to

the video and audio circuits. The output signals fromthe video and audio signals are converted into a signal

for channel 3 or 4 so that it can be received by a

conventional TV set.

A PLL complete sync detection system is employed as

the video detection system to improve waveform

distortion characteristics and picture quality character-

istics such as DG, DP, etc.

Configuration

(1) Antenna input/output circuits

(2) Tuner, channel selection circuits(3) PIF/SIF circuits

SPLITER

TUNING

TUNING

TUNING

TUNING

TUNING

TUNING

HPF

BPF

LPF

IFTUNE

TRAP

LPF

RFAMP

SWAFT

CH

SW

RFAMP

IFAMP

RFAMP

IFAMP

FMDET

RF MODULATORHA11560FP

PLLPC44818D

SAWRESONATOR

H007 TMLH2X006AANT OUT

3 IN 1 TUNERANT IN

RF OUT

RF SW

ANT INS0014.5MHz OSC

Q001

MIX/OSCAJ605A

PIF/SIF LA7577N

IF OUT

+B (9V)

ADDRESS

S.DATA

TU (32V)

PB (5V)

AUDIIO IN

CH SW

MB (5V)

RF AUDIO IN

TV/VCR

RF VIDEO IN

ON/OFF 5V

EVER 37V

SCL I

SDA I

AUDIO OUT

ON/OFF 9V

TUNERVIDEO OUT

AFT

CONTROL

AUDIO OUT

GND

AFT

N.C

VIDEO OUT

1

2

3

4

5

6

11

12

7

8

9

10

17

13

18

14

15

16

VIDEO IN

VIDEOCIRCUIT

4.5MHzBPF

N.C.

S.CLOCK

Above three circuits are integrated into a 3-IN-1 tuner

(TMLH2X006A)

Fig. 5-1-1 Block diagram of 3-IN-1 tuner


17/31

5 2

5-2. Antenna Input Output CircuitThe antenna input/output circuit consists of a spliter, RF

modulator and an antenna switch circuit. The spliter,

antenna switch circuit, and the RF modulator are

integrated into one unit. The spliter distributes a TV

signal from the antenna to built-in tuner and the antenna

switch.

(Input impedance is 75W , distribution loss is about 4 dBin VHF band and about 5 dB in UHF band.)

The antenna switch selects either one of the outputs

from the RF modulator and the spliter output according

to a selection of the TV/VCR switch on remote control-

ler. The antenna switch output develops the spliter

output when the TV is selected or the RF modulator

output when the video is selected. The antenna output

terminal is connected to the input terminal of the TV

receiver. As the RF modulator output can be switched

to channel 3 or channel 4, switching to a vacant channel

does not cause beat noises on the screen. The output

level of the RF modulator is about 66 dB (V) (peakvalue at 75W terminated).

Fig. 5-2-1

ANToutput

ANTinput

RFMODULATOR

DEVIATION

Antenna 8W

TUNER IF Signal

Video signal

Audio signal

BAND SW

INPUT SYNC.CIRCUIT

RF/AGC AMPCIRCUIT

TUNING CIRCUITBETWEEN STAGES

MIX.CIRCUITIF output VT

output

VT input

LOCAL OSCILLATIONCIRCUIT

PRE-SCALLERCIRCUIT

STANDARDOSCILLATION

4MHz

PLLCIRCUIT

LOWPASS

FILTER

Tuner section

PLL section

Clock

Data

Fig. 5-3-1

5-3. Tuner, Channel Selection CircuitThe channel selection circuit controls the tuner so that it

can tune in a desired broadcasting to receive it. This

unit employs a frequency synthesizer (FS) system to

obtain more stabilized receive frequency and less

variation of picture quality.

5-3-1. Channel Selecting OperationsThe main microcomputer performs following opera-

tions.

(1) Develops an audio mute pulse (A-Mute) and sets a

channel.

(2) Obtains a broadcasting frequency corresponding to

the channel number.

(3) Updates the channel display.

(4) Calculates an estimated broadcasting frequency and

the band data according to the channel number.

(5) That is, the computer varies frequency data and

reads the AFT data every time to search the

broadcasting frequency. When the frequency is

found, the computer locks the frequency data.

(6) Changes the audio mute output to high when the

channel selected is no signal.


18/31

5 3

5-3-2. Frequency Synthesizer CircuitWhen a specified voltage is applied to the tuning

voltage terminal (VT) of the ET tuner (Fig. 5-3-1), the

ET tuner tunes in a desired frequency, thereby receiv-

ing the broadcasting station. In a channel selection

circuit using the frequency synthesizing system, the

tuning frequency of the ET tuner is picked up as a

signal from the local oscillator and the signal isprocessed in a frequency divider operating at a division

ratio corresponding to the receive channel. The local

oscillator signal processed (counted down) in the

divider and another divided signal of a fixed reference

signal generator which has a very precision accuracy

are compared in their phases, and the tuning voltage is

varied according to the phase difference to keep the

receive frequency at a constant value. (This closed

loop is called a PLL loop.) Accordingly, TV

broadcastings can be received with very accurate and

stabilized condition.

The tuner used in this unit has the PLL circuit (Phase

Locked Loop).

The local oscillator in the tuner block is connected to

the PLL block through a PC board pattern. The tuning

voltage VT is also connected to the PLL circuit

through a PC board pattern, thus constituting the PLL

circuit.

A band data of 4 bits and division data which deter-

mine a receive frequency (Main counter data +

XXXX counter data: 15 bit) are transferred to the PLL

circuit through the I2C bus lines. The minimum

resolution by the division data is 62.5 kHz.

5-4. PIF CircuitThe TV signal sent from the antenna circuit enters the

tuner. The tuner develops IF signals corresponding to

the channel selected. The IF signals pass SAW filters,

enter an IF detector IC and video and audio signals are

detected.

5-4-1. PLL Complete Sync Detection SystemDescription on the PLL complete sync detection

system will be given by referring to a quasi sync

detection system. In the quasi sync detection system,an IF signal output from a tuner enters a sync detector

in passing through a SAW filter and an IF amplifier as

shown in Fig. 5-4-1.

The sync carrier for the sync detection is developed by

a tank circuit tuning in the limiter and P carrier.

On the other hand, in the PLL complete sync detection

system, processing method to develop the sync carrier is

different. That is, it uses a VCO (Voltage Controlled

Oscillator) output inside the IC. The VCO works as a

part of PLL with a APC DET (phase comparator) so

that it is locked to the P carrier from the tuner. ThePLL loop filter is set to about 100 kHz to reduce phase

modulated components caused at rising of a waveform,

thus reducing the waveform distortion by more than that

in the quasi sync detection system.

IFAMP

DET Videooutput

LIMITER

IF input

Quasi sync. detection

IFAMP

APCDET

DET

IF input

PLL sync. detection

VCO

Videooutput

New type White

Black

Time

Conventional

In a conventional quasi sync detection system, there is a

defect which makes black vertical stripes thicken.

Moreover, the PLL sync system is superior to the quasi

sync detection system in DG (Differential Gain), DP

(Differential Phase), cross color, sound beats, etc.

Fig. 5-4-1

Fig. 5-4-2


19/31

5 4

Peak deviation(KHz)

50

25

0fH

L +R PILOT

AM-DSB-SC

2fH 3fH 4fH 5fH

SAPdbx-TV NRFM 10KHz

6fHf

6.5fH

TELEMETRYFM 3KHz

fH 15.734KHz

L Rdbx-TV

NR5

5-5. MTS (Multi-channel TV Sound)Decoder

5-5-1. OutlineThe MTS decoder demodulates MTS composite signals

demodulated in the Tuner module (H001) and

sendsstereo sound outputs L and R, and SAP signals to

the audio circuit.

The MTS module consists of a MTS decoder IC

PC1852 controlled via I2C bus and associated circuits.

The PC1852 contains a stereo demodulation circuit,

SAP (Second Audio Program demodulation circuit),

dbx circuit, matrix circuit, etc.

The MTS composite signal to be entered into the MTS

module has frequency spectrums as shown in Fig. 5-5-

1.

(1) L-R and SAP signals are encoded with dbx-TV NR

(Noise Reduction).

(2) L-R signal is a carrier suppressed double sidebands

AM signal.

(3) SAP is a FM signal with frequency of deviation of

10 kHz from center of 5fH.

(4) TELEMETRY signal is not demodulated.

Fig. 5-5-1

5-5-2. Operation

(1) L+R (MAIN)

The MTS composite signal enters MPX IN terminal

pin 7 and the SAP and TELEMETRY signals are

suppressed in passing through a STEREO LPF.

Next, the pilot signal is canceled. Finally, the L-R

signal and the SAP signals are eliminated in passing

through the MAIN LPF, frequency response is adjusted

to a flat response in passing through an emphasis

circuit, and then fed to a matrix circuit.

(2) L-R (SUB)

The L-R signal passes the same circuits as the L+R

signal passes up to the pilot cancellation stage.

Since the L-R signal is a carrier suppressed double

sideband AM signal, it lacks carrier signal. So the

carrier signal must be restored. This restoration is

conducted using the pilot signal. Thus developed

carrier signal (quasi sine wave) is used to demodulate

the L-R signal. The demodulated L-R signal enters the

SUB LPF and residual high frequency components are

removed in passing through the SUB LPF. Then the

L-R signal enters the dbx-TV block through the NR-SW

circuit.

(3) SAP

The SAP is a FM signal with the center frequency of

5fH. First, only the SAP signal is extracted using a SAP

BPF. Then, the SAP is frequency detected. Finally,

high frequency components are removed from the SAP

signal in passing through the SAP LPF, the frequency

response is adjusted to flat, and then the SAP signal issent to the dbx-TV block through the NR-SW circuit.

(4) Mode identification

The mode identification is carried out by detecting

amplitude of the pilot signal. The SAP identification is

carried out by detecting 5fHcarrier and noises compo-

nents around 20 kHz in a stage following the FM

detector.

When stereo signals or the SAP signal are detected, the

information is updated in the contents of the read

register. (See Table 5-5-2.)

(5) Mode selection

The write register of subaddress 06H controls the output

terminals, pins 25 to 27 according to broadcast signals

and signals from the SAP SET SW to select the output

signals. (See Table 5-5-1 and 3.)


20/31

5 5

5-5-3. I2C BUS Commands(1) Subaddress list

Table 5-5-1 Write register (Command list)

SUBADDRESS MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

00H 0 During noise detection Input level settingStereo/SAP output stop

0: SAP OFF

1: Stereo, SAP OFF

01H 0 fH monitor ON/OFF Stereo VCO setting

0: OFF

1: ON

02H 0 Pilot canceler ON/OFF Filter setting

0: ON

1: OFF

03H 0 0 Low-band separation setting

04H 0 0 High-band separation setting

05H 0 5 fH monitor ON/OFF SAP VCO setting

0: OFF

1: ON

06H 0 0 Normal track Normal track SAP1/SAP2 Stereo/SAP Forced Mute

output select: 1 output select: 2 switch Note switch monaural

0: Internal SAP 0: SAP 0: SAP1 0: Stereo 0: OFF 0: ON

1: External SAP 1: Monaural 1: SAP2 1: SAP 1: ON 1: OFF

Note Output when SAP1 or SAP2 is selected is as follows:

Lot pin (L-channel output) Rot pin (R-channel output)

SAP1 SAP

SAP2 Monaural (L + R) SAP

Table 5-5-2 Read register

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

Broadcast status Receive status

Power-on reset Stereo pilot SAP signal Noise detection Stereo broadcast SAP broadcast

reception reception

0: Not available 0: Not available 0: Not available 0: Not available 0: Not available

1: Detect 1: Available 1: Available 1: Available 1: Available 1: Available 1 1


21/31

5 6

5-5-4. Mode Matrix(1) L-, R-channel output (LOT, ROT pins) matrix

Table 5-5-3 Mute OFF (Write register, subaddress 06H, bit D0 = 1)

BROADCAST WRITE REGISTER OUTPUT READ REGISTER

MODE Forced Stereo SAP1 Stereo L-ch R-ch Broadcast status Reception status Noise

monaural /SAP /SAP2 /SAP signal s ignal Stereo SAP Stereo SAP detection

ON/OFF switch switch output output output pilot signal broadcast broadcast

stop (LOT) (ROT) reception reception

Subaddress Subaddress

06H 00H

Bit: D1 Bit: D2 Bit: D3 Bit: D6 Bit: D6 Bit: D5 Bit: D3 Bit: D2 Bit: D4

Monaural L+R 0 0 0 0 0

Stereo 0 L R 1 0 1 0 0

0 L+R 1 0 1 0 1

1 0

1 L+R 1 0 1 0 0

Monaural+SAP 0 0 L+R 0 1 0 0 0

1 0 SAP 1 0

0 L+R 0 1 0 0 1

1

1 L+R SAP 0 1 0 1 0

0 L+R 0 1 0 0 1

1

1 L+R 0 1 0 0 0

Stereo+SAP 0 0 L R 1 1 1 0 0

0 L R 1 1 1 0 1

1 L+R 0

1 0 SAP 1 1 0 1 0

0 L+R 1 1 0 0 1

1

1 L+R SAP 1 1 0 1 0

0 L+R 1 1 0 0 1

1

1 L+R 1 1 0 0 0

Remarks: 1. Shaded areas represent weak electrical field.

2. : Dont care


22/31

5 7

(2) Normal output (NOT pin) matrix

Table 5-5-4 Mute OFF (Write register, subaddress 06H, bit D0 = 1)

BROADCAST WRITE REGISTER OUTPUT

MODE Normal track Normal track Forced monaural Stereo/SAP SAP1/SAP2 Normal output

Output Output ON/OFF switch switch (NOT pin)selection 2 selection 1

Subaddress: 06H

Bit: D4 Bit: D5 Bit: D1 Bit: D2 Bit: D3

Monaural L+R

Stereo L+R

Monaural+SAP 0 0 0 0 L+R

1 SAP

1 L+R

1 External SAP*

1 L+R

Stereo+SAP 0 0 0 0 L+R

1 SAP

1 L+R

1 External SAP*

1 L+R

Remark : Dont care

* : SAP signal input from ESA pin.

Caution All normal outputs with weak electrical field are L+R.


23/31

5 8

5-5-5. Block Diagram of MTS Decoder IC (PC1852)

Fig. 5-5-2 Block diagram of MTS decoder IC (PC1852)

6 5 4 3 2 17 16 15 14 28 27 26 25 24

23202122191813112

MatrixSelector

MatrixSelector

OffsetAbsorption

Stereo/SAPSwitch

Filter

Adjustment

SAP DemodulationBlock

StereoDemodulation

Block

MatrixSelector

12C Bus Interface

dbx Noise Reduction Block

1/2 Vcc

1198107

D/A

InputAttenuator

D/A

Normaloutput

R signaloutput

L signaloutput

1 F1 F22 F

GND12C GND0.1 F

1K4.7 F

1 F

SDASCL

10 F

5.1k

1 F16.6k

9V0.1 F

2.2 F

0.47 F 60k

0.1 F

0.047 F

ExternalSAP

Compositesignal input

1 F 3k

3.3F

1 F


24/31

6 1

6. VIDEO CIRCUIT6-1. Introduction

6-1-1. BackgroundThe concept is to reduce component count without

any compromise in the product quality. To achieve

this in video circuitrys, major video functional

blocks such as DOC, CCD delay line, OSD insert, areall packed into the video IC (TA1251F). Further-

more, it also has built-in linear audio circuit to

process conventional audio.

This TA1251F is designed exclusively for use with

the NTSC color television system. It uses parallel

control to switch each mode and characterisctics. No

I2C bus architecture is employed.

Fig. 6-1-1 shows a block diagram for video system

configuration.

6-2. Signal Flow

6-2-1. EE ModeThe CVBS signal comes from video line input (phono

jack). The chosen video is input to video processing

IC201 TA1251F pin 53. The video signal at pin 53 is

switched inside IC201 according to the input select line

(pin 6).

The level of the video signal is controlled by the AGCcircuit and outputs at pin 49.

6-2-2. Y Signal Record PathThe video signal that enter pin 53 of IC201 passes

through an AGC amplifier and then through main LPF

to separate the Y signal from the color. The Y signal

passed through the DPE, non-linear emphasis inside

IC201 is then emphasized by the main emphasis circuit at

pin 55 and 56. The level of the emphasized record Y

signal is controlled through white clip/dark clip circuits

before being FM modulated. The modulated signal willpass through a FM equalizer before mixing with record

color and outputs at pin 62. (Refer to Fig. 6-2-1.)

Fig. 6-2-1 Y signal record path

Fig. 6-1-1

DrumCGWA6NM

DrumInterface

TA1251F

RF ANT OUTRF ANT IN

Video OUT

VideoLine IN

OSDVideo IN

TMLH2X006A3 in 1Tuner

62 56 55 53 51 50 49 47 44

FM

MOD

MAIN

EMPH

RE-FMEQ

FBclamp

AGCDET

AGCFIL

FMAGC

Sync

sep

DPEMAINLPF

YNRDOC

NLEMPH

PV/PH/

OSD

Clamp

Clamp

AGC

RECFM OUT

C252 C238L207

R214R213

C237

C234

C232R210VideoOUT

Video LineIN

OSD VideoIN

C-SyncOUT

IC201 TA1251F


25/31

6 2

6-2-3. Color Signal Record PathThe color signal is separated from the input video

signal by a band pass filter inside IC201. The

separated color signal (C signal) passes through the

ACC circuit, burst emphasis circuit inside IC201 and

then down converted to 625 kHz in the main

converter circuit. Refer to Fig. 6-2-2.

Fig. 6-2-2 Color signal record path

62 53

23 22

51 50 49 47 44

FBclamp

MAINLPF

ACCAMP

BurstEMPH

REC C Lev

AGCDET

MAINCONV

PV/PH/

OSD

SubBPF

REC-CLPF

MAINBPF

C232R210

RECFM OUT

VideoOUT

OSD VideoIN

C-SyncOUT

IC201 TA1251F

AGCDET

Sync

sep

ClampAGC

C-ACCDET

C214 C212

REC-Y

FM

AGCFIL

C234

Video LineIN


26/31

6 3

6-2-4. Y Signal Playback PathThe playback Y signal entered at pin 63 of IC201 will

pass through a FM AGC amplifier, playback FM

equalizer, a color trap, double limiter circuit, FM

demodulator and output at pin 55. The demodulated

Y signal at pin 55 goes through the main de-emphasis

(external circuit) and returns to pin 58 of IC201.

Then the Y signal will be amplified, pass through themain LPF, nonlinear de-emphasis circuit, YNR and

output at pin 41.

The playback, Y signal enter Y-comb/DOC circuit

through pin 43 and 1H delayed signal is developed by

a CCD circuit through pin 39 of IC201. After the Y-

comb circuit, the Y signal will pass through ANR and

mixes with PBC. The mixed signal passes through a

quasi H and V sync signal insertion circuit and

amplified before output at pin 49 of IC201. Refer to

Fig. 6-2-3.

Fig. 6-2-3 Y signal playback path

(1) 1H CCD and Y-comb filter

In Playback mode, each video head scans its magnetic

track, and also picks up some FM signal from an

adjacent track. This cross-talk of FM signal also contains

other line frequency related noise components, and all

these noise have to be reduced. The basis of the

noise reduction scheme is to shift the recorded FM

signal by 7.8 kHz or 1/2fh so that each adjacent magnetictrack has a half line frequency shift with respect to its

neighbor. Because of this, when Playback, the cross-talk

FM signal will have 180 degrees phase different as

compared with the original signal after passing through

the 1H delay circuit. Therefore, FM cross-talk can be

eliminated by adding the two signals. At the same time,

other line frequency related noise is also reduced by this

process due to the fact that noise is uncorrelated

between original and delayed signal.

This feature is incorporated inside the IC201 and can

monitor at pin 39, pin 37, and pin 43.

63 55 58 40 3959

37

43

49

CTrap

PB FMAGC

MAINLPF

YNRDOC

GCA

PV/PH/OSD

Clamp

ANR

NL

Deemph

FMDeMod

SubLPF

FBClamp

De-Emphasis

IC201 TA1251F

PB FMEQ

DoubleLimiter

1HDelay

PB

AMP

V-out

PBC

PBY

C242PBFMIN

C254C225

5V

Q208

C227R223


27/31

6 4

6-2-5. Color Signal Playback PathThe FM signal enters pin 64 of IC201 for color

processing. In IC201, the C signal passes through

another LPF, a Pre-ACC amplifier, burst de-emphasis

circuit and converted into the 3.58 MHz band signal.

The converted C signal will pass through a trap, Sub-

BPF and output at pin 26 to IC201. The signal

enters the C-comb filter at pin 28 and output at pin30 of IC201.

The color signal reenters at pin 24 of IC201 and

passes through the main BPF, ACC amp and through

capacitor C208 at pin 17 and pin 15 of IC201. The

signal then, mixes with PBY and output at pin 49.

Refer to Fig. 6-2-4.

Fig. 6-2-4 Color signal playback path

6-3. Control Signal for Head Signal Am-plifier

The REC FM Y is sent out through pin 2 of PV01 to head

amplifier for recording.

The composite sync signal output from pin 44 of IC201

goes into pin 4 of PV01.

The video SW appears at pin 5 of PV01 to select therequired heads for operation

26

PB-C

LPF

Ch.ACC

Y/CTiming

B-Deemph

PV/PH/OSD

Clamp

MainCONV

Trap Sub

LPF

28

2217 24

C-Comb 30

MainBPF

ACCAMP

ACCDET

64

C243PB FMIN

Q207

C-Comboutput

R222

PBY

PBC

Vcc

C215

ColorInputafter C-comb

C212PBC

C208VideoOUT

1549


28/31

7 1

Table 7-1-1 Operations and functions of Hi-Fi audio process IC

LOCATION No. IC NAME OPERATION FUNCTION

IC920 TA1246F Input Switching L+R MIX output for Conventional Audio

Output Switching Output Switching Circuit

Mute Switching Circuit

Noise Reduction Noise Reduction Circuit (NR Emphasis, Built-in NRLPF)Emphasis Circuit

Audio Clip Circuit

FM Modulation/ FM Modulation/Demodulation Circuit

Demodulation AGC Circuit

BPF

Dropout Detection

Audio Tracking Circuit

Noise Correction Circuit

7. AUDIO CIRCUIT7-1. Hi-Fi Audio CircuitThe Hi-Fi audio circuit exists on the Main Board.

7-1-1. Outline of Hi-Fi Audio CircuitIn this Hi-Fi audio process IC (TA1246F), the input

switch, output switch, noise reduction circuit, FM

modulation/demodulation circuit, and the mute circuitare combined in one chip. (The conventional audio

circuit is eliminated from TA8863 which has been used

on the current Hi-Fi VCR.)

In this IC, each mode and characteristic can be switched

by I2C-bus from the main microcomputer.

Table 7-1-1 shows the operation and function on this

IC.

The Hi-Fi audio circuit consists of the FM modulation/

demodulation circuit which performs record and

playback of audio signal with FM modulation, the noise

reduction circuit, the input/output switching circuit, and

etc.

In the record mode, the audio signal entered from the

line input is recorded with the conventional and Hi-Fi

audio. The Hi-Fi audio can be recorded and played

back in stereo mode, and the conventional audio is

recorded and played back in monaural mode.

7-1-2. EE Mode(1) Audio input/output switching circuit

The line input entered from the P920 is input to the

input switching circuit of IC920, and selects the

signal to be recorded by the data of I2C-bus. This

recording signal is supplied to the Hi-Fi recording

circuit, and a part of the signal is supplied to the

monitor switching circuit as EE system signal.In the monitor switching circuit, the output signal is

selected from the EE audio signal and the

conventional audio signal. The output signal of this

monitor switching circuit is supplied to the

output switching circuit, and it is output from pin

11 and 13 after selection of L ch, R ch or stereo

mode.

(2) Audio mute circuit

The mute circuit is provided in the IC920 inside to

suppress noises generated by the power ON/OFF

and mode switching.

When output from pin 10 of IC920 is Hi, pin 12

and 14 are grounded, and then the line output signal

is muted.


29/31

7 2

Fig. 7-1-1 Signal flow in I/O and mute circuits (L ch)

(R ch has the same circuit components)

7-1-3. Recording Circuit

In the record mode, the audio signal selected by theinput switching circuit is input to the Hi-Fi audio

recording circuit.

In Hi-Fi audio recording circuit, the signal is applied to

VCO passing through PNR circuit and 20kHz LPF.

Also, the LPF output signal is fed back to the PNR

circuit passing through the peak detection circuit, and

controls the amplifier gain and the characteristics of the

PNR circuit.

The audio signal to be entered the VCO is com-

pressed by a square root ration passing through the

above PNR circuit and peak detection circuit.

The audio signal applied to VCO is modulated with

frequency. FM carrier frequency is L ch 1.3MHz and Rch 1.7MHz.

As the carriers and the frequency deviation have been

adjusted in fabricating the ICs, no adjustment will be

necessary.

The audio signal modulated with FM is added to FM

signal of the opposite channel after passing through the

FM LPF, and it is output from pin 22, and then sent to

the pre-amplifier in the cylinder.

Fig. 7-1-2 REC signal flow in Hi-Fi audio circuit (L ch)


31

35 11

12

10

IC920 TA1246F

EE47

ConventionalAudio Circuit

Line

From R ch inputswitching circuit

Conventional Audio

N.A InputSwitching

Circuit

L ch

MonitorSwitchingCircuit

L ch InputSwitching

Circuit

L chRecording

Circuit

From R ch monitorswitching circuit

L ch Output

SwitchingCircuit

Mute Switch

LineOutput L ch

(IC501)Audio Mute : Hi

20kHz

L.P.F. VCO

FM

L.P.F.

Audio FMModulationSignal

IC920 TA1246F

9

22

8

7

6

Emphasiselement

To Audio MonitorSwitching Circuit

PNR

Circuit

InputSwitching

Circuit

FM Signal ofOpposite Channel

Peak Detection Circuit

SmoothingCapacitor

Waighting Element


30/31

7 3

7-1-4. Playback CircuitThe playback audio FM signal to be output from the

pre-amplifier in the cylinder is input to pin 25 of IC920,

and input to the AGC amplifier. The playback audio

FM signal amplified by the AGC amplifier is input to

the BPFs (Band Pass Filters) of 1.3MHz and 1.7MHz,

and then it is demodulated by the phase sync circuit

consisting of each VCO and the phase detection circuit.The demodulated audio signal is input to the 20kHz

LPF after switching noises are corrected by the

switching noise correction circuit.

The signals except the audio band are eliminated by the

20kHz LPF, and the amplifier gain and the

characteristics by the PNR circuit are adjusted, and

then the audio signal is sent to the monitor switching

circuit after applying de-emphasis.

Also, the output of the 20kHz LPF is input to the

peak detection circuit, and the peak detection is

performed after being weighted.

The audio signal which the peak detection is performedis added to the PNR circuit with the inverse

characteristics against the recording characteristics, and

the amplifier gain of the PNR circuit is adjusted.

In result, the audio signal to be input to the monitor

switching circuit by the PNR circuit and the peak

detection circuit has the characteristic expanded in the

square power.

This expansion characteristic has the inverse

characteristic against the compression characteristic

for recording, and it returns back to original signal

level though process of the record and playback.

7-1-5. Dropout Correction CircuitThe playback audio FM signal to be input from pin

25 of IC920 is amplified by the AGC amplifier, and

input to BPF.

The gain of the AGC amplifier is adjusted by using this

BPF output.

Also, the BPF output of this 1.7MHz is used for the

dropout detection.

The dropout detection signal outputs the timing noise

correction pulse specified in IC inside, and noises are

corrected.

Also, when the dropout exceeding the time specified

with the external time constant is detected, the Hi-Fi

audio signal is muted by operating the mute circuit of

IC920 inside, and the conventional audio output

condition is set forcibly.

The following shows the cases in which the forced

normal switching will start to operate:

(1) When playing back a tape where Hi-Fi is notrecorded.

(2) When the tracking adjustment is not correct.

Fig. 7-1-3 Playback signal flow in Hi-Fi audio circuit (L ch)


BPF

NTSC: 1.7M

BPF

NTSC: 1.3M

AGC

AMP

VCO

20kHz

LPFPNR

IC920 TA1246F

25

11

9

8

7

6

Playback FM

Signal Input

Phase

Detection

Circuit

SwitchingNoise

CorrectionCircuit

OutputSwitching

Circuit

MonitorSwitching

Circuit

Line Output

L ch

Emphasis

Element

SmoothingCapacitor

Weighting Element

Peak Detection

Circuit


31/31

Toshiba VCR Training M-653

Documents

Transcript of Toshiba VCR Training M-653