Topic09 The timer subsystem on the Freescale MC9S12X

Timers: Father Time in a uP...

Topic Video 099

Friday, 5 November 2010

Timer • The timer section of the 9S12X is based around a 16 bit

free running counter driven by the system clock.

• The timer system provides the following basic functions:

• A Timer overflow

• Can be used to generate interrupts at predetermined intervals.

• Up to 8 Output Compare Functions

• Can be used to generate a variety of output waveforms by comparing the free running counter to programmable registers.

• Up to 8 Input Compare Functions

• Can be used to latch the value in the free running counter on the edges of an input signal.

• A single 16 bit pulse accumulator

• Pulse Width Modulator


Timer Overflow

• One of the great features of the timer subsystem is the timer overflow.

• The timer is a free running 16 bit counter called TCNT, it increments from $0000 to $FFFF, then overflows back to $0000 and continues once more.

• Each time TCNT resets back to $0000, the timer can trigger a Timer Overflow Interrupt (TOI).

• The period of the TOI can be altered by changing the rate at which the counter TCNT increments.

• The counter increments on each rising edge of the clock source, so changing the frequency of the clock source, through prescaling would therefore change the period between TOIs.


Timer OverflowA 2bit Example

00

TCNT Free Running Counter



01




10





11




00

TOI


Controlling the TOI

• Programming the Timer Overflow is done using the following registers of the Enhanced Capture Timer.

TCNTH

TCNTL

TFLG2

TSCR2

TSCR1


TSCR1

– TEN (Timer Enable)• This bit enables the Timer Subsystem

• 0 means subsystem is OFF• 1 means subsystem is ON

– TSWAI(Timer module stops while in WAIT mode)• This bit controls the behavior of the system during WAIT.

• 0 means subsystem is running unaffected during a WAIT.• 1 means subsystem is disabled during WAIT.

000PRNTTFFCATSFRZTSWAITEN

Controlling the TOI


TSCR1

– TSFRZ (Timer and modulus counter stop while in Freeze mode)• This bit controls the behavior of the system during FREEZE.

• 0 means subsystem is running unaffected during a FREEZE.• 1 means subsystem is disabled during FREEZE.

– TFFCA (Timer Fast Flag Clear all). • 0 means that the TOF flag must be manually cleared.• 1 means that any read or write to a Output/Input compare

register automatically resets the TOF flag.


Controlling the TOI


TSCR1

– PRNT(Precision Timer)• This bit controls the behavior of the Timer.

• 0 means legacy timer is enabled.• 1 means precision timer is enabled.


Controlling the TOI


TSCR2

– TOI (Timer Overflow Interrupt Enable)• 0 means Timer overflow interrupt is disabled.• 1 means Timer overflow interrupt is enabled.

– TCRE (Timer Counter Reset Enable). • 0 means that TCNT runs normally and overflows at $FFFF.• 1 means that TCNT is reset when its contents equals that of

TC7.

PR0PR1PR2TCRE000TOI

Controlling the TOI


TSCR2

– PR2-PR0 (Timer Prescaler Select)• When PRNT is cleared, these bits select the main Timer

Prescaler.

PR0PR1PR2TCRE000TOI

Prescale factor = 2PR[2:0]

Controlling the TOI


Controlling the TOI

TFLG2

• TOF (Timer Overflow Flag)– Writing 1 to TOF resets the timer overflow flag.– Failure to reset this flag in the ISR will result in a continuos firing of the

TOI interrupt.

0000000TOF


Using the TOI

• Since the TOI is a part of the timer subsystem, it makes sense that the timer must be enabled for it to work.

• The Timer Overflow System is enabled by setting the msb (0x80) of the TSCR1. The remaining bits in this register are related to IOC and are not required by the TOI.

• The TOI is enabled by ensuring that TOI in TSCR2 is set and that TCRE is cleared.

• A value for PR2-PR0 needs to be chosen in order to produce the desired interrupt period.

• Lastly, interrupts need to be enabled (assuming an ISR has been written that resets TOF in TFLAG2).


Using the TOIFinding a value for PR2-PR0

• The value for PR is simply a prescaler on the Bus Clock (fbus) to produce the Timer Clock (ftimer).

ftimer = fbus / (2PR)

• The Timer Clock is then used to pulse TCNT which increments on each rising clock edge. It will take 65536 clock pulses to cause TCNT to overflow. So the TOI period (TOIperiod) would be

TOIperiod = (2PR*65536)/fbus


Timer Overflow System

TSCR1

TSCR2

TSCR2

BUS CLOCK

Timer Overflow System


Example

• We would like to create a program to toggle the output on pin 1 of PORTA every 131ms.

• Firstly, we will need to calculate the value of PR.TOIperiod = (2PR*65536)/fbus

PR = log2 ( (TOIperiod*fbus)/65536 )

• Assuming an 8MHz bus clock, the value for PR isPR = log2 ( (TOIperiod*fbus)/65536 )

PR = log2 ( (0.131*8000000)/65536 )

PR = 4


Examplemainloop: MOVB #$F7,IVBR

MOVB #$01,DDRA

MOVB #$01,PORTA

JSR InitTOI

Spin BRA Spin

InitTOI: MOVB #$80,TSCR1 ; Turn on Timer Subsystem, Fast Flag Clearing is OFF.

MOVB #$84,TSCR2 ; Turn on TOI, TCRE is OFF and prescaler set at 4.

CLI ; Turn ON interrupts.

RTS

TOI_ISR: MOVB #$80,TFLG2 ; Reset TOF Flag

LDAA PORTA

EORA #$01

STAA PORTA

RTI


Example

ORG $FFDE ; Set up Interrupt Vector Table

DC.W TOI_ISR ; TOI Vector


Pulse Width Modulation

• Pulse width modulation is the process of encoding numbers into the width of digital pulses.

• With the use of a free running counter both the width and period of a digital pulse can be set using programmable registers.

• Pulse width modulation is an efficient means of controlling electric motors. It allows the speed of the motor to be varied without losing valuable torque.


Pulse Width Modulation

• The 9S12X has 8 PWM channels.

• Each PWM channel has a duty register and a period register associated with it.

• The duty register defines the value at which the PWM channel will change its state.

• The period register defines the value at which the counter and channel must reset.

DUTY PERIOD


Pulse Width ModulationA 3bit Example

PERIODDUTY

000

Free Running Counter



PERIODDUTY

011 101

000




PERIODDUTY

011 101

001




011 101

010

PERIODDUTY




101

PERIODDUTY


011

011



011 101

100

PERIODDUTY




011

PERIODDUTY


101

101



011 101

000

PERIODDUTY



On-Chip PWM Subsystem

• The PWM Subsystem on the MC9S12XDP512 contains

• Eight independent PWM channels with programmable period and duty cycle

• Dedicated counter for each PWM channel

• Programmable PWM enable/disable for each channel

• Software selection of PWM duty pulse polarity for each channel


On-Chip PWM Subsystem


Controlling the PWM

• Interaction with the PWM subsystem is done via the following register set.

PWMDTYx

PWMPERx

PWMCNTx

PWMPOL

PWME

PWMPRCLK

PWMCLK

PWMCTL

PWMCAE

PWMSCLB

PWMSCLA


Controlling the PWM

PWME (PWM Enable Register)

– PWMEx (Pulse Width Modulation Enable)• 0 means the PWM channel is disabled.• 1 means the PWM channel is enabled.

PWME0PWME1PWME6PWME7 PWME5 PWME4 PWME3 PWME2


Controlling the PWM

PWMPOL (PWM Polarity Register)

– PPOLx (Pulse Polarity)• 0 means the PWM channel output starts low.• 1 means the PWM channel output starts high.

PPOL0PPOL1PPOL6PPOL7 PPOL5 PPOL4 PPOL3 PPOL2


Controlling the PWM

PWMCLK (PWM CLock Select Register)

– PCLKx (Pulse Clock Source Select)• For PCLK7, PCLK6, PCLK3, PCLK2

• 0 means ClockB is the clock source.• 1 means ClockSB is the clock source.

• For PCLK5, PCLK4, PCLK1, PCLK0• 0 means ClockA is the clock source.• 1 means ClockSA is the clock source.

PCLK0PCLK1PCLK6PCLK7 PCLK5 PCLK4 PCLK3 PCLK2


Controlling the PWMPWMPRCLK (PWM Prescale Clock Select Register)

– PCKBx (ClockB prescaler)• These three bits are used to prescale ClockB.

– PCKAx (ClockA prescaler)• These three bits are used to prescale ClockA.

PCKA0PCKA1PCKB20 PCKB1 PCKB0 0 PCKA2


Controlling the PWM

PWMSCLA (PWM Scale A Register)

– Prescaler for Clock SA

fClockSA = Clock A / ( 2 * PWMSCLA)

• Note a value of $00 in PWMSCLA means 256.

Bit0Bit1Bit6Bit7 Bit5 Bit4 Bit3 Bit2


Controlling the PWM

PWMSCLB (PWM Scale B Register)

– Prescaler for Clock SB

fClockSB = Clock B / ( 2 * PWMSCLB)

• Note a value of $00 in PWMSCLB means 256.



PWM Clocks


Controlling the PWM

PWMCAE (PWM Center Align Enable Register)

– CAEx (Center Aligned Output Mode)• 0 means channel works in left-aligned mode.• 1 means channel works in center-aligned mode.

CAE0CAE1CAE6CAE7 CAE5 CAE4 CAE3 CAE2


Controlling the PWM

PWMCTL (PWM Control Register)

– CONxy (Concatenate Channels)• 0 means the channels work as two seperate independent 8

bit channels.• 1 means both channels work as a single 16 bit PWM

channel, channel x provides the output channel y is unused.

– PSWAI (PWM Stops in WAIT mode)• 0 means PWM functions normally in WAIT mode.• 1 means STOP the input clock to the PWM when in WAIT

mode.

00CON45CON67 CON23 CON01 PSWAI PFREZ


Controlling the PWM

PWMCTL (PWM Control Register)

– PFREZ (PWM Stops Counters in Freeze Mode)• 0 allows PWM to continue normally in FREEZE mode.• 1 means STOP the input clock to the PWM when in

FREEZE mode.

00CON45CON67 CON23 CON01 PSWAI PFREZ


Controlling the PWM

PWMCNTx (PWM Channel Counter Registers)

• Each Channel has its own counter associated with it. These counters can be read at any time but can not be written to.



Controlling the PWM

PWMPERx (PWM Channel Period Registers)

• Each Channel has its own period register associated with it. These registers can be written to at any time, but it is always a good idea to turn off the channel before modifying it.



Controlling the PWM

PWMDTYx (PWM Channel Duty Registers)

• Each Channel has its own duty register associated with it. These registers can be written to at any time, but it is always a good idea to turn off the channel before modifying it.



Using the PWM

• When using the PWM system there are a few questions that you need to ask about your application.

• Does the application require 8 or 16 bit PWM?

• What clock frequency does your application require?

• Does the waveform need to be center-aligned?

• Does the output waveform need to start at ‘0’ or ‘1’?


Example• We have an application that requires a 10Hz waveform

with a 50% duty cycle (PWMPER = 2 * PWMDTY) on PWM0.

• The PWMPER in combination with clock prescalers will enable us to create a 10 Hz waveform.

• Assuming we used ClockA as our clock source and also assuming our bus clock was 8MHz, we could only prescale Clock A down to 62.5kHz (8MHz/128). Therefore we shall require the use of clock SA.


Example

• The problem can be reduced mathematically to

10Hz = fbus /( 2PCKA2:0 * 2 * PWMSCLA * PWMPER0)

• If we choose PCKA2:0 to be 7 and PWMSCLA to be 132 then PWMPER0 must be

PWMPER0 = 8,000,000/(10 * 128 * 2 * 132 )

PWMPER0 = 23.67 (24)

PWMDTY0 = 12 (for 50%)


Example




PWMPER0 = 8,000,000/(10 * 128 * 2 * 132 )

PWMPER0 = 23.67 (24)


ClockA


Example




PWMPER0 = 8,000,000/(10 * 128 * 2 * 132 )

PWMPER0 = 23.67 (24)



Example




PWMPER0 = 8,000,000/(10 * 128 * 2 * 132 )

PWMPER0 = 23.67 (24)


ClockSAPrescaler


Example




PWMPER0 = 8,000,000/(10 * 128 * 2 * 132 )

PWMPER0 = 23.67 (24)



Example




PWMPER0 = 8,000,000/(10 * 128 * 2 * 132 )

PWMPER0 = 23.67 (24)


ClockSA


Example




PWMPER0 = 8,000,000/(10 * 128 * 2 * 132 )

PWMPER0 = 23.67 (24)



Examplemainloop: JSR InitPWM

Spin BRA Spin

InitPWM: MOVB #$00,PWME ; Turn OFF PWM Channels.

MOVB #$00,PWMPOL ; All PWM channels start low.

MOVB #$01,PWMCLK ; Clock SA chosen for PWM0.

MOVB #$07,PWMPRCLK ; Set ClockA prescale to /128.

MOVB #$00,PWMCAE ; All PWM channels are left-justified.

MOVB #$00,PWMCTL ; All PWM channels are independent.

MOVB #132,PWMSCLA ; Set SA clock prescaler to /132.

MOVB #24,PWMPER0 ; Set the period to 24 (10Hz).

MOVB #12,PWMDTY0 ; Set the duty cycle to 12 (50%).

MOVB #$01,PWME ; Enable PWM0

RTS


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Topic09 The timer subsystem on the Freescale MC9S12X

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