Topic 8 Sequential Circuits
Transcript of Topic 8 Sequential Circuits
Topic 8 - 1 Nov-27-09 E4.20 Digital IC Design
Topic 8
Sequential Circuits1
Peter Cheung Department of Electrical & Electronic Engineering
Imperial College London
URL: www.ee.ic.ac.uk/pcheung/ E-mail: [email protected]
Rabaey Chapter 7
1 Based on slides from Prentice-Hall
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Mux-Based Latches
Negative latch (transparent when CLK= 0)
Positive latch (transparent when CLK= 1)
CLK
1
0 D
Q 0
CLK
1 D
Q
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Master-Slave (Edge-Triggered) Register
Two opposite latches trigger on edge Also called master-slave latch pair
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Overpowering the Feedback Loop ─ Cross-Coupled Pairs
NOR-based set-reset
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Cross-Coupled NAND
Cross-coupled NANDs Added clock
This is not used in datapaths any more, but is a basic building block for memory cell
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Sizing Issues
Output voltage dependence on transistor width
Transient response
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Master-Slave Static Flip-flop
Overlapping Clocks Can Cause • Race Conditions • Undefined Signals
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Other Latches/Registers: C2MOS
“Keepers” can be added to make circuit pseudo-static
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Insensitive to Clock-Overlap
M 1
D Q M 4
M 2
0 0
V DD
X
M 5
M 8
M 6
V DD
(a) (0-0) overlap
M 3
M 1
D Q
M 2
1
V DD
X M 7 1
M 5
M 6
V DD
(b) (1-1) overlap
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Other Latches/Registers: TSPC
Negative latch (transparent when CLK= 0)
Positive latch (transparent when CLK= 1)
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Including Logic in TSPC
AND latch Example: logic inside the latch
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μ π latches: Poor man’s TSPC Latch
What is wrong with this TSPC Latch?
Second attempt:
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Pulse-Triggered Latches An Alternative Approach
Master-Slave Latches
D Clk
Q D Clk
Q
Clk
Data D Clk
Q Clk Data
Pulse-Triggered Latch
L1 L2 L
Ways to design an edge-triggered sequential cell:
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Pulsed Latches
Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :
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Non-Bistable Sequential Circuits─ Schmitt Trigger
• VTC with hysteresis
• Restores signal slopes