TOP beamtest, electronics and plans
Transcript of TOP beamtest, electronics and plans
TOP beamtest, electronics and plans
Gary Varner University of Hawaii for the bPID groupGary Varner, University of Hawaii for the bPID group, BPAC, February 27th, 2012
What tested – detector components
R 5000mml=1200+1310+30mm=2540mm
R=5000mm
(Integrated Front‐end)(Integration atw=450mm
440mm
(Integration at Nagoya University)
t=20mm
54mm
54mm
2Belle II barrel Particle Identification (p/K separation) Upgrade: Start running at SuperKEKB in 2015
Goal: Data versus Simulation• Use data to tune/confirm Monte Carlo• Use data to tune/confirm Monte Carlo• Results below were for old PMT type & CAMAC readout
DataPDF (floating norm)
TDC (counts/25ps)TDC (counts/25ps)
ch16~19 ch32~353
Beam test set‐upp
5x5mm2
Trigger5x5mm2
TriggerVeto counters
Tracker Timing counters
Trigger TriggerTOP Tracker
• 2‐types scintillator trigger counters– Larger counters (50x50mm2) for system checks and beam alignmentLarger counters (50x50mm ) for system checks and beam alignment– Smaller counters (5x5mm2) to realize a collimated beam
• SciFi tracker: 2D, ~3m distance, resolution~1mm• Veto counters: to reduce hadronic shower eventsVeto counters: to reduce hadronic shower events• Timing counters: resolution~22ps
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Ready for beam
(not pictured: Yasuyuki Horii (photographer) [Nagoya], Alan Schwartz
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( p y (p g p ) [ g y ],[Cincinnati], Lynn Wood [PNNL], Marc Rosen & Casey Honniball [Hawaii] )
DAQ system Hawaii Tracker(ASIC SciFi readout)
DC power for pFront‐end Modules
cPCI CPU and fiber
VME/ /
cPCI CPU and fiberCard (custom) = “PC1”; USB readout of CAMACTrig/Timing/
ProgrammingModule
of CAMAC
Dell PowerEdge2970 Server (“PC2”)
Firmware programming (USB to remote JTAG)
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Trigger/HVCAEN HV
Nagoya Trigger Logic/Timing Modules
Pico‐second Calibration LaserTrigger
CAMAC for
Trigger
“SuperKEKB RF clock phase measurement, Nagoya timing counters/tracker 9
Some LimitationsO l 20/32 t bOnly 20/32 tubes from Hamamatsu
JT0180 tripped frequently (not used)
82% of electronics h l “ d”channels “good”(bad RF amps, solder connections, etc.)
384 channels @ 2.7 GSa/s “oscilloscope on
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pa chip” (1.5TBy/s)!
Event Sizes/Rates• Read 4 “windows” of 64 samples from each channel (each channel has 512 windows of t )storage);
• 1 fiber link/module
• Each event ~74kB/module
• Total ~ 230kB/event• Total 230kB/event
• Logging rate obtained was 130‐160 events/spill160 events/spill
(~10MB/s PCI bus + CAMAC USB)
Able to log about 100k beam events per day (~1‐2 M single photons), with comparable number of laser calibration events
11To do better will need to zero‐suppress/online feature extraction (next beam test)
Example single‐photon signals
Clean hit (center of Anode pad) Depending upon amplitude, “cross talk” hit (red) == remove by filteringtalk hit (red) == remove by filtering
( f f )(16 waveforms from JT0164)
Can (in principle) decouple PMT, i i & d t t lk
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wiring & readout x‐talk
Start timing/tracking
Veto counter(Sci-Fi)
ScintillatingFiber Tracker
plane (fibe
r #)
Trigger Trigger7.5x7.5mm2
Trigger
(Sci Fi)
7.5x7.5mm2
Trigger
Y‐p
TriggeriTOP
Trigger
X‐plane (fiber #)
~30ps Full GEANT4 beamline MC
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Initial Raw Timing Distributions (cos()=0.5)
Data (Exp 10 = 1 shift) GEANT4‐based MC(limited to 50ns window)
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Analysis itemsy• Most of the waveforms look very clean
– Precise timebase/timing calibration needed– Leading edge timing extraction algorithmg g g g
• Photon yield (can do without precise timing)C i i• MC comparisons on‐going
• “direct” light is easy, mirror reflections more g y,complexB lit d t d b k d b• Beam quality good, study backgrounds by overlaying events
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One complication• At Super‐KEKB the timing of signals should be fixedrelative to trigger (system clock)
p
relative to trigger (system clock)– But it is random with respect to 21 MHz derived (Super‐KEKB RF clock). – thit from waveform must be combined with tFTSW from CAMAC TDC to align hit FTSW
events.– tglobal = thit + tftsw 21 MHz period (~50ns)
thit (ns, uncal.)19
Standard Laser Run ‐ DistributionsDST2‐Based Analysis
Black – laser run dataRed – profile histogram ofRed profile histogram of same data. Blue – linear fit
No fine calibration applied: assumed 2.7 GSa/s for all samples; 25 ps / count for CAMAC TDC.Time extracted by software fixed threshold discrimination (‐40 ADC counts).
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Phase Synchronous Triggering @ Beam Test
Signal Generator Laser Control Unit
Softwaretriggered.
Set to trigger on 1‐input only.
Signal Generator (Agilent 33250A)
Laser Control Unit (PiLas EIG1000D) Coincidence UnitMod3
Triggered synchronous w/ 21 MHz front end clock
Mod0
21 MHz front‐end clock.
Laser Head(PiLas PIL???S?S) Gate Generator
SL10s Quartz BarMod1
Mod2
FTSWCAT6 timing/trigger
CAMAC TDC ECL NIM
CAT6 timing/trigger
In this mode, the phase of 21 MHz clocks should be fixed
(25 ps least count) Converterrelative to the global trigger time.
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Phase Synchronous Triggering @ Beam Test
Signal Generator
Softwaretriggered.
Signal Generator (Agilent 33250A)Mod3
Triggered synchronous w/ 21 MHz front end clock
t = 140 ps
21 MHz front‐end clock.
Input is 5 0 V TTL
Output is 2.5 V pulse.
Input is 5.0 V TTL.
Probably contributed a large amount to the jitter.
Actual FTSW phase measurement jitter may have been less than this measurement.(Triggering for normal beam and laser runs did not have this trigger level issue.) 22
Phase Synchronous Triggering @ Hawaii
Gate Generator (To21 MHz
Gate Generator (To Provide Shorter Trigger Pulse)
Gate Generator(Latch Mode)FTSW
clock
Trigger in to FTSW21 MHz synchronous trigger Cable delayed
f
CAMAC TDC
triggeroutput from gate generator (to match
f TDC)(Phillips 7186) TDC startTDC stop range of TDC)
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Phase Synchronous Triggering @ Hawaii
Very fussy – could easily get > 100psWith poor connections/coupling
• Consistent with FTSW clock jitter measured on scope (and previous measurements in Nagoya). 24
Hawaii Test Setup – random phasep p
Signal Generator Pulser (Avtech
Signal generator runs asynchronously
Signal Generator (Agilent 33250A)
Pulser (AvtechAVMP‐2‐C‐EPIA) TTL NIM
Pulse sent to all ch. of 1 ASIC
Gate GeneratorMod2 Differentiator1 8 splitter
Fanout
FTSWCAT6 timing/trigger
NIM Trigger In
CAMAC TDC ECL NIM
21 MHz Latched TriggerTDC Start
TDC
(25 ps least count) Converter
Stop
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Measure & Apply Correction
Half of 1/(21 MHz)
For fixed amplitude, well behaved signal… in this case we estimateestimate:core sigma ~ 58 ps (73 ps RMS)
This timing calibration consistent all samples (32k samples, 128 unique timing)
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Previous result:N b f hit h l ( 0 5)Number of hit channels (cos=0.5)
DataSimulation
• Nhit~7 / 8 MCP‐PMTs (without PMT6)• Good agreement with simulation
(Histogram for simulation is scaled according to number of PMTs.)
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Extracting number of p.e.Preliminary!! Expectations: ~1 p.e. per PMT 1‐12
~0.4 p.e. per PMT 14‐24
I iti l
12 p.e. * ~82% electronics ~ 10 p.e.
Initial scan: charge sharing <~20%
Evidence for “cross talk” double‐hits
Work in progress
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Work in progress…
T‐1019 Preliminary Summary• Data taking completed less than 2 months ago (transit back recovery from spending holidays(transit back, recovery from spending holidays working…)
• About 534,000 events at normal incidence, ~300k at cos(theta)=0.5 ( )– Preliminary results show data clean, but two issues found: event time start trigger windowfound: event time start, trigger window
– Much analysis to be done – a very rich data set
/• Calibration & Debug at KEK/Hawaii• Setting up to extended cosmic running at KEKSetting up to extended cosmic running at KEK
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Lessons Learned: things to improveg p
• Timebase servo‐loopp– Firmware needs to be re‐writtenPossible hardware change– Possible hardware change
• Better thermal management (85C redline ops)• SCROD v2 (“final” form factor)• HV/packaging SL 10 into module by HPK/Nagoya• HV/packaging SL‐10 into module by HPK/Nagoya• Demonstrate DSP (real time) data reduction• In‐situ (on demand) calibration• Sample pointer dephasing fix (next slide)• Sample pointer dephasing fix (next slide)
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IRS3 Single Channel 32
• Sampling: 128 (2x 64) separate transfer lanes
Recording in one set 64, transferring other (“ping‐pong”)
separate transfer lanes
• Cleaned up input routing
• Storage: 64 x 512 (512 = 8 * 64)
p p g
Storage: 64 x 512 (512 8 64)
• Wilkinson (64x1): was (32x2)Wilkinson (64x1): was (32x2)• 64 conv/channel
bPID Short‐term Schedule2012 3 4 5 6 7 8 9 10 11 12
‐ Readout and structure confirmation
Prototype test‐ Cosmic ray‐ Beam test
Set up Data take
Beam testQBB, structure‐ Prototype
T t
DesigningStructure prototype
‐ AssemblyMCP‐PMT‐ B‐field test
Test
MeasurementB field test
Readout‐ Test System check
New version check with PMT Next version‐ PrototypeSoftware‐ Reconstruct
New version check with PMT
Prototype test
Next version
MC + exp. data studyReconstruct‐ Optimization Simmirror test
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Summaryy
• T 1019 beam test very valuable• T‐1019 beam test very valuable• Analysis pre‐prod prototypes in 2012
– Verify ASIC– Final board‐stack configurationFinal board stack configuration
• Continued cosmic ray testing at KEK; more i i / i hexperience operating/tuning the system
• Definitive beam test with real‐time feature extraction late 2012/early 2013
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Highly integrated readout
4x4 anode “1 inch”
CH1MCP-PMT (HPK SL-10)
6.4 psσ ~ 38 37RMS
CH2
σ ~ 38.37
36NIM A602 (2009) 438Single p.e. resolution
Back‐End Data Acquisition
• cPCI crate (above) with custom card (DSP_cPCI, left), that receives data from front end modules.
• This crate collects all data for the cosmic and beam testscosmic and beam tests.– Collects data from front‐end modules by
Giga‐bit fiber optic link.ll d– Collects CAMAC data via USB.
– Horizontal slice is “FINESSE” back‐end o o ta s ce s SS bac e dprototype for COPPER system
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Prototype HV/PMT issuesyp
• PMT case at HV• Pins not uniform diameter, location• Difficult to register 8 (32) onto a plane• No detailed information about anode
fi ti l t i kconfiguration – layout is guesswork (poor cross‐talk performance)• Took 4x iterations before “mostly
HV boardTook 4x iterations before mostly
solved” HV sparking/arcing issues (run VERY hot) • Working design does not fit in electronics envelopeW k ith HPK t k b MCP
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• Work with HPK to package bare MCP‐PMTs into an integrated module
Current Status: Calibrated time resolutionCurrent Status: Calibrated time resolution• Exp. 8 (normal incident), 4000 < event ID < 8000.
• Channel 9 of PMT 16.
• Only odd samples analyzed.
ents
mbe
r of e
ve
Preliminary
NumResolution = (123 ± 14) psec.
Need further investigation.Corrected time [nsec]
Need further investigation.Need extension to all good channels.
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Major (short‐term) milestonesSimplified TOP Electronics Schedule
2011 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012
Dec Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov
Complete beamtestComplete beamtest
Set‐up @ UH, KEK
Cal/T0 studies
Data Reprocess
Beamtest Analysis
C l l iComplete analysis
Intense WBS work
Complete WBS
BPAC Review
CDR Review
Pre CD‐1 Review
CD‐1 Review
Commission CRT run
Fast Feature Extract
TOP CRT run
CRT results (FFE)
IRS3 evaluation
SCROD Rev. B
Carrier Rev. B
Interconnect Rev. B
HV & integrate
Board stack V2
42IRSx Pre‐prod proto
DSP_FINESSE Rev B