Toggle Equivalence Preserving (TEP) Logic Optimization Eugene Goldberg (Cadence), Kanupriya Gulati...
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Transcript of Toggle Equivalence Preserving (TEP) Logic Optimization Eugene Goldberg (Cadence), Kanupriya Gulati...
![Page 1: Toggle Equivalence Preserving (TEP) Logic Optimization Eugene Goldberg (Cadence), Kanupriya Gulati (Texas A&M University) Sunil Khatri (Texas A&M University)](https://reader035.fdocuments.in/reader035/viewer/2022071716/56649ec55503460f94bcffc4/html5/thumbnails/1.jpg)
Toggle Equivalence Preserving (TEP) Logic Optimization
Eugene Goldberg (Cadence), Kanupriya Gulati (Texas A&M University)
Sunil Khatri (Texas A&M University)
IWLS-2007, San Diego, USA
This paper is available at http:/eigold.tripod.com/papers/iwls-2007-tep.pdf
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Summary
• Example of Logic Synthesis preserving Toggle Equivalence (LS_TE)
• Escaping Local Minima in LS_TE• Novel Convergence Scheme• TEP procedure (example)• Some experimental results
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Example
…
x1 xn
N1
N*1
Circuit N
square(x)
Circuit N*
abs(x)
…
x1 xn
…y1 y2n …y*1 y*n
y < 100 y* < 10N2N*2
z z
Subcircuit N1 is toggle equivalent to N*1. Subcircuit N2 is toggle equivalent to N*2 (under “allowable” input assignments)
square(x) < 100 abs(x) < 10
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Logic Synthesis preserving Toggle Equivalence (LS_TE)
Given a single-output combinational circuit N partitioned into subcircuits N1,..,Nk, LS_TE is to produce a new circuit N* :
replace each Ni with an optimized toggle equivalent N*i.
Single-output subcircuits: Toggle equivalence functional equivalence (modulo negation).
Multi-output subcircuits Ni and N*i are toggle equivalent
if Ni(p ) Ni(p ) N*i(p ) N*i (p ).
Definition of toggle equivalence can be extended to the case when Ni and Ni* have different input variables but there is a one-to-one mapping between “allowed” input assignments.
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Importance of LS_TE (escaping local minima)
…x1 xn
N1 square(x)
…y1 y2n
y < 100N2
abs(x)
…x1 xn
…y*1 y*n
R*1
N*1abs(x)
…x1 xn
…y*1 y*n
y* < 10N*2
N*1
Re-encoder
…y1 y2n
y < 100N2
z
z z
z*Re-encoder
R*2
Even if |N*i| < |Ni|, it maybe the case that |N*i| + |R*i| > |Ni|
In terms of equivalent transformations, LS_TE may
temporarily increase the circuit size.
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TEP procedure (first introduction)
…
x1 xn
M
…y1 yp
…
x1 xn
M*
…y*1 y*m
Let M be a subcircuit Ni of N. For the sake of simplicity, we assume that M and M* have identical variables.
Problem: Given a multi-output circuit M, build an (optimized) toggle equivalent circuit M*.
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Toggle Implication
Toggle implication (denoted M M* )
M(p ) M(p ) M*(p ) M*(p ).
M and M* are toggle equivalent iff
M M* and M* M
Strict toggle implication (denoted M < M* )
if M M* is true, but M* M is not
M, M* are multi-output circuits
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Novel Convergence SchemeA TEP procedure, in general, can not re-use the structure of M. Then we need to sovle the convergence problem.
Alternatively, the convergence problem is solved by severely restricting the class of implementations we consider. In SIS, it is sums-of-products. In BDDs, it is networks of multiplexers.
We build a sequence of circuits M1,…,Md such that
a) M Mi and b) Mi < Mi-1
This sequence converges to a circuit M* such that
a) M M* and b) M* M.
Usually, the convergence problem is avoided by making functionally equivalent, incremental transformations.
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Example
M1 = identity; // so M M1
repeat
{M = rem_toggles(Mi);
Mi+1= add_toggles(M );}until (Mi+1 M)
Targe circuit M* implements x1 x2
M1
M
M2
Init. circuit
First iter.
rem_toggles
add_toggles
Second iter.
M3
rem_toggles
![Page 10: Toggle Equivalence Preserving (TEP) Logic Optimization Eugene Goldberg (Cadence), Kanupriya Gulati (Texas A&M University) Sunil Khatri (Texas A&M University)](https://reader035.fdocuments.in/reader035/viewer/2022071716/56649ec55503460f94bcffc4/html5/thumbnails/10.jpg)
Experimental Results
We successfully applied our TEP procedure
a) to simplify large circuits implementing redundant
arithmetic expressions
b) to optimize small single-output circuits (up to 8 inputs)
c) to build toggle equivalent counterparts of small
multi-output circuits
d) to optimize a cascade of two circuits by LS_TE (TEP procedure was used twice)
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Conclusions
• Our TEP procedure can be used for developing new structure-agnostic synthesis algorithms
• Besides, TEP procedure enables a powerful method of logic synthesis (LS_TE).
• LS_TE suggests a way to address local minimum entrapment problem
• LS_TE facilitates informational exchange with the designer (specification describes high-level structure of the circuit)