Today's FPGA Ecosystem - Neeraj Varma, Xilinx

Xilinx OverviewNeeraj Varma, Country Manager – Sales (India, Australia, New Zealand)

May 2010

Agenda

The Programmable Imperative: The Next Wave

Xilinx Product Strategy

Technology Roadmap

Xilinx in India

The Programmable Imperative: The Next WaveThe Next Wave

Decline of ASICs, Challenged ASSP Business FPGAs Closing the Gap with ASICs/ASSPsg p

ASIC landscape continues to deteriorateASIC landscape continues to deteriorateWith each process node, the ASIC business model is in jeopardy

ASSP business model is challenged Suppliers profitability and long term viability is at stake

Increasing FPGA penetration by nodeExcellent FPGA coverage of technology and businessExcellent FPGA coverage of technology and business

Historically the Industry has “Cried Wolf”…

y yNow the Industry is Starting to Deliver to Expectations

FPGA Coverage of ASIC / ASSPs is Growing

FPGA Process Node

Technology Attribute 90nm 65nm 40nm 28nm

Analog

Processor

System PowerSystem Power

Memory

Total Cost

Gate Count <25% 25%-50% 50%-75% >75%Clock Speed

Interface ProtocolsInterface Protocols

DSP Capability

Pin Count

Source: Xilinx Internal Estimates

At Each Process Node, FPGAs Address an Increasing % of ASIC/ASSP Designs

Fiscal Year Revenues

$1,825

$568

1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009

1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009

Xilinx Revenue BreakdownQ4 Calendar Year 2009

Revenue by Geography Revenue by End Market

Japan Asia Pacific

Consumer& AutoData

Processing Industrial& Other

15%7%

32%

36%

20%

9%Europe& Other

46%35%

North America Communications

Source: Xilinx, Inc.

Programmable Device Market Segment ShareQ4 Calendar Year 2009

L tti

PLD Segment FPGA SegmentLatticeActel Others: 1%

6% 6%Xilinx

51%36%

53%

11%

XilinxAltera

Altera

AllOthers

36%11%

Xilinx revenues are greater than all other pure-play PLD companies combined.

Pag

Source: Company reportsLatest information available; computed on a 4-quarter rolling basis

Xilinx Product Strategygy

Xilinx Product Strategy Overview

Improve Power / Performance / Price Increase ProductivityPower / Performance / Price by riding the leading edge of

process technology

Increase Productivity with Targeted Design

Platforms

Market-Specific

Application

Base Platform

Domain-Specific

Base Platform

Provide customers with early access to silicon and development tools

Raise the starting point for key vertical applications

Page 10

pat each node

Targeted Design PlatformsEnabling Customers to Innovate Faster

C i ti Vid AVB

Focus on DifferentiationApplication

Application Embedded DSP Connectivity

ApplicationCommunication • Video • AVB

Market specific IP, custom tools, custom boardsMarket‐specific

Silicon Family +B IP ISE b b d

pp Embedded • DSP • ConnectivityDomain IP, Domain tools,

FMC daughter cardsDomain‐specific

Base IP, ISE program, base boardsBase Platform

Greater Capacity and Performance at Every Node

Virtex-6

LXVirtex-4

LXLXTSXTFXT

Virtex-5LXTSXTHXT

orm

ance

Spartan-33

3E3A/N

SXFX

FXTTXT

LXLXT

Spartan-6

Per

fo

65nm 45/40nm90nm

3A/N3ADSP

Page 12

Over 1Tbps IO bandwidth

ARM and Xilinx Collaboration is a Key Enabler

Optimized interconnect Industry’s best embeddedOptimized interconnect standard for FPGAs– Next-generation AMBA

Enables Socketable IP

Industry s best embedded processor roadmap and

FPGA fabricEmbedded Processing PlatformEnables Socketable IP Embedded Processing Platform

Robust ecosystem of tools, IP and programmers ARM Connected Community

Page 13

yand Xilinx Partners

Enabling a Vibrant Ecosystem

Open, standards-based platforms

Licensing / IP protectionLicensing / IP protection

New business models

Page 14

Unparalleled Support, Training and ServicesHelps You Accelerate FPGA Projects

Most services available in India – delivered through local resources

Technology Roadmapgy p

Strategy for Sustained Leadership

Rid th l di d C ti d i tiRide the leading edge of process technology

Continued innovationbeyond silicon

Unified, power-efficient architecture

Page 17

Unified Architecture at 28nm and Beyond

Virtex-6

28nmGen

IP

LXVirtex-4

LXLXTSXTFXT

Virtex-5 LXTSXTHXT

Spartan-33

3E

LXSXFX

FXTTXT

LXLXT

Spartan-6

IP

65nm 45/40nm 28nm90nm

3E3A/N

3ADSPLXT

Unified Architecture Enables Design and IP Migration Across Families

Major Focus on Power Reduction at 28nmdu

ctio

n

0.8

1.0

Pow

er R

ed

0.4

0.6

50% dd’l

50%power

reduction

Rel

ativ

e

0.2

50% add’l power reduction

90nm 65nm 40nm / 45nm 28nm

Page 19

Rapid Progress on 28nm

Rigorous Test Vehicle Development Methodology– Confirm product power, functionality, and performance targets

2010 delivery– Software support in mid-2010

Software support in mid 2010– Initial silicon samples in 2010

Productivity Improvements in ISE

ISE 12.1 (Now!)– Reduced run time

for large designs– Power reduction

Runtime(hrs)24

Implementation Runtime Normalized to ISE 11.1 3.8

capability– Design partitioning

supportP ti l

12

18

2.1

– Partial reconfiguration

– Spartan-6 and Virtex-6 QoR

330K LCs

330K LCs

330K LCs

6330K LCs

330K LCs

1.00.7

Virtex-6 QoRenhancements 20082007 2009 2010 2011

ISE12.1ISE11.1ISE10.1ISE9.1i

Xilinx in India

Expansion of India Development Centre

Technical Support Centre – Investments aligned with growing needs

f l l t bof local customer baseRobust engineering resources– Key contributor to delivery of current and

next generation Targeted Designnext generation Targeted Design Platforms

– IC Design, IP, SW, systems and application developmentpp p

Doubled workforce in last 12 months– Tapping into rich local talent pool– Increasing employee base to 260g p y

Expanding facility – 57,000 sq. ft. total available space– Capacity for up to 456 employees

Capacity for up to 456 employees

Thriving India Ecosystem

Leading technology developers for digital convergence– 15 Alliance member companies

• IP, design services, EDA, boards

– Joint go-to-market programs – Fertile partnership opportunities

Key Xilinx vertical solutions delivered by partners in IndiaEstablishing scalable and robust 3rd party partner business modelsEstablishing scalable and robust 3rd party partner business models Active Xilinx University Program (XUP)– 500 engineering institutes in India and growing– Best practices exchange between universities in India & abroad

The Programmable Imperative is Here Today

Insatiable bandwidth

Xilinx is a

FPGA price/performance/power improving at each node

Xilinx is a strategic choice

Fewer ASSPs to choose from, ASICs too risky

Increasing productivity with Targeted Design Platforms

and Xilinx Support

Page 25

Thank You

[email protected]

Today's FPGA Ecosystem - Neeraj Varma, Xilinx

Technology

Transcript of Today's FPGA Ecosystem - Neeraj Varma, Xilinx