TMS320F2837xS Delfino™ Microcontrollers...TMS320F2837xS Delfino Microcontrollers 1 Device Overview...

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

TMS320F28379S, TMS320F28378S, TMS320F28377STMS320F28376S, TMS320F28375S, TMS320F28374S

SPRS881D –AUGUST 2014–REVISED JULY 2017

TMS320F2837xS Delfino™ Microcontrollers

1 Device Overview

1

1.1 Features1

• TMS320C28x 32-Bit CPU– 200 MHz– IEEE 754 Single-Precision Floating-Point Unit

(FPU)– Trigonometric Math Unit (TMU)– Viterbi/Complex Math Unit (VCU-II)

• Programmable Control Law Accelerator (CLA)– 200 MHz– IEEE 754 Single-Precision Floating-Point

Instructions– Executes Code Independently of Main CPU

• On-Chip Memory– 512KB (256KW) or 1MB (512KW) of Flash

(ECC-Protected)– 132KB (66KW) or 164KB (82KW) of RAM

(ECC-Protected or Parity-Protected)– Dual-Zone Security Supporting Third-Party

Development• Clock and System Control

– Two Internal Zero-Pin 10-MHz Oscillators– On-Chip Crystal Oscillator– Windowed Watchdog Timer Module– Missing Clock Detection Circuitry

• 1.2-V Core, 3.3-V I/O Design• System Peripherals

– Two External Memory Interfaces (EMIFs) WithASRAM and SDRAM Support

– 6-Channel Direct Memory Access (DMA)Controller

– Up to 169 Individually Programmable,Multiplexed General-Purpose Input/Output(GPIO) Pins With Input Filtering

– Expanded Peripheral Interrupt Controller (ePIE)– Multiple Low-Power Mode (LPM) Support With

External Wakeup• Communications Peripherals

– USB 2.0 (MAC + PHY)– Support for 12-Pin 3.3 V-Compatible Universal

Parallel Port (uPP) Interface– Two Controller Area Network (CAN) Modules

(Pin-Bootable)– Three High-Speed (up to 50-MHz) SPI Ports

(Pin-Bootable)– Two Multichannel Buffered Serial Ports

(McBSPs)

– Four Serial Communications Interfaces(SCI/UART) (Pin-Bootable)

– Two I2C Interfaces (Pin-Bootable)• Analog Subsystem

– Up to Four Analog-to-Digital Converters (ADCs)– 16-Bit Mode

– 1.1 MSPS Each (up to 4.4-MSPS SystemThroughput)

– Differential Inputs– Up to 12 External Channels

– 12-Bit Mode– 3.5 MSPS Each (up to 14-MSPS System

Throughput)– Single-Ended Inputs– Up to 24 External Channels

– Single Sample-and-Hold (S/H) on Each ADC– Hardware-Integrated Post-Processing of ADC

Conversions– Saturating Offset Calibration– Error From Setpoint Calculation– High, Low, and Zero-Crossing Compare,

With Interrupt Capability– Trigger-to-Sample Delay Capture

– Eight Windowed Comparators With 12-BitDigital-to-Analog Converter (DAC) References

– Three 12-Bit Buffered DAC Outputs• Enhanced Control Peripherals

– 24 PWM Channels With Enhanced Features– 16 High-Resolution Pulse Width Modulator

(HRPWM) Channels– High Resolution on Both A and B Channels of

8 PWM Modules– Dead-Band Support (on Both Standard and

High Resolution)– Six Enhanced Capture (eCAP) Modules– Three Enhanced Quadrature Encoder Pulse

(eQEP) Modules– Eight Sigma-Delta Filter Module (SDFM) Input

Channels, 2 Parallel Filters per Channel– Standard SDFM Data Filtering– Comparator Filter for Fast Action for Out of

Range

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2

TMS320F28379S, TMS320F28378S, TMS320F28377STMS320F28376S, TMS320F28375S, TMS320F28374SSPRS881D –AUGUST 2014–REVISED JULY 2017 www.ti.com

Submit Documentation FeedbackProduct Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28376S TMS320F28375S

TMS320F28374S

Device Overview Copyright © 2014–2017, Texas Instruments Incorporated

• Package Options:– Lead-Free, Green Packaging– 337-Ball New Fine Pitch Ball Grid Array

(nFBGA) [ZWT Suffix]– 176-Pin PowerPAD™ Thermally Enhanced Low-

Profile Quad Flatpack (HLQFP)[PTP Suffix]

– 100-Pin PowerPAD Thermally Enhanced ThinQuad Flatpack (HTQFP) [PZP Suffix]

• Temperature Options:– T: –40ºC to 105ºC Junction– S: –40ºC to 125ºC Junction– Q: –40ºC to 125ºC Free-Air

(AEC Q100 Qualification for AutomotiveApplications)

1.2 Applications• Advanced Driver Assistance Systems (ADAS)• Building Automation• Electronic Point of Sale• Electric Vehicle/Hybrid Electric Vehicle (EV/HEV)

Powertrain• Factory Automation• Grid Infrastructure

• Industrial Transport• Medical, Healthcare and Fitness• Motor Drives• Power Delivery• Telecom Infrastructure• Test and Measurement

1.3 DescriptionThe Delfino™ TMS320F2837xS is a powerful 32-bit floating-point microcontroller unit (MCU) designed foradvanced closed-loop control applications such as industrial drives and servo motor control; solarinverters and converters; digital power; transportation; and power line communications. Completedevelopment packages for digital power and industrial drives are available as part of the powerSUITE andDesignDRIVE initiatives.

The real-time control subsystem is based on TI’s 32-bit C28x floating-point CPU, which provides 200 MHzof signal processing performance. The C28x CPU is further boosted by the new TMU accelerator, whichenables fast execution of algorithms with trigonometric operations common in transforms and torque loopcalculations; and the VCU accelerator, which reduces the time for complex math operations common inencoded applications.

The F2837xS microcontroller family features a CLA real-time control coprocessor. The CLA is anindependent 32-bit floating-point processor that runs at the same speed as the main CPU. The CLAresponds to peripheral triggers and executes code concurrently with the main C28x CPU. This parallelprocessing capability can effectively double the computational performance of a real-time control system.By using the CLA to service time-critical functions, the main C28x CPU is free to perform other tasks, suchas communications and diagnostics.

The TMS320F2837xS supports up to 1MB (512KW) of onboard flash memory with error correction code(ECC) and up to 164KB (82KW) of SRAM. Two 128-bit secure zones are also available on the CPU forcode protection.

Performance analog and control peripherals are also integrated on the F2837xS MCU to further enablesystem consolidation. Four independent 16-bit ADCs provide precise and efficient management of multipleanalog signals, which ultimately boosts system throughput. The new sigma-delta filter module (SDFM)works in conjunction with the sigma-delta modulator to enable isolated current shunt measurements. TheComparator Subsystem (CMPSS) with windowed comparators allows for protection of power stages whencurrent limit conditions are exceeded or not met. Other analog and control peripherals include DACs,PWMs, eCAPs, eQEPs, and other peripherals.

Peripherals such as EMIFs, CAN modules (ISO 11898-1/CAN 2.0B-compliant), and a new uPP interfaceextend the connectivity of the F2837xS. The uPP interface is a new feature of the C2000™ MCUs andsupports high-speed parallel connection to FPGAs or other processors with similar uPP interfaces. Lastly,a USB 2.0 port with MAC and PHY lets users easily add universal serial bus (USB) connectivity to theirapplication.

http://www.ti.com/product/tms320f28379s?qgpn=tms320f28379shttp://www.ti.com/product/tms320f28378s?qgpn=tms320f28378shttp://www.ti.com/product/tms320f28377s?qgpn=tms320f28377shttp://www.ti.com/product/tms320f28376s?qgpn=tms320f28376shttp://www.ti.com/product/tms320f28375s?qgpn=tms320f28375shttp://www.ti.com/product/tms320f28374s?qgpn=tms320f28374shttp://www.ti.comhttp://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SPRS881D&partnum=TMS320F28379Shttp://www.ti.com/product/tms320f28379s?qgpn=tms320f28379shttp://www.ti.com/product/tms320f28378s?qgpn=tms320f28378shttp://www.ti.com/product/tms320f28377s?qgpn=tms320f28377shttp://www.ti.com/product/tms320f28376s?qgpn=tms320f28376shttp://www.ti.com/product/tms320f28375s?qgpn=tms320f28375shttp://www.ti.com/product/tms320f28374s?qgpn=tms320f28374shttp://www.ti.com/lsds/ti/applications/automotive/adas/overview.pagehttp://www.ti.com/lsds/ti/applications/industrial/building-automation/overview.pagehttp://www.ti.com/lsds/ti/applications/industrial/epos/overview.pagehttp://www.ti.com/lsds/ti/applications/automotive/hev-ev-powertrain/overview.pagehttp://www.ti.com/lsds/ti/applications/automotive/hev-ev-powertrain/overview.pagehttp://www.ti.com/lsds/ti/applications/industrial/factory-automation/overview.pagehttp://www.ti.com/lsds/ti/applications/industrial/grid-infrastructure/overview.pagehttp://www.ti.com/lsds/ti/applications/industrial/industrial-transport/overview.pagehttp://www.ti.com/lsds/ti/applications/industrial/medical/overview.pagehttp://www.ti.com/lsds/ti/applications/industrial/motor-drives/overview.pagehttp://www.ti.com/lsds/ti/applications/industrial/power-delivery/overview.pagehttp://www.ti.com/lsds/ti/applications/communications-equipment/telecom-infrastructure/overview.pagehttp://www.ti.com/lsds/ti/applications/industrial/test-measurement/overview.pagehttp://www.ti.com/lsds/ti/microcontrollers_16-bit_32-bit/c2000_performance/real-time_control/applications.page#driveshttp://www.ti.com/lsds/ti/microcontrollers_16-bit_32-bit/c2000_performance/real-time_control/applications.page#solarhttp://www.ti.com/lsds/ti/microcontrollers_16-bit_32-bit/c2000_performance/real-time_control/applications.page#solarhttp://www.ti.com/lsds/ti/microcontrollers_16-bit_32-bit/c2000_performance/real-time_control/applications.page#digihttp://www.ti.com/lsds/ti/microcontrollers_16-bit_32-bit/c2000_performance/real-time_control/applications.page#transportationhttp://www.ti.com/lsds/ti/microcontrollers_16-bit_32-bit/c2000_performance/real-time_control/applications.page#plchttp://www.ti.com/tool/powersuitehttp://www.ti.com/tool/designdrive

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TMS320F28374S

Device OverviewCopyright © 2014–2017, Texas Instruments Incorporated

(1) For more information on these devices, see Mechanical Packaging and Orderable Information.

Device Information (1)PART NUMBER PACKAGE BODY SIZE

TMS320F28379SZWT nFBGA (337) 16.0 mm × 16.0 mmTMS320F28378SZWT nFBGA (337) 16.0 mm × 16.0 mmTMS320F28377SZWT nFBGA (337) 16.0 mm × 16.0 mmTMS320F28376SZWT nFBGA (337) 16.0 mm × 16.0 mmTMS320F28375SZWT nFBGA (337) 16.0 mm × 16.0 mmTMS320F28374SZWT nFBGA (337) 16.0 mm × 16.0 mmTMS320F28379SPTP HLQFP (176) 24.0 mm × 24.0 mmTMS320F28378SPTP HLQFP (176) 24.0 mm × 24.0 mmTMS320F28377SPTP HLQFP (176) 24.0 mm × 24.0 mmTMS320F28376SPTP HLQFP (176) 24.0 mm × 24.0 mmTMS320F28375SPTP HLQFP (176) 24.0 mm × 24.0 mmTMS320F28374SPTP HLQFP (176) 24.0 mm × 24.0 mmTMS320F28379SPZP HTQFP (100) 14.0 mm × 14.0 mmTMS320F28377SPZP HTQFP (100) 14.0 mm × 14.0 mmTMS320F28376SPZP HTQFP (100) 14.0 mm × 14.0 mmTMS320F28375SPZP HTQFP (100) 14.0 mm × 14.0 mmTMS320F28374SPZP HTQFP (100) 14.0 mm × 14.0 mm

http://www.ti.com/product/tms320f28379s?qgpn=tms320f28379shttp://www.ti.com/product/tms320f28378s?qgpn=tms320f28378shttp://www.ti.com/product/tms320f28377s?qgpn=tms320f28377shttp://www.ti.com/product/tms320f28376s?qgpn=tms320f28376shttp://www.ti.com/product/tms320f28375s?qgpn=tms320f28375shttp://www.ti.com/product/tms320f28374s?qgpn=tms320f28374shttp://www.ti.comhttp://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SPRS881D&partnum=TMS320F28379Shttp://www.ti.com/product/tms320f28379s?qgpn=tms320f28379shttp://www.ti.com/product/tms320f28378s?qgpn=tms320f28378shttp://www.ti.com/product/tms320f28377s?qgpn=tms320f28377shttp://www.ti.com/product/tms320f28376s?qgpn=tms320f28376shttp://www.ti.com/product/tms320f28375s?qgpn=tms320f28375shttp://www.ti.com/product/tms320f28374s?qgpn=tms320f28374s

16-/12-bit ADC

x4

ADC

Result

Regs

Peripheral Frame 1

GPIO MUX, Input X-BAR, Output X-BAR

Secure Memories

shown in Red

CPU1 BusesComparator

Subsystem

(CMPSS)

DAC

x3

Config

Data BusBridge

ePWM-1/../12eCAP-

1/../6eQEP-1/2/3

HRPWM-1/../8

SDFM-1/2

EX

TS

YN

CIN

EX

TS

YN

CO

UT

TZ

1-T

Z6

EC

AP

x

EQ

EP

xA

EQ

EP

xB

EP

WM

xA

EP

WM

xB

EQ

EP

xI

EQ

EP

xS

SD

x_

Dy

SD

x_

Cy

SCI-

A/B/C/D

(16L FIFO)

I2C-A/B

(16L FIFO)

Data Bus Bridge

SC

ITX

Dx

SC

IRX

Dx

SD

Ax

SC

Lx

CAN-

A/B(32-MBOX)

Data BusBridge

CA

NR

Xx

CA

NT

Xx

Data BusBridge

US

BD

P

US

BD

M

USB

Ctrl /

PHY

GPIO

Data BusBridge

GP

IOn

EMIF1

Data BusBridge

EM

1D

x

EM

1A

x

EM

1C

TL

x

EMIF2

Data BusBridge

EM

2D

x

EM

2A

x

EM

2C

TL

x

A

D

B

C

JTAG

AUXCLKIN

External Crystal orOscillator

Watchdog

Main PLL

Aux PLL

INTOSC1

INTOSC2

Low-PowerMode Control

GPIO MUX

TRST

TCK

TDI

TMS

TDO

MEMCPU1

Global Shared

16x 4Kx16

GS0-GS15 RAMs

CP

U1.C

LA

1B

us

C28 CPU-1

CPU Timer 0

CPU Timer 1

CPU Timer 2

ePIE(up to 192

interrupts)

WD Timer

NMI-WDT

CPU1.CLA1 Data ROM

(4Kx16)

CPU1.CLA1 to CPU1

128x16 MSG RAM

CPU1 to CPU1.CLA1

128x16 MSG RAM

Boot-ROM 32Kx16

Nonsecure

Secure-ROM 32Kx16

Secure

CPU1.M0 RAM 1Kx16

CPU1.M1 RAM 1Kx16

CPU1.D0 RAM 2Kx16

CPU1.D1 RAM 2Kx16

CPU1 Local Shared

6x 2Kx16

LS0-LS5 RAMs

CPU1.CLA1

CPU1.DMA

PSWD

DualCode

SecurityModule

+Emulation

CodeSecurity

Logic(ECSL)

PUMP

Flash Bank 0256K x 16

Secure

(F28377S, F23875S only)

256K x 16Secure

Flash Bank 1

User-ConfigurableDCSMOTP

1K x 16

(F28378S, F28377S, andF28375S only)

Flash Wrapper forBank 1

Flash Wrapper forBank 0

FPUVCU-IITMU

Analog

MUX

A5:0

B5:0

C5:2

ADCIN14

ADCIN15

D5:0

Peripheral Frame 2

SPI-

A/B/C

(16L FIFO)S

PIS

IMO

x

SP

ISO

MIx

SP

ICL

Kx

SP

IST

Ex

McBSP-A/B

MD

Xx

MR

Xx

MC

LK

Xx

MC

LK

Rx

MF

SX

x

MF

SR

x

UP

PA

D[7

:0]

UP

PA

CL

K

UP

PA

EN

UP

PA

WT

UP

PA

ST

uPPRAM

Copyright © 2017, Texas Instruments Incorporated

4



TMS320F28374S

Device Overview Copyright © 2014–2017, Texas Instruments Incorporated

1.4 Functional Block DiagramFigure 1-1 shows the CPU system and associated peripherals.

Figure 1-1. Functional Block Diagram


5




TMS320F28374S

Table of ContentsCopyright © 2014–2017, Texas Instruments Incorporated

Table of Contents1 Device Overview ......................................... 1

1.1 Features .............................................. 11.2 Applications........................................... 21.3 Description............................................ 21.4 Functional Block Diagram ........................... 4

2 Revision History ......................................... 63 Device Comparison ..................................... 7

3.1 Related Products ..................................... 94 Terminal Configuration and Functions ............ 10

4.1 Pin Diagrams........................................ 104.2 Signal Descriptions.................................. 174.3 Pins With Internal Pullup and Pulldown............. 404.4 Pin Multiplexing...................................... 414.5 Connections for Unused Pins ....................... 48

5 Specifications ........................................... 495.1 Absolute Maximum Ratings ........................ 495.2 ESD Ratings – Commercial ......................... 505.3 ESD Ratings – Automotive.......................... 505.4 Recommended Operating Conditions............... 515.5 Power Consumption Summary...................... 525.6 Electrical Characteristics ............................ 565.7 Thermal Resistance Characteristics ................ 575.8 System .............................................. 595.9 Analog Peripherals .................................. 945.10 Control Peripherals ................................ 1205.11 Communications Peripherals ...................... 137

6 Detailed Description.................................. 1736.1 Overview ........................................... 173

6.2 Functional Block Diagram ......................... 1736.3 Memory ............................................ 1756.4 Identification........................................ 1836.5 Bus Architecture – Peripheral Connectivity........ 1846.6 C28x Processor .................................... 1856.7 Control Law Accelerator ........................... 1886.8 Direct Memory Access............................. 1896.9 Boot ROM and Peripheral Booting................. 1916.10 Dual Code Security Module ....................... 1946.11 Timers.............................................. 1946.12 Nonmaskable Interrupt With Watchdog Timer

(NMIWD) ........................................... 1946.13 Watchdog .......................................... 1956.14 Configurable Logic Block (CLB) ................... 195

7 Applications, Implementation, and Layout ...... 1967.1 TI Design or Reference Design.................... 196

8 Device and Documentation Support .............. 1978.1 Device and Development Support Tool

Nomenclature ...................................... 1978.2 Tools and Software ................................ 1988.3 Documentation Support............................ 2008.4 Related Links ...................................... 2018.5 Community Resources............................. 2018.6 Trademarks ........................................ 2018.7 Electrostatic Discharge Caution ................... 2018.8 Glossary............................................ 201

9 Mechanical Packaging and OrderableInformation ............................................. 2029.1 Packaging Information ............................. 202


6



TMS320F28374S

Revision History Copyright © 2014–2017, Texas Instruments Incorporated

2 Revision History

Changes from May 6, 2016 to July 25, 2017 (from C Revision (May 2016) to D Revision) Page

• Global: Added TMS320F28378S................................................................................................... 1• Global: Restructured document. ................................................................................................... 1• Section 1.2 (Applications): Updated section. ..................................................................................... 2• Section 4.1 (Pin Diagrams): Added NOTE about PowerPAD. ................................................................ 15• Table 4-1 (Signal Descriptions): Updated DESCRIPTION of VREFHIA, VREFHIB, VREFHIC, VREFHID, XRS, VREGENZ,

VSS, and VSSA......................................................................................................................... 17• Table 4-1: Updated MUX POSITION of GPIO22–GPIO23, GPIO87–GPIO99. ............................................. 17• Table 4-7 (Connections for Unused Pins): Updated ACCEPTABLE PRACTICE column of VREGENZ................. 48• Section 5.2 (ESD Ratings – Commercial): Added table. ...................................................................... 50• Section 5.3 (ESD Ratings – Automotive): Changed title from "ESD Ratings" to "ESD Ratings – Automotive". ....... 50• Section 5.8.1 (Power Sequencing): Updated "The voltage on VDDIO should be greater than VDD ..." paragraph. ...... 59• Table 5-7 (Input Clock Frequency): f(X1) for PLL enabled: Changed MAX value from 20 MHz to 25 MHz. ............. 64• Table 5-12 (Internal Clock Frequencies): Updated f(AUXPLL). ................................................................... 65• Table 5-12: Added footnote about using INTOSC1 or INTOSC2 as clock source. ........................................ 65• Table 5-18 (Internal Oscillator Electrical Characteristics): Updated table. .................................................. 68• Section 5.8.4 (Flash Parameters): Added NOTE about Main Array flash programming. ................................. 69• Table 5-20 (Flash Parameters): Changed table title from "Flash Parameters at 200 MHz" to "Flash Parameters".

Updated table and footnotes....................................................................................................... 69• Table 5-20: Moved data from "Flash/OTP Endurance" table and "Flash Data Retention Duration" table into

"Flash Parameters" table. Removed "Flash/OTP Endurance" table and "Flash Data Retention Duration" table ...... 69• Section 5.8.5 (Emulation/JTAG): Added link to "Hardware Breakpoints and Watchpoints for C28x in CCS" website. 70• Section 5.8.9.2 (Synchronous DRAM Support): Updated section. ........................................................... 86• Table 5-37 (EMIF Asynchronous Memory Timing Requirements): Added "E = EMxCLK period in ns" footnote. ..... 87• Table 5-41 (ADC Operating Conditions (16-Bit Differential Mode)): Updated Sample window duration. Added

footnote about sample window. .................................................................................................. 100• Table 5-43 (ADC Operating Conditions (12-Bit Single-Ended Mode)): Updated Sample window duration. Added

footnote about sample window. .................................................................................................. 102• Table 5-48 (Per-Channel Parasitic Capacitance): Added footnote about increased capacitance....................... 105• Table 5-52 (Comparator Electrical Characteristics): Updated footnote about hysteresis. ............................... 113• Figure 5-47 (ePWM Submodules and Critical Internal Signal Interconnects): Changed "CTR=CPMC" to

"CTR=CMPC". Changed "CTR=CPMD" to "CTR=CMPD". .................................................................. 124• Figure 5-48 (ePWM Trip Input Connectivity): Removed TRIP13 from "All ePWM Modules" block. ................... 125• Table 5-61 (eQEP Timing Requirements): Changed "Synchronous" to "Asynchronous/Synchronous". ............... 131• Table 5-61: Added footnote about limitations in the asynchronous mode. ................................................ 131• Table 5-63 (High-Resolution PWM Characteristics): Updated footnote. ................................................... 132• Section 5.11.5 (Serial Peripheral Interface (SPI)): Updated "Rising edge with phase delay" clocking scheme. ..... 153• Section 5.11.5.1 (SPI Electrical Data and Timing): Updated section. ...................................................... 155• Figure 5-69 (SPI Master Mode External Timing (Clock Phase = 1)): Updated figure. ................................... 158• Figure 5-71 (SPI Slave Mode External Timing (Clock Phase = 1)): Updated figure. .................................... 160• Figure 5-73 (High-Speed SPI Master Mode External Timing (Clock Phase = 1)): Updated figure. .................... 163• Figure 5-75 (High-Speed SPI Slave Mode External Timing (Clock Phase = 1)): Updated figure. ..................... 165• Table 6-2 (Addresses of Flash Sectors on F28379S, F28378S, F28377S, and F28375S): Changed "TI OTP

Bank 1", "User configurable DCSM OTP Bank 1", "TI OTP ECC Bank 1", and "User-configurable DCSM OTPECC Bank 1" to "Reserved". Added footnote about ECC error event. ..................................................... 176

• Table 6-4 (EMIF Chip Select Memory Map): Updated SIZE and END ADDRESS of EMIF2_CS0n - Data. .......... 178• Table 6-4: Added footnote about memory size and pin mux setting. ....................................................... 178• Table 6-4: Added footnote about memory size and byte enables. ......................................................... 178• Table 6-8 (Device Identification Registers): Added JTAG ID. ............................................................... 183• Section 8.2 (Tools and Software): Updated section. ......................................................................... 198


7




TMS320F28374S

Device ComparisonCopyright © 2014–2017, Texas Instruments Incorporated

(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minordifferences between devices that do not affect the basic functionality of the module. For more information, see the C2000 Real-TimeControl Peripherals Reference Guide.

(2) Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.

3 Device Comparison

Table 3-1 lists the features of each 2837xS device.

Table 3-1. Device Comparison

FEATURE (1) 28379S 28378S 28377S 28376S 28375S 28374S

Package Type(ZWT is an nFBGA package.PTP is an HLQFP package.PZP is an HTQFP package.)

337-BallZWT

176-PinPTP

100-PinPZP

337-BallZWT

176-PinPTP

337-BallZWT

176-PinPTP

100-PinPZP

337-BallZWT

176-PinPTP

100-PinPZP

337-BallZWT

176-PinPTP

100-PinPZP

337-BallZWT

176-PinPTP

100-PinPZP

Processor and Accelerators

C28x

Number 1

Frequency (MHz) 200

Floating-Point Unit(FPU) Yes

VCU-II Yes

TMU – Type 0 Yes

CLA – Type 1Number 1

Frequency (MHz) 200

6-Channel DMA – Type 0 1

Memory

Flash (16-bit words) 1MB (512KW) 1MB (512KW) 1MB (512KW) 512KB (256KW) 1MB (512KW) 512KB (256KW)

RAM(16-bit words)

Dedicated and LocalShared RAM 36KB (18KW)

Global Shared RAM 128KB (64KW) 128KB (64KW) 128KB (64KW) 96KB (48KW) 128KB (64KW) 96KB (48KW)

Total RAM 164KB (82KW) 164KB (82KW) 164KB (82KW) 132KB (66KW) 164KB (82KW) 132KB (66KW)

Code security for on-chip flash, RAM,and OTP blocks Yes

Boot ROM Yes

System

Configurable Logic Block (CLB) Yes No

32-bit CPU timers 3

Watchdog timers 1

Nonmaskable Interrupt Watchdog(NMIWD) timers 1

Crystal oscillator/External clock input 1

0-pin internal oscillator 2

I/O pins(shared) GPIO 169 97 41 169 97 169 97 41 169 97 41 169 97 41 169 97 41

External interrupts 5

EMIFEMIF1 (16-bit or 32-bit) 1 – 1 1 – 1 – 1 – 1 –

EMIF2 (16-bit) 1 – – 1 – 1 – – 1 – – 1 – – 1 – –

Analog Peripherals

ADC 16-bitmode

MSPS 1.1 – 1.1 –

Conversion Time(ns)(2) 915 – 915 –

Input pins 24 20 14 – 24 20 14 24 20 14 –

Channels (differential) 12 9 7 – 12 9 7 12 9 7 –

ADC 12-bitmode

MSPS 3.5

Conversion Time(ns)(2) 290

Input pins 24 20 14 24 20 24 20 14 24 20 14 24 20 14 24 20 14

Channels(single-ended) 24 20 14 24 20 24 20 14 24 20 14 24 20 14 24 20 14

Number of 16-bit or 12-bit ADCs 4 2 – 4 2 4 2 –

Number of 12-bit only ADCs – 4 – 4 2 4 2

Temperature sensor 1

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8



TMS320F28374S

Device Comparison Copyright © 2014–2017, Texas Instruments Incorporated

Table 3-1. Device Comparison (continued)FEATURE (1) 28379S 28378S 28377S 28376S 28375S 28374S

Package Type(ZWT is an nFBGA package.PTP is an HLQFP package.PZP is an HTQFP package.)

337-BallZWT

176-PinPTP

100-PinPZP

337-BallZWT

176-PinPTP

337-BallZWT

176-PinPTP

100-PinPZP

337-BallZWT

176-PinPTP

100-PinPZP

337-BallZWT

176-PinPTP

100-PinPZP

337-BallZWT

176-PinPTP

100-PinPZP

(3) For devices that are available in more than one package, the peripheral count listed in the smaller package is reduced because thesmaller package has less device pins available. The number of peripherals internally present on the device is not reduced compared tothe largest package offered within a part number. See Section 4 to identify which peripheral instances are accessible on pins in thesmaller package.

(4) The CAN module uses the IP known as D_CAN. This document uses the names CAN and D_CAN interchangeably to reference thisperipheral.

(5) The letter Q refers to AEC Q100 qualification for automotive applications.

CMPSS (each CMPSS has twocomparators and two internal DACs) 8 4 8 8 4 8 4 8 4 8 4

Buffered DAC 3

Control Peripherals(3)

eCAP inputs – Type 0 6

Enhanced Pulse Width Modulator(ePWM) channels – Type 4 24 15 24 24 15 24 15 24 15 24 15

eQEP modules – Type 0 3 2 3 3 2 3 2 3 2 3 2

High-resolution ePWM channels –Type 4 16 9 16 16 9 16 9 16 9 16 9

SDFM channels – Type 0 8 6 8 8 6 8 6 8 6 8 6

Communication Peripherals(3)

Controller Area Network (CAN) –Type 0 (4) 2

Inter-Integrated Circuit (I2C) – Type 0 2

Multichannel Buffered Serial Port(McBSP) – Type 1 2

Serial Communications Interface(SCI) – Type 0 4 3 4 4 3 4 3 4 3 4 3

Serial Peripheral Interface (SPI) –Type 2 3

Universal Serial Bus (USB) – Type 0 1

uPP – Type 0 1

Temperature and Qualification

JunctionTemperature(TJ)

T: –40°C to 105°C Yes No Yes

S: –40°C to 125°C Yes

Q: –40°C to 150°C(5) No No Yes No No Yes No

Free-AirTemperature(TA)

Q: –40°C to 125°C(5) No No Yes No No Yes No

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9




TMS320F28374S

Device ComparisonCopyright © 2014–2017, Texas Instruments Incorporated

3.1 Related ProductsFor information about other devices in this family of products, see the following links:

TMS320F2837xD Dual-Core Delfino™ MicrocontrollersThe Delfino™ TMS320F2837xD is a powerful 32-bit floating-point microcontroller unit (MCU) designed foradvanced closed-loop control applications such as industrial drives and servo motor control; solarinverters and converters; digital power; transportation; and power line communications. Completedevelopment packages for digital power and industrial drives are available as part of the powerSUITE andDesignDRIVE initiatives. While the Delfino product line is not new to the TMS320C2000™ portfolio, theF2837xD supports a new dual-core C28x architecture that significantly boosts system performance. Theintegrated analog and control peripherals also let designers consolidate control architectures and eliminatemultiprocessor use in high-end systems.

TMS320F2807x Piccolo™ MicrocontrollersThe TMS320F2807x microcontroller platform is part of the Piccolo™ family and is suited for advancedclosed-loop control applications such as industrial drives and servo motor control; solar inverters andconverters; digital power; transportation; and power line communications. Complete developmentpackages for digital power and industrial drives are available as part of the powerSUITE andDesignDRIVE initiatives.

TMS320F2833x Digital Signal Controllers (DSCs)The TMS320F28335, TMS320F28334, and TMS320F28332 devices, members of the TMS320C28x/Delfino™ DSC/MCU generation, are highly integrated, high-performance solutions for demanding controlapplications.

TMS320F2823x Digital Signal Controllers (DSCs)The TMS320F28235, TMS320F28234, and TMS320F28232 devices, members of the TMS320C28x/Delfino™ DSC/MCU generation, are highly integrated, high-performance solutions for demanding controlapplications.

TMS320C2834x Delfino MicrocontrollersThe TMS320C2834x (C2834x) Delfino™ microcontroller unit (MCU) devices build on TI's existing F2833xhigh-performance floating-point microcontrollers. The C2834x delivers up to 300 MHz of floating-pointperformance, and has up to 516KB of on-chip RAM. Designed for real-time control applications, theC2834x is based on the C28x core, making it code-compatible with all C28x microcontrollers. The on-chipperipherals and low-latency core make the C2834x an excellent solution for performance-hungry real-timecontrol applications.

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W

V

U

T

R

P

N

M

L

K

10987654321

654321

VSS

VSSA

VSSA

VSSAVSSA

VSSA

VDDA

VDDA

VREFHIB

VREFLOBVREFHID

VREFLOD

VREFHIA

VREFHIC VREFLOA

VREFLOC

W

V

U

TGPIO129GPIO125

GPIO23GPIO24GPIO25GPIO26

GPIO27 GPIO108GPIO107GPIO106

GPIO111GPIO112GPIO110

GPIO109 GPIO114 GPIO113

GPIO122ADCIND4ADCIND2ADCIND0ADCIN14

ADCIN15

ADCINC5ADCINC3

ADCINC2

ADCINA5ADCINA3ADCINA1

ADCINA0 ADCINA2 ADCINA4

ADCINC4

ADCIND1 ADCIND3

ADCINB4ADCINB2ADCINB0

ADCINB1 ADCINB3 ADCINB5

ADCIND5 GPIO123

GPIO124

GPIO126

GPIO127

GPIO128

GPIO130

GPIO131

GPIO116

R

P

VSSVSS

VSSVSSVSS

VDD

VDDVDD

VDDIO

VDDIOVDDIOVDDIO

VDDIO

VDDIO VDD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS VSS

1098

M

L

K

N

M

L

K

10987

10



TMS320F28374S

Terminal Configuration and Functions Copyright © 2014–2017, Texas Instruments Incorporated

4 Terminal Configuration and Functions

4.1 Pin DiagramsFigure 4-1 to Figure 4-4 show the terminal assignments on the 337-ball ZWT New Fine Pitch Ball GridArray. Each figure shows a quadrant of the terminal assignments. Figure 4-5 shows the pin assignmentson the 176-pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack. Figure 4-6 shows the pinassignments on the 100-pin PZP PowerPAD Thermally Enhanced Thin Quad Flatpack.

A. Only the GPIO function is shown on GPIO terminals. See Table 4-1 for the complete, muxed signal name.

Figure 4-1. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant A]


W

V

U

T

R

P

17161514131211

17161514

VDD

VDD VSS

VSS VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

GPIO66GPIO65

GPIO61

GPIO59

GPIO56

GPIO52

GPIO48

GPIO38GPIO119GPIO35GPIO33GPIO118GPIO30

GPIO31

GPIO28

GPIO29

GPIO117

GPIO115

GPIO32 GPIO34 GPIO120

TCKTRST

TDOTDI TMSFLT1

FLT2

GPIO37

GPIO36

GPIO121

GPIO64

GPIO60

GPIO58

GPIO53

GPIO49

GPIO136

GPIO41

GPIO40

GPIO39

VDDIOVDDIO

VDDIOVDDIO

VDD3VFL VDD3VFL

1918

1918

VSS

W

V

U

T

R

P

N

M

L

KGPIO45GPIO44

GPIO142

GPIO140GPIO141

GPIO57 GPIO139

GPIO55GPIO54

GPIO50

GPIO137

GPIO135

GPIO134

GPIO132

GPIO51

GPIO138

ERRORSTS

VDDIO

VSS

1211

M

L

K

N

M

L

K

131211

11




TMS320F28374S

Terminal Configuration and FunctionsCopyright © 2014–2017, Texas Instruments Incorporated


Figure 4-2. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant B]


F

E

D

C

B

A

191817161514

191817161514131211

X1

X2VREGENZ

GPIO67GPIO69

GPIO70GPIO73GPIO77GPIO81GPIO149GPIO153GPIO84

GPIO85

GPIO86

GPIO87

GPIO154

GPIO155

GPIO156

GPIO150

GPIO151

GPIO152

GPIO82

GPIO83

GPIO148

GPIO78

GPIO79

GPIO80

GPIO72

GPIO76

GPIO75

GPIO71

GPIO74

GPIO147

GPIO145

GPIO144

GPIO68

GPIO146

GPIO143

GPIO133

GPIO62GPIO63

GPIO47

GPIO43

GPIO42

GPIO46

XRS

H

G

F

E

D

C

B

A

J

VSS

VSS

VSS

VSS

VSS VSS VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSSVDD

VDD

VDD

VDD

VDD VDD

VDDIO

VDDOSCVDDOSC

VDDIO

VDDIO

VDDIO

VDDIO

VSSOSC VSSOSCH

J

1211

131211

H

G

J

12



TMS320F28374S



Figure 4-3. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant C]


J

H

G

F

E

D

C

B

A

654321

7654321

GPIO2GPIO6GPIO90GPIO92GPIO94GPIO97

GPIO10

GPIO11

GPIO13

GPIO16

GPIO98

GPIO99

GPIO100

GPIO103

GPIO12

GPIO14

GPIO17

GPIO20

GPIO95

GPIO96

GPIO15

GPIO18

GPIO21

GPIO9GPIO8

GPIO101

GPIO104

GPIO102

GPIO105

GPIO93

GPIO167

GPIO168

GPIO19

GPIO22

GPIO91

GPIO165

GPIO166

GPIO7

GPIO88

GPIO89

GPIO3

GPIO4

GPIO5

VDDIO

VDDIO

VSS

VSS

VSS VSS

VSS

VSS

VSS

VDDIO

VDDIO

VDDIO

VDDIO

VDDIO

VDDIO

VDDIONC

VSS

VSS VSS VSS

VSS VSS

1098

J

H

J

H

G

1098

F

E

D

C

BGPIO157GPIO160

GPIO163

GPIO164

GPIO0

GPIO1

GPIO161

GPIO162

GPIO158

GPIO159

A

VDD

VDD

VSS

VSS

VSS

VDDIO

VDDIO

VDDIO

10987

13




TMS320F28374S



Figure 4-4. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant D]


88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

1 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

VDD

VDD

VDDAVREFHIB

VREFLOB

VREFLOD

VREFHID

VSSA

GPIO40

GPIO39

GPIO38

GPIO37

TCK

TMS

TDO

TDI

GPIO35

GPIO34

GPIO33

GPIO32

GPIO31

GPIO29

GPIO28

GPIO30

ADCIND4

ADCIND3

ADCIND2

ADCIND1

ADCIND0

ADCINB3

ADCINB2

ADCINB1

ADCINB0

ADCIN15

FLT1

FLT2

TRST

GPIO36

VDDIO

VDDIO

VDDIO

VDDIO

VDDIO

VDD3VFL

GP

IO67

GP

IO133

GP

IO45

GP

IO44

GP

IO66

GP

IO65

GP

IO64

GP

IO63

GP

IO62

GP

IO61

GP

IO60

GP

IO59

GP

IO58

GP

IO57

GP

IO56

GP

IO55

GP

IO54

GP

IO53

GP

IO52

GP

IO51

GP

IO50

GP

IO49

GP

IO48

GP

IO41

ER

RO

RS

TS

VR

EG

EN

Z

X1

X2

XR

S

GP

IO43

GP

IO42

GP

IO47

GP

IO46

VS

SO

SC

VD

D

VD

D

VD

DIO

VD

DO

SC

VD

DO

SC

VD

DIO

VD

DIO

VD

DIO

VD

DIO

VD

DIO

GP

IO10

GP

IO11

GP

IO12

GP

IO13

GP

IO14

GP

IO15

GP

IO16

GP

IO17

GP

IO18

GP

IO19

GP

IO20

GP

IO8

GP

IO9

GP

IO22

GP

IO23

GP

IO24

GP

IO25

GP

IO26

GP

IO27

AD

CIN

C4

AD

CIN

C3

AD

CIN

C2

AD

CIN

A5

AD

CIN

A4

AD

CIN

A3

AD

CIN

A2

AD

CIN

A1

AD

CIN

A0

AD

CIN

14

GP

IO21

VS

SA

VD

DA

VR

EF

HIC

VR

EF

LO

C

VR

EF

LO

A

VR

EF

HIA

VD

D

GP

IO99

VD

D

VD

DIO

VD

DIO

VD

DIO

VD

DIO

VD

DIO

GPIO68

GPIO69

GPIO70

GPIO71

GPIO72

GPIO73

GPIO74

GPIO75

GPIO76

GPIO77

GPIO78

GPIO79

GPIO80

GPIO81

GPIO82

GPIO83

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO88

GPIO89

GPIO90

GPIO91

GPIO92

GPIO93

GPIO94

GPIO84

GPIO85

GPIO86

GPIO87

VDD

VDD

VDD

VDDIO

VDDIO

VDDIO

VDDIO

VDDIO

VDD

14



TMS320F28374S


A. Only the GPIO function is shown on GPIO pins. See Table 4-1 for the complete, muxed signal name.

Figure 4-5. 176-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (Top View)


75

74

73

72

71

70

69

68

67

66

65

64

63

62

50

49

48

47

46

45

44

43

42

41

40

39

38

37

76

77

78

79

80

81

82

83

84

85

86

87

88

89

1 2 3 4 5 6 7 8 9 10

11

12

13

14

61

60

59

58

57

56

15

16

17

18

19

20

90

91

92

93

94

95

36

35

34

33

32

31

21

22

23

24

25

30

29

28

27

26

55

54

53

52

51

96

97

98

99

100

GPIO70

GPIO71

GPIO72

GPIO73

GPIO78

GPIO84

GPIO85

GPIO86

GPIO87

GPIO2

GPIO3

GPIO4

GPIO89

GPIO90

GPIO91

GPIO92

GPIO10

VDD

VDD

VDD

VDDIO

VDDIO

VDDIO

VDDIO

VDD

GP

IO11

AD

CIN

A3

AD

CIN

A0

AD

CIN

A1

AD

CIN

A2

AD

CIN

A4

AD

CIN

A5

GP

IO21

GP

IO20

GP

IO99

GP

IO18

GP

IO19

GP

IO17

GP

IO16

GP

IO15

GP

IO14

GP

IO13

GP

IO12

TCK

TDO

TDI

FLT1

FLT2

ADCINB5

ADCINB4

ADCINB3

ADCINB2

ADCINB1

ADCINB0

ADCIN15

ADCIN14

VDD

VDD

VSSA

VDD3VFL

VDDIO

VDDA

VREFHIB

VSSA

VREFLOB

VDDIO

TMS

TRST

GP

IO69

GP

IO41

GP

IO58

GP

IO59

GP

IO60

GP

IO61

GP

IO62

GP

IO63

GP

IO64

GP

IO65

GP

IO66

VR

EG

EN

Z

X1

X2

GP

IO43

GP

IO42

XR

S

VD

DIO

VD

DO

SC

VD

DIO

VD

DIO

VD

DO

SC

VD

D

VD

D

VS

SO

SC

VD

DIO

VD

DIO

VD

DIO

VD

D

V/V

SS

AR

EF

LO

A

VD

DA

VR

EF

HIA

15




TMS320F28374S


A. Only the GPIO function is shown on GPIO pins. See Table 4-1 for the complete, muxed signal name.

Figure 4-6. 100-Pin PZP PowerPAD HTQFP (Top View)

NOTEThe exposed lead frame die pad of the PowerPAD™ package serves two functions: toremove heat from the die and to provide ground path for the digital ground (analog ground isprovided through dedicated pins). Thus, the PowerPAD should be soldered to the ground(GND) plane of the PCB because this will provide both the digital ground path and goodthermal conduction path. To make optimum use of the thermal efficiencies designed into thePowerPAD package, the PCB must be designed with this technology in mind. A thermal landis required on the surface of the PCB directly underneath the body of the PowerPAD. Thethermal land should be soldered to the exposed lead frame die pad of the PowerPADpackage; the thermal land should be as large as needed to dissipate the required heat. Anarray of thermal vias should be used to connect the thermal pad to the internal GND plane ofthe board. See PowerPAD™ Thermally Enhanced Package for more details on using thePowerPAD package.

http://www.ti.com/product/tms320f28379s?qgpn=tms320f28379shttp://www.ti.com/product/tms320f28378s?qgpn=tms320f28378shttp://www.ti.com/product/tms320f28377s?qgpn=tms320f28377shttp://www.ti.com/product/tms320f28376s?qgpn=tms320f28376shttp://www.ti.com/product/tms320f28375s?qgpn=tms320f28375shttp://www.ti.com/product/tms320f28374s?qgpn=tms320f28374shttp://www.ti.comhttp://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SPRS881D&partnum=TMS320F28379Shttp://www.ti.com/product/tms320f28379s?qgpn=tms320f28379shttp://www.ti.com/product/tms320f28378s?qgpn=tms320f28378shttp://www.ti.com/product/tms320f28377s?qgpn=tms320f28377shttp://www.ti.com/product/tms320f28376s?qgpn=tms320f28376shttp://www.ti.com/product/tms320f28375s?qgpn=tms320f28375shttp://www.ti.com/product/tms320f28374s?qgpn=tms320f28374shttp://www.ti.com/lit/pdf/SLMA002

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TMS320F28374S


NOTEPCB footprints and schematic symbols are available for download in a vendor-neutral format,which can be exported to the leading EDA CAD/CAE design tools. See the CAD/CAESymbols section in the product folder for each device, under the Packaging section. Thesefootprints and symbols can also be searched for at http://webench.ti.com/cad/.

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TMS320F28374S


4.2 Signal DescriptionsTable 4-1 describes the signals. The GPIO function is the default at reset, unless otherwise mentioned.The peripheral signals that are listed under them are alternate functions. Some peripheral functions maynot be available in all devices. See Table 3-1 for details. All GPIO pins are I/O/Z and have an internalpullup, which can be selectively enabled or disabled on a per-pin basis. This feature only applies to theGPIO pins. The pullups are not enabled at reset.

Table 4-1. Signal DescriptionsTERMINAL

I/O/Z(1) DESCRIPTIONNAME MUXPOSITION

ZWTBALLNO.

PTPPINNO.

PZPPINNO.

ADC, DAC, AND COMPARATOR SIGNALS

VREFHIA V1 37 19 I

ADC-A high reference. This voltage must be driven intothe pin from external circuitry. Place at least a 1-µFcapacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor shouldbe placed as close to the device as possible betweenthe VREFHIA and VREFLOA pins.NOTE: Do not load this pin externally.

VREFHIB W5 53 37 I

ADC-B high reference. This voltage must be driven intothe pin from external circuitry. Place at least a 1-µFcapacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor shouldbe placed as close to the device as possible betweenthe VREFHIB and VREFLOB pins.NOTE: Do not load this pin externally.

VREFHIC R1 35 – I

ADC-C high reference. This voltage must be driven intothe pin from external circuitry. Place at least a 1-µFcapacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor shouldbe placed as close to the device as possible betweenthe VREFHIC and VREFLOC pins.NOTE: Do not load this pin externally.

VREFHID V5 55 – I

ADC-D high reference. This voltage must be driven intothe pin from external circuitry. Place at least a 1-µFcapacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor shouldbe placed as close to the device as possible betweenthe VREFHID and VREFLOD pins.NOTE: Do not load this pin externally.

VREFLOA R2 33 17 I

ADC-A low reference.On the PZP package, pin 17 is double-bonded to VSSAand VREFLOA. On the PZP package, pin 17 must beconnected to VSSA on the system board.

VREFLOB V6 50 34 I ADC-B low referenceVREFLOC P2 32 – I ADC-C low referenceVREFLOD W6 51 – I ADC-D low referenceADCIN14

T4 44 26

I Input 14 to all ADCs. This pin can be used as a general-purpose ADCIN pin or it can be used to calibrate allADCs together (either single-ended or differential) froman external reference.

CMPIN4P I Comparator 4 positive inputADCIN15

U4 45 27

I Input 15 to all ADCs. This pin can be used as a general-purpose ADCIN pin or it can be used to calibrate allADCs together (either single-ended or differential) froman external reference.

CMPIN4N I Comparator 4 negative input


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TMS320F28374S


Table 4-1. Signal Descriptions (continued)TERMINAL


ZWTBALLNO.

PTPPINNO.

PZPPINNO.

ADCINA0

U1 43 25

I ADC-A input 0. There is a 50-kΩ internal pulldown onthis pin in both an ADC input or DAC output mode whichcannot be disabled.

DACOUTA O DAC-A outputADCINA1

T1 42 24

I ADC-A input 1. There is a 50-kΩ internal pulldown onthis pin in both an ADC input or DAC output mode whichcannot be disabled.

DACOUTB O DAC-B outputADCINA2

U2 41 23I ADC-A input 2

CMPIN1P I Comparator 1 positive inputADCINA3

T2 40 22I ADC-A input 3

CMPIN1N I Comparator 1 negative inputADCINA4

U3 39 21I ADC-A input 4

CMPIN2P I Comparator 2 positive inputADCINA5

T3 38 20I ADC-A input 5

CMPIN2N I Comparator 2 negative inputADCINB0

V2 46 28

I ADC-B input 0. There is a 100-pF capacitor to VSSA onthis pin in both ADC input or DAC reference mode whichcannot be disabled. If this pin is being used as areference for the on-chip DACs, place at least a 1-µFcapacitor on this pin.

VDAC I Optional external reference voltage for on-chip DACs.There is a 100-pF capacitor to VSSA on this pin in bothADC input or DAC reference mode which cannot bedisabled. If this pin is being used as a reference for theon-chip DACs, place at least a 1-µF capacitor on thispin.

ADCINB1

W2 47 29

I ADC-B input 1. There is a 50-kΩ internal pulldown onthis pin in both an ADC input or DAC output mode whichcannot be disabled.

DACOUTC O DAC-C outputADCINB2

V3 48 30I ADC-B input 2

CMPIN3P I Comparator 3 positive inputADCINB3

W3 49 31I ADC-B input 3

CMPIN3N I Comparator 3 negative inputADCINB4 V4 – 32 I ADC-B input 4ADCINB5 W4 – 33 I ADC-B input 5ADCINC2

R3 31 –I ADC-C input 2

CMPIN6P I Comparator 6 positive inputADCINC3

P3 30 –I ADC-C input 3

CMPIN6N I Comparator 6 negative inputADCINC4

R4 29 –I ADC-C input 4

CMPIN5P I Comparator 5 positive inputADCINC5

P4 – –I ADC-C input 5

CMPIN5N I Comparator 5 negative inputADCIND0

T5 56 –I ADC-D input 0

CMPIN7P I Comparator 7 positive inputADCIND1

U5 57 –I ADC-D input 1

CMPIN7N I Comparator 7 negative input


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TMS320F28374S




ZWTBALLNO.

PTPPINNO.

PZPPINNO.

ADCIND2T6 58 –

I ADC-D input 2CMPIN8P I Comparator 8 positive inputADCIND3

U6 59 –I ADC-D input 3

CMPIN8N I Comparator 8 negative inputADCIND4 T7 60 – I ADC-D input 4ADCIND5 U7 – – I ADC-D input 5

GPIO AND PERIPHERAL SIGNALSGPIO0 0, 4, 8, 12

C8 160 –I/O General-purpose input/output 0

EPWM1A 1 O Enhanced PWM1 output A (HRPWM-capable)SDAA 6 I/OD I2C-A data open-drain bidirectional portGPIO1 0, 4, 8, 12

D8 161 –

I/O General-purpose input/output 1EPWM1B 1 O Enhanced PWM1 output B (HRPWM-capable)MFSRB 3 I/O McBSP-B receive frame synchSCLA 6 I/OD I2C-A clock open-drain bidirectional portGPIO2 0, 4, 8, 12

A7 162 91

I/O General-purpose input/output 2EPWM2A 1 O Enhanced PWM2 output A (HRPWM-capable)OUTPUTXBAR1 5 O Output 1 of the output XBARSDAB 6 I/OD I2C-B data open-drain bidirectional portGPIO3 0, 4, 8, 12

B7 163 92

I/O General-purpose input/output 3EPWM2B 1 O Enhanced PWM2 output B (HRPWM-capable)OUTPUTXBAR2 2 O Output 2 of the output XBARMCLKRB 3 I/O McBSP-B receive clockOUTPUTXBAR2 5 O Output 2 of the output XBARSCLB 6 I/OD I2C-B clock open-drain bidirectional portGPIO4 0, 4, 8, 12

C7 164 93

I/O General-purpose input/output 4EPWM3A 1 O Enhanced PWM3 output A (HRPWM-capable)OUTPUTXBAR3 5 O Output 3 of the output XBARCANTXA 6 O CAN-A transmitGPIO5 0, 4, 8, 12

D7 165 –

I/O General-purpose input/output 5EPWM3B 1 O Enhanced PWM3 output B (HRPWM-capable)MFSRA 2 I/O McBSP-A receive frame synchOUTPUTXBAR3 3 O Output 3 of the output XBARCANRXA 6 I CAN-A receiveGPIO6 0, 4, 8, 12

A6 166 –

I/O General-purpose input/output 6EPWM4A 1 O Enhanced PWM4 output A (HRPWM-capable)OUTPUTXBAR4 2 O Output 4 of the output XBAREXTSYNCOUT 3 O External ePWM synch pulse outputEQEP3A 5 I Enhanced QEP3 input ACANTXB 6 O CAN-B transmitGPIO7 0, 4, 8, 12

B6 167 –

I/O General-purpose input/output 7EPWM4B 1 O Enhanced PWM4 output B (HRPWM-capable)MCLKRA 2 I/O McBSP-A receive clockOUTPUTXBAR5 3 O Output 5 of the output XBAREQEP3B 5 I Enhanced QEP3 input BCANRXB 6 I CAN-B receive


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TMS320F28374S




ZWTBALLNO.

PTPPINNO.

PZPPINNO.

GPIO8 0, 4, 8, 12

G2 18 –

I/O General-purpose input/output 8EPWM5A 1 O Enhanced PWM5 output A (HRPWM-capable)CANTXB 2 O CAN-B transmitADCSOCAO 3 O ADC start-of-conversion A output for external ADCEQEP3S 5 I/O Enhanced QEP3 strobeSCITXDA 6 O SCI-A transmit dataGPIO9 0, 4, 8, 12

G3 19 –

I/O General-purpose input/output 9EPWM5B 1 O Enhanced PWM5 output B (HRPWM-capable)SCITXDB 2 O SCI-B transmit dataOUTPUTXBAR6 3 O Output 6 of the output XBAREQEP3I 5 I/O Enhanced QEP3 indexSCIRXDA 6 I SCI-A receive dataGPIO10 0, 4, 8, 12

B2 1 100

I/O General-purpose input/output 10EPWM6A 1 O Enhanced PWM6 output A (HRPWM-capable)CANRXB 2 I CAN-B receiveADCSOCBO 3 O ADC start-of-conversion B output for external ADCEQEP1A 5 I Enhanced QEP1 input ASCITXDB 6 O SCI-B transmit dataUPP-WAIT 15 I/O Universal parallel port wait. Receiver asserts to request

a pause in transfer.GPIO11 0, 4, 8, 12

C1 2 1

I/O General-purpose input/output 11EPWM6B 1 O Enhanced PWM6 output B (HRPWM-capable)SCIRXDB 2, 6 I SCI-B receive dataOUTPUTXBAR7 3 O Output 7 of the output XBAREQEP1B 5 I Enhanced QEP1 input BUPP-START 15 I/O Universal parallel port start. Transmitter asserts at start

of DMA line.GPIO12 0, 4, 8, 12

C2 4 3

I/O General-purpose input/output 12EPWM7A 1 O Enhanced PWM7 output A (HRPWM-capable)CANTXB 2 O CAN-B transmitMDXB 3 O McBSP-B transmit serial dataEQEP1S 5 I/O Enhanced QEP1 strobeSCITXDC 6 O SCI-C transmit dataUPP-ENA 15 I/O Universal parallel port enable. Transmitter asserts while

data bus is active.GPIO13 0, 4, 8, 12

D1 5 4

I/O General-purpose input/output 13EPWM7B 1 O Enhanced PWM7 output B (HRPWM-capable)CANRXB 2 I CAN-B receiveMDRB 3 I McBSP-B receive serial dataEQEP1I 5 I/O Enhanced QEP1 indexSCIRXDC 6 I SCI-C receive dataUPP-D7 15 I/O Universal parallel port data line 7


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TMS320F28374S




ZWTBALLNO.

PTPPINNO.

PZPPINNO.

GPIO14 0, 4, 8, 12

D2 6 5

I/O General-purpose input/output 14EPWM8A 1 O Enhanced PWM8 output A (HRPWM-capable)SCITXDB 2 O SCI-B transmit dataMCLKXB 3 I/O McBSP-B transmit clockOUTPUTXBAR3 6 O Output 3 of the output XBARUPP-D6 15 I/O Universal parallel port data line 6GPIO15 0, 4, 8, 12

D3 7 6

I/O General-purpose input/output 15EPWM8B 1 O Enhanced PWM8 output B (HRPWM-capable)SCIRXDB 2 I SCI-B receive dataMFSXB 3 I/O McBSP-B transmit frame synchOUTPUTXBAR4 6 O Output 4 of the output XBARUPP-D5 15 I/O Universal parallel port data line 5GPIO16 0, 4, 8, 12

E1 8 7

I/O General-purpose input/output 16SPISIMOA 1 I/O SPI-A slave in, master outCANTXB 2 O CAN-B transmitOUTPUTXBAR7 3 O Output 7 of the output XBAREPWM9A 5 O Enhanced PWM9 output ASD1_D1 7 I Sigma-Delta 1 channel 1 data inputUPP-D4 15 I/O Universal parallel port data line 4GPIO17 0, 4, 8, 12

E2 9 8

I/O General-purpose input/output 17SPISOMIA 1 I/O SPI-A slave out, master inCANRXB 2 I CAN-B receiveOUTPUTXBAR8 3 O Output 8 of the output XBAREPWM9B 5 O Enhanced PWM9 output BSD1_C1 7 I Sigma-Delta 1 channel 1 clock inputUPP-D3 15 I/O Universal parallel port data line 3GPIO18 0, 4, 8, 12

E3 10 9

I/O General-purpose input/output 18SPICLKA 1 I/O SPI-A clockSCITXDB 2 O SCI-B transmit dataCANRXA 3 I CAN-A receiveEPWM10A 5 O Enhanced PWM10 output ASD1_D2 7 I Sigma-Delta 1 channel 2 data inputUPP-D2 15 I/O Universal parallel port data line 2GPIO19 0, 4, 8, 12

E4 12 11

I/O General-purpose input/output 19SPISTEA 1 I/O SPI-A slave transmit enableSCIRXDB 2 I SCI-B receive dataCANTXA 3 O CAN-A transmitEPWM10B 5 O Enhanced PWM10 output BSD1_C2 7 I Sigma-Delta 1 channel 2 clock inputUPP-D1 15 I/O Universal parallel port data line 1


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TMS320F28374S




ZWTBALLNO.

PTPPINNO.

PZPPINNO.

GPIO20 0, 4, 8, 12

F2 13 12

I/O General-purpose input/output 20EQEP1A 1 I Enhanced QEP1 input AMDXA 2 O McBSP-A transmit serial dataCANTXB 3 O CAN-B transmitEPWM11A 5 O Enhanced PWM11 output ASD1_D3 7 I Sigma-Delta 1 channel 3 data inputUPP-D0 15 I/O Universal parallel port data line 0GPIO21 0, 4, 8, 12

F3 14 13

I/O General-purpose input/output 21EQEP1B 1 I Enhanced QEP1 input BMDRA 2 I McBSP-A receive serial dataCANRXB 3 I CAN-B receiveEPWM11B 5 O Enhanced PWM11 output BSD1_C3 7 I Sigma-Delta 1 channel 3 clock inputUPP-CLK 15 I/O Universal parallel port transmit clockGPIO22 0, 4, 8, 12

J4 22 –

I/O General-purpose input/output 22EQEP1S 1 I/O Enhanced QEP1 strobeMCLKXA 2 I/O McBSP-A transmit clockSCITXDB 3 O SCI-B transmit dataEPWM12A 5 O Enhanced PWM12 output ASPICLKB 6 I/O SPI-B clockSD1_D4 7 I Sigma-Delta 1 channel 4 data inputGPIO23 0, 4, 8, 12

K4 23 –

I/O General-purpose input/output 23EQEP1I 1 I/O Enhanced QEP1 indexMFSXA 2 I/O McBSP-A transmit frame synchSCIRXDB 3 I SCI-B receive dataEPWM12B 5 O Enhanced PWM12 output BSPISTEB 6 I/O SPI-B slave transmit enableSD1_C4 7 I Sigma-Delta 1 channel 4 clock inputGPIO24 0, 4, 8, 12

K3 24 –

I/O General-purpose input/output 24OUTPUTXBAR1 1 O Output 1 of the output XBAREQEP2A 2 I Enhanced QEP2 input AMDXB 3 O McBSP-B transmit serial dataSPISIMOB 6 I/O SPI-B slave in, master outSD2_D1 7 I Sigma-Delta 2 channel 1 data inputGPIO25 0, 4, 8, 12

K2 25 –

I/O General-purpose input/output 25OUTPUTXBAR2 1 O Output 2 of the output XBAREQEP2B 2 I Enhanced QEP2 input BMDRB 3 I McBSP-B receive serial dataSPISOMIB 6 I/O SPI-B slave out, master inSD2_C1 7 I Sigma-Delta 2 channel 1 clock input


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TMS320F28374S




ZWTBALLNO.

PTPPINNO.

PZPPINNO.

GPIO26 0, 4, 8, 12

K1 27 –

I/O General-purpose input/output 26OUTPUTXBAR3 1 O Output 3 of the output XBAREQEP2I 2 I/O Enhanced QEP2 indexMCLKXB 3 I/O McBSP-B transmit clockOUTPUTXBAR3 5 O Output 3 of the output XBARSPICLKB 6 I/O SPI-B clockSD2_D2 7 I Sigma-Delta 2 channel 2 data inputGPIO27 0, 4, 8, 12

L1 28 –

I/O General-purpose input/output 27OUTPUTXBAR4 1 O Output 4 of the output XBAREQEP2S 2 I/O Enhanced QEP2 strobeMFSXB 3 I/O McBSP-B transmit frame synchOUTPUTXBAR4 5 O Output 4 of the output XBARSPISTEB 6 I/O SPI-B slave transmit enableSD2_C2 7 I Sigma-Delta 2 channel 2 clock inputGPIO28 0, 4, 8, 12

V11 64 –

I/O General-purpose input/output 28SCIRXDA 1 I SCI-A receive dataEM1CS4 2 O External memory interface 1 chip select 4OUTPUTXBAR5 5 O Output 5 of the output XBAREQEP3A 6 I Enhanced QEP3 input ASD2_D3 7 I Sigma-Delta 2 channel 3 data inputGPIO29 0, 4, 8, 12

W11 65 –

I/O General-purpose input/output 29SCITXDA 1 O SCI-A transmit dataEM1SDCKE 2 O External memory interface 1 SDRAM clock enableOUTPUTXBAR6 5 O Output 6 of the output XBAREQEP3B 6 I Enhanced QEP3 input BSD2_C3 7 I Sigma-Delta 2 channel 3 clock inputGPIO30 0, 4, 8, 12

T11 63 –

I/O General-purpose input/output 30CANRXA 1 I CAN-A receiveEM1CLK 2 O External memory interface 1 clockOUTPUTXBAR7 5 O Output 7 of the output XBAREQEP3S 6 I/O Enhanced QEP3 strobeSD2_D4 7 I Sigma-Delta 2 channel 4 data inputGPIO31 0, 4, 8, 12

U11 66 –

I/O General-purpose input/output 31CANTXA 1 O CAN-A transmitEM1WE 2 O External memory interface 1 write enableOUTPUTXBAR8 5 O Output 8 of the output XBAREQEP3I 6 I/O Enhanced QEP3 indexSD2_C4 7 I Sigma-Delta 2 channel 4 clock inputGPIO32 0, 4, 8, 12

U13 67 –I/O General-purpose input/output 32

SDAA 1 I/OD I2C-A data open-drain bidirectional portEM1CS0 2 O External memory interface 1 chip select 0GPIO33 0, 4, 8, 12

T13 69 –I/O General-purpose input/output 33

SCLA 1 I/OD I2C-A clock open-drain bidirectional portEM1RNW 2 O External memory interface 1 read not write


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ZWTBALLNO.

PTPPINNO.

PZPPINNO.

GPIO34 0, 4, 8, 12

U14 70 –

I/O General-purpose input/output 34OUTPUTXBAR1 1 O Output 1 of the output XBAREM1CS2 2 O External memory interface 1 chip select 2SDAB 6 I/OD I2C-B data open-drain bidirectional portGPIO35 0, 4, 8, 12

T14 71 –

I/O General-purpose input/output 35SCIRXDA 1 I SCI-A receive dataEM1CS3 2 O External memory interface 1 chip select 3SCLB 6 I/OD I2C-B clock open-drain bidirectional portGPIO36 0, 4, 8, 12

V16 83 –

I/O General-purpose input/output 36SCITXDA 1 O SCI-A transmit dataEM1WAIT 2

TMS320F2837xS Delfino™ Microcontrollers...TMS320F2837xS Delfino Microcontrollers 1 Device Overview...

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