TLV320AIC29EVM and TLV320AIC29EVM-PDK User's Guide · 2019. 11. 15. · Connect 2 ~ 3: from...

User's GuideSLAU179–April 2006

TLV320AIC29EVM and TLV320AIC29EVM-PDK

This user's guide describes the characteristics, operation, and use of theTLV320AIC29EVM, both by itself and as part of the TLV320AIC29EVM-PDK. Thisevaluation module (EVM) is a complete stereo audio codec evaluation module, withseveral audio inputs and outputs, side tone, key click, and effects capabilities. Acomplete circuit description, schematic diagram and bill of materials are also included.

The following related documents are available through the Texas Instruments web siteat www.ti.com.

EVM-COMPATIBLE DEVICE DATA SHEETS

DEVICE LITERATURE NUMBER

TLV320AIC29 SLAS494

TAS1020B SLES025

REG1117-5 SBVS001

TPS767D301/318 SLVS209

SN74LVC125A SCAS290

SN74LVC1G125 SCES223

SN74LVC1G07 SCES296

Contents1 EVM Overview ............................................................................................................... 22 Getting Started ............................................................................................................... 23 Program Description......................................................................................................... 74 Other board Level Connections .......................................................................................... 195 Physical Description ....................................................................................................... 23

List of Figures

1 Mount TLV320AIC29EVM Board on Top of USBMODEVM Board ................................................... 52 TLV320AIC29 EVM-PDK Software – Data Acquisition Tab............................................................ 63 Data Acquisition Screen, Reading Content Box ......................................................................... 84 Configuration Screen ........................................................................................................ 95 Configuration Screen With External Reference Selection ............................................................ 106 Audio 1 Screen at Default................................................................................................. 127 Audio 2 Screen at Default................................................................................................. 138 Bass Boost Filter Screen at Default ..................................................................................... 149 Audio Effect Screen With Bad Data ..................................................................................... 1810 Component Layout ......................................................................................................... 2511 Top PCB Layer ............................................................................................................. 2612 Power/Ground Plane 1 .................................................................................................... 2713 Power/Ground Plane 2 .................................................................................................... 2814 Bottom PCB Layer ......................................................................................................... 2915 Bottom Silkscreen and Solder Mask..................................................................................... 3016 TSC2111EVM/TLV320AIC29EVM Schematic, ............................................................... 3117 TSC2111EVM/TLV320AIC29EVM Schematic, Page 2 ............................................................... 3218 USB Board Schematic, Page 1........................................................................................... 33

SLAU179–April 2006 TLV320AIC29EVM and TLV320AIC29EVM-PDK 1Submit Documentation Feedback

http://www-s.ti.com/sc/techlit/SLAS494

http://www-s.ti.com/sc/techlit/SLVS209

http://www-s.ti.com/sc/techlit/SCAS290

http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLAU179

www.ti.com

1 EVM Overview

1.1 Features

1.2 Introduction

2 Getting Started

2.1 Unpacking the EVM or EVM-PDK

EVM Overview

19 USB Board Schematic, ........................................................................................... 34

List of Tables

1 TLV320AIC29EVM Board Default Configuration Settings.............................................................. 32 USBMODEVM Board Default Configuration Settings................................................................... 43 Analog Interface Pinout.................................................................................................... 194 Analog Connectors......................................................................................................... 205 Digital Interface Pinout..................................................................................................... 206 Power Supply Pin Out ..................................................................................................... 217 TLV320AIC29EVM Bill of Materials ..................................................................................... 23

• Full-featured evaluation board to evaluate/test the TLV320AIC29 functions and features• Modular design for use with a variety of DSP and microcontroller interface boards

The TLV320AIC29EVM-PDK is a complete evaluation kit, which includes a TLV320AIC29EVM board, auniversal serial bus (USB)-based motherboard, and the evaluation software for use with a personalcomputer running Microsoft Windows™ operating systems (Win2000 or XP).

The TLV320AIC29 is an advanced analog interface circuit. It communicates with a host processor througha standard SPI serial interface. A mono-input/stereo-output audio codec is included in the TLV320AIC29,and audio data is communicated to the device over an I2S bus. The TLV320AIC29 also offers two auxiliaryanalog inputs and one battery voltage measurements. The battery measurement is capable of readingbattery voltages up to 6 V while operating with only a 2.7-V supply. It also has an on-chip temperaturesensor capable of 1°C resolution. For more detail about the device, refer to the TLV320AIC29 data sheet.

The TLV320AIC29EVM is in Texas Instruments' modular EVM form factor, which allows direct evaluationof the TLV320AIC29 performance and operating characteristics, and eases software development andsystem prototyping. This EVM is compatible with the Texas Instruments 5-6K DSP Interface Board(SLAU104) from Texas Instruments and additional third party boards such as the HPA449 demonstrationboard from SoftBaugh, Inc. and the Speedy33™ from Hyperception, Inc.

The TLV320AIC29EVM-PDK is a complete evaluation/demonstration kit, which includes the TLV320AIC29EVM and a USB-based motherboard called the USB-MODEVM Interface Board. Also included withTLV320AIC29EVM-PDK is the evaluation software for use with a personal computer running MicrosoftWindows operating systems.

This chapter guides you through unpacking and configuring your EVM.

The EVM kit includes the following:

• TLV320AIC29EVM board, PWB 6451250• USBMODEVM board, PWM 6463995 (for TLV320AIC29EVM-PDK only)• CD–ROM, 645125

If any of these components is missing, contact Texas Instruments for a replacement.

TLV320AIC29EVM and TLV320AIC29EVM-PDK2 SLAU179–April 2006Submit Documentation Feedback

http://www-s.ti.com/sc/techlit/SLAU104


www.ti.com

2.2 Default ConfigurationGetting Started

The default settings of the TLV320AIC29EVM board are shown in Table 1, and the default settings of theUSBMODEVM board are shown in Table 2. When you unpack your TLV320AIC29EVM-PDK, ensure thatboth boards are configured as listed in the two tables.

Table 1. TLV320AIC29EVM Board Default Configuration Settings

Board Description Default SettingsIdentifier

SW1 Headset (SPK1/SPK2) Output Mode Selection Capless mode

JMP1 AGND and DGND connection Installed: Connect AGND to DGND Installed

Removed: Disconnect AGND to DGND

JMP2 FW Boot source selection Installed: boot from daughtercard EEPROM Installed

Removed: boot from motherboard EEPROM

JMP3 AUX2 resistance measurement (1) Removed

JMP4 AUX1 resistance measurement (1) Removed

JMP5 +1.8VD to TLV320AIC29 DVDD pin connection (2) Installed

JMP6 +3.9VA to TLV320AIC29 BVDD pin connection (2) Installed

JMP7 +3.3VA to TLV320AIC29 DRVDD pin connection (2) Installed

JMP8 +3.3VA to TLV320AIC29 AVDD1 pin connection (2) Installed

JMP9 +3.3VA to TLV320AIC29 AVDD2 pin connection (2) Installed

JMP10 IOVDD power selection Connect 1 ~ 2: IOVDD = +5VD Connect 3 ~ 4

Connect 3 ~ 4: IOVDD = +3.3VD


JMP11 Reset connection Installed: RESET from J4-GPIO2 and GPIO4 Removed

Removed: RESET from J4-GPIO2

JMP12 IOVDD to TLV320AIC29 IOVDD pin connection (2) Installed

JMP13 MIC BIAS source selection Connect 1 ~ 2: from +3.3 VA Connect 2 ~ 3

Connect 2 ~ 3: from TLV320AIC29 MICBIAS_HND pin

JMP14 VGND mode Selection Connect 1 ~ 2: TLV320AIC29 VGND pin as VGND Connect 1 ~ 2

Connect 2 ~ 3: TLV320AIC29 VGND pin as CP_OUT–

JMP15 Differential MICIN selection Removed: Single-ended MINCIN only Removed

Connect 1 ~ 3: MICIN_HND and AUX2 diff

Connect 3 ~ 5: MICIN_HND and AUX1 diff

Connect 2 ~ 4: MICIN_HED and AUX2 diff

Connect 4 ~ 6: MICIN_HED and AUX1 diff

(1) Refer to the note on the TLV320AIC29 EVM schematic for the details of these jumpers.(2) JMP5, JMP6, JMP7, JMP8, JMP9 and JMP12 are installed by default. These jumpers can be replaced by current meters for

evaluating or testing the corresponding power consumption.



www.ti.com

Getting Started

Table 2. USBMODEVM Board Default Configuration Settings

Board Description Default SettingsIdentifier

SW1 Onboard power supply enable SW1-1: +1.8VD Enable On: Enabled

SW1-2: +3.3VD Enable

SW2 On/Off board control selection SW2-1: Onboard EEPROM address bit A0 On: A0=0

SW2-2: Onboard EEPROM address bit A1 Off: A1=1

SW2-3: Onboard EEPROM address bit A2 On: A2=0 On: A2=0

SW2-4: Onboard I2S On: Onboard

SW2-5: Onboard MCLK On: Onboard

SW2-6: Onboard SPI On: Onboard

SW2-7: Onboard RESET On: Onboard

SW2-8: External MCLK from J10 (EXT MCK) Off: Not EXT Off: Not EXT

JMP1 +5VA and +5VD connection Installed: Connect +5VA to +5VD Installed

Removed: Disconnect +5VA to +5VD

JMP2 AGND and DGND connection Installed: Connect AGND to DGND Removed

Removed: Disconnect AGND to DGND

JMP3 Connect I2C SDA pull-up to IOVDD Removed

JMP4 Connect I2C SCL pull-up to IOVDD Removed

JMP5 SPI /SS select Connect 1 ~ 2: /SS from CNTL Connect 2 ~ 3 (FSX)

Connect 2 ~ 3: /SS from FSX

JMP6 Board power selection Connect 1 ~ 2: +5VD from USB Connect 1 ~ 2 (USB)

Connect 2 ~ 3: +5VD from U2

JMP7 IOVDD power selection Connect 1 ~ 2: IOVDD = +5VD Connect 3 ~ 4(+3.3VD)Connect 3 ~ 4: IOVDD = +3.3VD


JMP8 TAS1020B P1.3 GPIO connection Removed









www.ti.com

2.3 Connection

Getting Started

The TLV320AIC29 EVM-PDK allows direct evaluation of the TLV320AIC29 device with a personalcomputer. The TLV320AIC29EVM board, as the daughtercard, is installed on the top of the USBMODEVMmotherboard, as shown in Figure 1.

Use a USB cable to connect the PC to the EVM system through the J7 USB connector on theUSBMODEVM card.

Figure 1. Mount TLV320AIC29EVM Board on Top of USBMODEVM Board



www.ti.com

2.4 Quick Start

Getting Started

Once the TLV320AIC29EVM-PDK has been unpacked, and you have verified that both the daughterboard (TLV320AIC29EVM) and the motherboard (USBMODEVM) had been configured as shown inTable 1 and Table 2, and connected as shown in Figure 1, install the TLV320AIC29EVM software from theincluded CD-ROM, following the instructions provided by the installer.

When the installation is complete, connect a USB cable from the PC to the J7 on the motherboard. Whenthe TLV320AIC29EVM-PDK is connected to the PC the first time, the user may see a message that aHuman Interface/Audio Device has been connected. When this connection has been made, launch theTLV320AIC29EVM software on the PC. The software should automatically find the TLV320AIC29EVM. Ifthe board is found, the screen shown in Figure 2 appears.

Figure 2. TLV320AIC29 EVM-PDK Software – Data Acquisition Tab

With the firmware/software default configuration, the TLV320AIC29 audio output OUT8 is powered up, andthe side tone and the key click functions enabled. To verify proper function of the EVM system, a speaker(8-Ω or above) can be connected to J13 (the loudspeaker connection terminal or OUT8) on theTLV320AIC29EVM daughter-card. A 'ding' sound is heard when the USB cable from the PC is pluggedinto the motherboard (J7). Additional dings are heard when launching the software. Tapping or talkingthrough the onboard microphone (MK1) on the daughter board is audible through the speaker.



www.ti.com

3 Program Description

3.1 Data Acquisition Screen

Program Description

After installing the software for the TLV320AIC29EVM, the user can begin to evaluate the functions of theTLV320AIC29 device using the evaluation-software graphic user interface (GUI).

The user interface is a simple, five-tab interface. Clicking on a tab takes you to the functions associatedwith that tab. The program begins on the Data Acquisition (the default) as shown in Figure 2.

The status bar at the bottom of the screen is divided into four sections showing the communication statusbetween the PC and the EVM-PDK. Starting from the left, the first section shows the connection status. Ifan error in communication occurs, an error message appears here; otherwise, it displays Connected, asshown in Figure 2. The final section, on the right side of the status bar, shows the number of readings persecond being taken.

3.1.1 Data Acquisition

At this screen and with the buffer mode NOT enabled, the TLV320AIC29 automatically performs thebattery and auxiliary input voltage readings, and then TEMP1 and TEMP2 measurements. Thesemeasurements are all repeated twice per second, and the results are displayed on the three boxes at theleft side of this screen.



www.ti.com

Program Description

3.1.2 Buffer Function

In the middle of the screen, the buffer mode settings can be accessed. By default, the buffer function isdisabled, and the BAT, AUX1, AUX2, TEMP1 and TEMP2 data are converted and stored to thecorresponding registers. When the buffer function is enabled by checking the Enable option, the data isconverted and saved to the buffer registers in page 3 of the TLV320AIC29 memory space. Refer to thedata sheet for the details of the buffer function.

When the buffer function is enabled by clicking on the Read Buffered Data button, the TLV320AIC29 is putinto host-controlled mode. The TLV320AIC29 then enters auto-scan mode to poll AUX1, AUX2, andTEMP1. The raw data displays in the Reading Content on the right side of the Data Acquisition tab, asshown in Figure 3. The data in Figure 3 is listed in this order: AUX1, AUX2, TEMP1, AUX1, AUX2,TEMP1, AUX1, etc.

Figure 3. Data Acquisition Screen, Reading Content Box

With this EVM version, the buffer trigger level can be set to either 8 or 16, selected by the Buffer TriggerLevel selection slide. Even though the TLV320AIC29 can be set to a higher trigger level up to 64, thisEVM allows only 8 or 16. The buffer function can be set to Continuous or Single Shot mode using themode-control option box. Refer to the data sheet for more on TLV320AIC29 buffer function. The data inthe list is cleared by clicking on the Clear List button on this screen.

3.1.3 Register Content Display

Four additional buttons display the corresponding register contents in the list. This is helpful for testing anddebugging.



www.ti.com

3.2 Configuration Screen

Program Description

This screen accesses the configurable settings for the TLV320AIC29 analog-to-digital converter (ADC)and reference as shown in Figure 4.

Figure 4. Configuration Screen

3.2.1 ADC Control Section

The sliders in this section control all of the parameters of the A/D converter for BAT, AUX1, AUX2,TEMP1, and TEMP2 data. Each slider controls one parameter, whose value is shown next to the slider.

• Resolution — Selects between 8–, 10–, and 12–bit resolution.• Conversion Clock — The internal clock that runs the ADC can run at 8, 4, 2, or 1 MHz. When running

at 8 MHz, only 8-bit resolution is possible; when running at 4 MHz, only 8- or 10-bit resolution ispossible. Only 1- or 2-MHz clock rates allow 12-bit resolution to be chosen.

• Average/Median — There are two ways to reduce noise effect to the ADC result. One is averaging,where 4, 8, or 16 readings are averaged; another option is to find the median value among 5, 9, or 15readings. The default is the average mode, as shown in Figure 4. Median mode can be selected withthe corresponding button.

Note that these settings apply to all operations of the A/D converter and, thus, resolution and averagingcan be changed to increase accuracy in the data acquisition functions.



www.ti.com

Program Description

3.2.2 Reference Section

A reference voltage is needed for ADC measurements.

The internal reference voltage can be set to either 1.25 V or 2.5 V. The internal reference powers downbetween conversions to save power. The Powered at all times checkbox overrides this feature, and thereference does not power down. If the reference is allowed to power down, the TLV320AIC29 must allowa delay time for the reference to power up when a conversion is to take place. This delay time can be setusing the slider in this section.

If an external reference is to be used, it can be selected as shown in Figure 5. The value of the externalreference is entered in the text box shown.

Figure 5. Configuration Screen With External Reference Selection

3.2.3 Measurement Section

The TLV320AIC29 supports programmable, automatic temperature and auxiliary-input measurements. Inthe auto measurement mode, the TLV320AIC29 can auto start the TEMP1, TEMP2, AUX1, and/or AUX2measurement after a programmable interval. The checkboxes and sliders in the Measurement sectionprovide choices.

Additionally, the AUX1 and AUX2 can be configured to measure voltage or resistance. Under theresistance measurement, the bias can be configured as external or internal by checking or unchecking theEnable External Bias Resistance box.



www.ti.com

Program Description

3.2.4 Threshold Section

The TLV320AIC29 monitor the temperature and the auxiliary inputs and set corresponding flags if an inputexceeds the bounds set in the threshold registers.

In this section, if the threshold function has not been enabled (Enable checkbox has not been checked),the corresponding MAX/MIN slider does not move. Also note that the MAX value must be greater than orequal to the MIN value.

3.2.5 Continuous Conversion Delay Section

In the auto measurement mode, the delays between the conversions are programmable. This section canbe used to program to delays between the continuous conversions.

By clicking on the Enable checkbox, the auto measurement delay is enabled. The delay-time option allowsselection of delay clock source and divider.

The clock used can be the internal oscillator or the external MCLK. The clock divider (CLKDIV) is used toderive the 1-MHz clock for the programmable delay. This sets the CLKDIV so that MCLK/CLKDIV = 1MHz.

3.2.6 Reinitialization and Reset

Two buttons on this screen allow the user to reset and reinitialize the TLV320AIC29. By clicking the SWReset button, a software device reset is issued to the TLV320AIC29. By clicking the Init TLV320AIC29button, the control registers (for ADC and audio) revert back to the startup (firmware) default settings.

To restore the TLV320AIC29 EVM to its power-up state, click SW Reset, followed by Init TLV320AIC29.



www.ti.com

3.3 Audio Screens

Program Description

Three tabs control the TLV320AIC29 audio functions: Audio 1, Audio 2, and Audio Effects Filters tabs.

Figure 6 shows the default condition of the Audio 1 tab with the following sections:

• INTERFACE: Audio I2S port• PLL: PLL parameters to get the desired FSref frequency• ADC: Audio ADC, and select the ADC input source• DAC/Outputs: Audio DAC and the all analog output features• GPIO1: GPIO1 function/status• GPIO2: GPIO2 function/status

Figure 6. Audio 1 Screen at Default

12 TLV320AIC29EVM and TLV320AIC29EVM-PDK SLAU179–April 2006Submit Documentation Feedback


www.ti.com

Program Description

Figure 7 shows the default condition of the Audio 2 tab. The functions and setting on Audio 2 mainlycontrol the audio analog inputs with the following sections:

• HeadSet: Headset input power and gain control (PGA or AGC) function and other headset specifiedfunctions.

• HandSet: Handset input power and gain control (PGA or AGC) function and other handset specifiedfunctions.

• Cell Phone: Cell-phone input power and gain control (PGA or AGC) function.• SideTone: Sidetone power and gain.• KeyClick: Key-click tone.• Buzz Input: Power and gain for the BUZZ_IN input pin.

Figure 7. Audio 2 Screen at Default



www.ti.com

Program Description

Figure 8 shows the default configuration of the AudioEffects Filters tab. This tab displays the boost filters,the de-emphasis filter, and the DAC and output driver pop-noise reduction functions.

Figure 8. Bass Boost Filter Screen at Default

3.3.1 Interface Section

This section (refer to Figure 6) controls the behavior of the I2S port (BCLK, LRCLK, DIN, and DOUT pins).In this EVM, the audio port transfers the 16 bit data in I2S format, and the codec reference sample rate isat 44.1 kHz.

The TLV320AIC29 is programmed as a slave by default. The onboard processor TAS1020B is the master,which generates the BCLK and LRCLK signal. If the TLV320AIC29 is used as a master, the onboardprocessor must be disabled and the I2S port must be detached from the processor by turning OFF theonboard I2S interface. Refer to Table 2 for more information about hardware settings.



www.ti.com

Program Description

3.3.2 PLL Section

There is an on-chip phase-locked loop (PLL) on the TLV320AIC29. The PLL can be enabled or disabled,based on the given master clock (MCLK) to the TLV320AIC29 and the required reference frequency(FSref) for the codec. For more details on the PLL, refer to the TLV320AIC29 data sheet.

The PLL can be configured in the PLL Secton of Audio 1 screen (Figure 6).

The default frequencies for this EVM board are• MCLK = 11.2896 MHz• Reference sample rate = 44.1 kHz

At the bottom of the section, the corresponding FSref frequency is shown based on the selection of:

1. the Q-value if the PLL has not been enabled, or2. the P, J, D values if the PLL has been enabled.

3.3.3 ADC Section

This section (Audio 1 Tab, Figure 6) configures the audio ADC power and the analog input source.

By default, the audio ADC is powered up so that the audio-recording function can start to run at the defaultsettings. By checking Power Down ADC, audio ADC power is disabled.

The ADC sample rate can be set as a divider frequency from the reference frequency, FSref. Forexample, when FSref = 44.1 kHz (set at the INTERFACE section of the same tab), an 8-K sample rate isachieved by setting the divider to 5.5 (44100/5.5 = 8018 Hz).

The audio ADC also has a high-pass filter, which is a sub-multiple of the sample rate, to remove dc or lowfrequency components from the input signal.

The input signal to the audio ADC can be selected from different analog resources and under differentmodes using the Select ADC Input Source option list. The microphone input from the headset or thehandset can be selected; the single-ended or the differential input (paired with AUX1 or AUX2) can beused.

The cell-phone input can also be connected to the audio ADC.

3.3.4 DAC/Outputs Section

This section configures the audio DAC power and all functions of the analog outputs, such as power, gain,mode, and destination, which identifies the analog output pin or pins where the analog output signal issent.

In the Power Down subsection, the DAC and the output driver circuits can be powered up/downindividually. By checking a checkbox, the corresponding TLV320AIC29 circuit is powered down.

In the SC Protect subsection, the short-circuit (SC) protection function can be enabled or disabled. Whenthe short-circuit protection function is enabled and a short-circuit occurs, all analog outputs are disabledand the corresponding flag is set. For example, to set the headset SC protection, check the box. In theevent of a headset short circuit, all analog outputs are disabled, and D1 of control registers in page 2address 0x1D is set. The TLV320AIC29 requires hardware or software reset to return to normal operation.

Similar to the ADC, the DAC sample rate can be set as a divider frequency from the reference FSreffrequency, through the DAC Sample Rate option list.

The TLV320AIC29 has the capability to route the stereo DAC output signals to the selected analog output.To route the signals to the headset drivers (SP1 and SP2 pins), select from the DAC Output to lists. Bydefault, the left channel DAC output is routed to SP1 and the right channel to SP2.

The signal routed to SP1 can also be output to the loud speaker (OUT8P/OUT8N), if the SP1 to Loud SPcheckbox is checked.

SP1 can be used in single-ended or differential mode. In single-ended mode, it is driven as one channel ofthe stereo headset outputs, and the audio sound is output through a headset at J11 on theTLV320AIC29EVM daughtercard. In differential mode, the SP1 is paired with the OUT32N pin as thereceiver driver, and the audio sound is output through a speaker connected to the terminal block J2 on theTLV320AIC29EVM. By default, the SP1 is set to single-ended mode.



www.ti.com

Program Description

Other signals, such as the SideTone, KeyClick, CP_IN, and BUZZ_IN can be routed to speaker 1 (SP1),speaker 2 (SP2), and/or the loud speaker (LoudSP). Signal selection can be done in this section bychecking the corresponding checkbox.

The signals to SP1, SP2, or the ADC can be output to the TSC’s cellphone output pin. And the BUZZ_IN,SP1 and SP2 signals can also be output the BUZZ_IN PGA.

The DAC PGA gain, can be set to soft-stepping mode. Under the soft-stepping mode, the soft steppingcan be set to either 0.5–dB per one sample, or 0.5–dB per two samples.

The stereo DAC audio volume is controlled by the left (L) and right ®) volume control slides, selectablethrough setting the master volume controller, in three different ways:• Independent,• Right channel controlled, or• Left channel controlled.

In addition to the left and right DAC channel volume controls and mutes, the analog signals from theSPK1, SPK2, OUT8P/OUT8N (loud speaker), and CP_OUT pins can be individually muted or unmuted.

The TLV320AIC29 supports both capacitor-coupled (cap) and capacitorless (capless) headset interfacesthrough settings in software and hardware. To use the capless outputs, Check the box Enable CaplessHeadset Output, and select the CAPLESS setting on SW1 on the TLV320AIC29EVM daughter board.

Note: The settings of SW1 and Enable Capless Headset Output must match for proper EVMoperation.

3.3.5 GPIO1 and GPIO2 Sections

The two GPIO pins on the TLV320AIC29 are programmed for several different functions, selectablethrough the GPIO1 or GPIO2 section. Refer to the data sheet for more information. When a GPIO pin isused as a digital output, its status can be controlled by the GPO Command to either logic high or low.When not being used, the GPIO pin should be set to high impedance (Hi-Z) status.

3.3.6 Headset Section

The headset section is in the Audio 2 tab, which is used mainly to select the headset-amplifier input gaincontrol between the headset PGA or the AGC, using the Headset/AUX Input AGC ON checkbox.

By default, the AGC is OFF and the programmable gain amplifier (PGA) on the headset circuit is selectedfor the gain control, allowing analog input gain control from 0 dB to 59.5 dB. When the AGC is OFF,moving the volume slide on the AGC OFF subsection adjusts the PGA on the MICIN_HED path andchecking the Mute box mutes the headset input signal.

When the PGA changes from the current value to a newly programmed value, the change rate can becontrolled if the PGA Soft Stepping box is checked in the Head/Handset MIC PGA section, where the PGAchanges 0.5 dB at either 1 step per sample or one step per two samples.

When the box by AGC ON is checked, the AGC is enabled. Refer to the TLV320AIC29 data sheet and theappreciated application note(s) for setting and using the AGC.

In addition to the input gain control, the headset microphone bias can be selected. The programmablede-bounce features for the headset and button detect are also configured in this section. Refer to datasheet for the details on detection and de-bounce.



www.ti.com

Program Description

3.3.7 Handset Section

Similar to the headset section, the handset section is used mainly to configure the handset input gainthrough the handset PGA or the AGC, selectable by the Handset Input AGC ON checkbox.

By default, when the handset AGC is OFF, and the programmable gain amplifier (PGA) is selected for theinput gain control, allowing analog input gain control from 0 dB to 59.5 dB. Under the case (AGC OFF),moving the volume slide on the AGC OFF subsection adjusts the PGA on the MICIN_HND path andchecking the Mute box mutes the handset input signal.

The handset and headset share the soft-stepping settings. Refer to the explanation in the Headset Sectionfor the feature and settings.

Similar to the headset, when the AGC ON box is checked, the handset AGC is enabled.

In addition to the handset input gain control, the handset microphone bias can be selected inside theHandset Section, similar to that in the Headset Section.

3.3.8 Cell-Phone Section

The cell-phone section is used to configure the cell-phone input gain, by using the CP_IN PGA or AGC.

When the Cell Phone Input AGC ON checkbox is not checked, the PGA controls the gain, from –34.5 dBto 12 dB, and in 0.5 dB steps if the soft-stepping option was selected. The cell-phone input is muted whenthe Mute box under the slider is checked.

When the AGC ON box is checked, the cell-phone input AGC is enabled. Refer to the TLV320AIC29 datasheet or the appropriate application report(s) for setting and using the AGC.

At the TLV320AIC29 device, both CP_IN and CP_OUT signals can be at single-ended or differentialmode.

3.3.9 Sidetone Section

The TLV320AIC29 has an analog sidetone circuit. The audio outputs of theTLV320AIC29 include a mixerso that the sidetone can be mixed with the audio output signals, in proportion to their respective volumesettings.

The sidetone is enabled when the PowerUp box is checked. Its volume can be adjusted by the analogvolume control slider, ranging from –34.5 dB to 12 dB, in 0.5-dB steps if the soft-stepping option is used.The sidetone is muted when the Mute box under the slider is checked.

At the EVM power up, the sidetone is powered-up by default.

3.3.10 Keyclick Section

When the Enable Key Click box is checked, a clicking sound is heard when an audio-related setting isselected or checked in the Audio 1, Audio 2 and the Audio Effects Filters screens.

The volume, frequency, and duration (length) of this keyclick can be adjusted using the correspondingslider and selectors.

At the EVM power up, the keyclick is enabled by default.

3.3.11 Buzz Input Section

The buzzer input from the cell phone can be routed to TLV320AIC29 through the BUZZ_IN pin, if thePowerDown checkbox is not selected. This input path supports the PGA range of from –45 dB to 0 dB, in3 dB steps if the soft-stepping option is selected.



www.ti.com

Program Description

3.3.12 Audio Effects

The programmable Audio Effects filters coefficients of the TLV320AIC29 can be accessed at the AudioEffect Filters screen, as shown at the above Figure 8.

Different filter coefficients can be loaded for left and right channels, although typically they are set to thesame values.

If changes are made to coefficient values directly, the response can be viewed on the graph by pressingthe View Response button. It is recommended that the user view the response before downloading valuesto the TLV320AIC29, as some values can cause clipping or oscillation of the filter. The filter equation isdescribed in the TLV320AIC29 data sheet. When the data entered is outside the acceptable range, awarning window appears to indicate the improper coefficient entered, as shown in Figure 9.

Figure 9. Audio Effect Screen With Bad Data

In addition to the direct coefficient settings previously described, there are six preconfigured filtersdesigned with the EVM software, selectable using the drop-down list of this screen. On selection, thecoefficients are updated along with the graph of the filter response to the selection. However, nothing isloaded into the TLV320AIC29 until the Download button is pressed. Checking the Boost Filter box enablesthe filter selected.

3.3.13 De-emphasis Filter

In addition to the boost filter, a de-emphasis filter is provided by TLV320AIC29 for the audio DAC.Checking the Deemphasis Filter On box enables the filter.



www.ti.com

4 Other board Level Connections

4.1 Analog Interface

Other board Level Connections

3.3.14 Power-Up Pop Reductions

Settings on this tab can reduce the pop noise heard at the moment the power is brought up to the outputcircuit of the TLV320AIC29. The pop noise reduction can be set on the DAC or the analog output drivercircuit. Click on the Enable DAC HP PR checkbox to enable the DAC pop-reduction feature, and theEnable Driver PR checkbox to enable the output driver pop-reduction feature. Change the Driver PRDuration to set and optimize the noise reduction effects.

This chapter describes the connectors of the TLV320AIC29 EVM-PDK. Using these board levelconnections, the TLV320AIC29 EVM can work stand-alone or as the daughter-board of theUSBMODEVM.

For maximum flexibility, the TLV320AIC29EVM is designed for easy interface to multiple analog sources.Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 2x10-pindual row header/socket combination at J1 and J2. These headers/sockets provide access to the analoginput and output pins of the device. Table 3 summarizes the analog interface pinout for theTLV320AIC29EVM.

Table 3. Analog Interface Pinout

Pin Number Signal Description

J1.1 CP_IN+ Input from cell-phone module (+)

J1.2 NC Not connected

J1.3 CP_IN– Input from cell-phone module (–)


J1.5 CP_OUT+ Output to cell-phone module (+)


J1.7 CP_OUT– Output to cell-phone module (–)


J1.9 AGND Analog ground

J1.10 VBAT Battery monitor input


J1.12 AUX1 First auxiliary input




J1.16 AUX2 Second auxiliary input




J1.20 REF+ Reference Voltage

J2.1 OUT32N Receiver driver output (–)

J2.2 SPK1 Headset driver output (1) /receiver driver output (+)

J2.3 VGND Virtual ground for audio outputs

J2.4 SPK2 Headset driver output (2)

J2.5 OUT8N Loudspeaker driver output (–)

J2.6 OUT8P Loudspeaker driver output (+)

J2.7 MICBIAS_HED Headset microphone bias voltage

J2.8 MICIN_HED Headset microphone input



www.ti.com

4.2 Digital Interface


Table 3. Analog Interface Pinout (continued)



J2.10 MIC_DETECT_IN Microphone detect input


J2.12 SPKFC Driver feedback/speaker detect input


J2.14 MICIN_HND Handset microphone input


J2.16 MICBIAS_HND Handset microphone bias voltage





In addition to the analog headers, the analog inputs and outputs may also be accessed through alternateconnectors, either screw terminals or audio jacks, listed in Table 4.

Table 4. Analog Connectors

Description Pin1 Pin2 Pin3 Pin4 Pin5

J7 External Inputs VBAT AUX1 AUX2 AGN –

J9 Cell-phone In/Out CP_IN/CP_IN+ BZ_IN/CP_IN– CP_OUT+ CP_OUT– AGND

J10 External MIC Input MICIN_HND Onboard MIC Onboard MIC MICBIAS_HND AGND

J11 Headset MICIN_HED SPK2 SPK1 VGND/GND –

J12 Receiver (OUT32) OUT32N OUT32P – – –

J13 Loud-speaker (OUT8) OUT8N OUT8P – – –

The TLV320AIC29EVM is designed to easily interface with multiple control platforms. Samtec partnumbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 2x10-pin dual rowheader/socket combination at J4 and J5. These headers/sockets provide access to the digital control andserial data pins of the device. Table 5 summarizes the digital interface pinout for the TLV320AIC29EVM.

Table 5. Digital Interface Pinout


J4.1 NC Not Connected

J4.2 GPIO1 General purpose I/O 1

J4.3 SCLK SPI Interface serial clock input

J4.4 DGND Digital ground


J4.6 GPIO2 General purpose I/O 2

J4.7 /SS SPI Interface slave select input

J4.8 /RESET Selectable to TLV320AIC29 reset



J4.11 MOSI SPI serial data mater-OUT-slave-IN


J4.13 MISO SPI serial data mater-IN-slave-OUT

J4.14 /RESET TLV320AIC29 reset



www.ti.com

4.3 Power Supplies


Table 5. Digital Interface Pinout (continued)


J4.15 /DAV /data-available output

J4.16 SCL I2C interface clock line



J4.19 /PWR_DN Hardware power down input

J4.20 SDA I2C interface data line



J5.3 BCLK I2S interface audio bit clock




J5.7 WCLK I2S interface audio word clock




J5.11 DIN I2S interface data input


J5.13 DOUT I2S interface data output



J5.16 SCL I2C interface clock line

J5.17 MCLK Master clock



J5.20 SDA I2C interface data line

J3 provides power connection to the TLV320AIC29. Power is supplied on the pins listed in Table 6.

Table 6. Power Supply Pin Out

Signal Pin Number Signal

NC J3.1 J3.2 NC

+5VA J3.3 J3.4 NC

DGND J3.5 J3.6 AGND

+1.8VD J3.7 J3.8 NC

+3.3VD J3.9 J3.10 +5VD

The TLV320AIC29EVM-PDK motherboard (the USB-MODEVM Interface board) supplies power to J3 ofthe TLV320AIC29EVM. Power for the motherboard is supplied either through its USB connection or viaterminal blocks on that board.



www.ti.com

4.4 External Voltage Reference


4.3.1 Stand-Alone Operation

When used as a stand-alone EVM, power can be applied to J3 directly. The user must reference thesupplies to the appropriate grounds on that connector.

CAUTION

Verify that all power supplies are within the safe operating limits shown on theTLV320AIC29 data sheet before applying power to the EVM.

4.3.2 USB-MODEVM Interface Power

The USB-MODEVM Interface board can be powered from several different sources:

• USB• 6 VDC - 10 VDC AC/DC external wall supply (not included)• Lab power supply

When powered from the USB connection, JMP6 must have a shunt from pins 1–2 (this is the defaultfactory configuration). When powered from 6 V-10 VDC, either through the J8 terminal block or the J9barrel jack, JMP6 must have a shunt installed on pins 2-3. If power is applied in any of these ways,onboard regulators generate the required supply voltages, and no additional power supplies arenecessary.

If lab supplies are used to provide the individual voltages required by the USB-MODEVM Interface, JMP6must have no shunt installed. Voltages are then applied to J2 (+5VA), J3 (+5VD), J4 (+1.8VD), and J5(+3.3VD). The +1.8VD and +3.3VD can also be generated on the board by the onboard regulators fromthe +5VD supply; to enable this configuration, the switches on SW1 need to be set to enable theregulators by placing them in the ON position (lower position, looking at the board with text readingright-side up). If +1.8VD and +3.3VD are supplied externally, disable the onboard regulators by placingSW1 switches in the OFF position.

Each power supply voltage has an LED (D1–D7) that illuminates when the power supply is active.

If the external voltage reference is used, the reference can be input to the TLV320AIC29 device throughthe J8 terminal block.



www.ti.com

5 Physical Description

5.1 Bill of Materials

Physical Description

This chapter contains the bill of materials, the TLV320AIC29 EVM board layout, and the schematics.

Table 7. TLV320AIC29EVM Bill of Materials

Item Qty Value Ref. Des. Description Vendor Part number

1 2 0 Ω R13, R14 1/8 W 5% Chip Resistor Panasonic ERJ-6GEY0R00V

Not 4 0 Ω R9-R12 1/8 W 5% Chip Resistor Panasonic ERJ-6GEY0R00VInstalled

2 1 0 Ω R25, R27 1/4 W 5% Chip Resistor Panasonic ERJ-8GEY0R00V

3 1 220 Ω R15 1/8 W 5% Chip Resistor Panasonic ERJ-6GEYJ221V

4 1 2.2 KΩ R26 1/4 W 5% Chip Resistor Panasonic ERJ-8GEYJ222V

5 3 2.7 KΩ R7, R28, R29 1/10 W 5% Chip Resistor Panasonic ERJ-3GEYJ272V

6 1 2.7 KΩ R8 1/4 W 5% Chip Resistor Panasonic ERJ-8GEYJ272V

7 1 30.1 R6 1/16 W 1% Chip Resistor Panasonic ERJ-3EKF3012VKΩ

8 1 69.8 R5 1/16 W 1% Chip Resistor Panasonic ERJ-3EKF6982VKΩ

9 4 100 R1, R2, R3, R4 1/10 W 5% Chip Resistor Panasonic ERJ-3GEYJ104VKΩ

Not 9 NI R16-R24Installed

10 12 0.1 µF C7-C9, C11-C19 25 V Ceramic Chip Capacitor, +/ - TDK C1608X7R1E104KT10%, X7R

Not 7 0.1 µF C20-C26 25 V Ceramic Chip Capacitor, +/ - TDK C2012X7R1E104KTInstalled 10%, X7R

11 2 0.1 µF C10, C35 100 V Ceramic Chip Capacitor, +/ - TDK C3216X7R2A104KT10%, X7R

12 1 0.33 C1 10 V Ceramic Chip Capacitor, +/ - TDK C1608X5R1A334KTµF 10%, X5R

13 10 10 µF C2-C6, C27-C31 6.3 V Ceramic Chip Capacitor, +/ - TDK C3216X5R0J106KT10%, X5R

14 2 47 µF C36, C37 6.3 V Ceramic Chip Capacitor, +/ - TDK C3225X5R0J476MT20%, X5R

Not 3 NI C32, C33, C34Installed

15 1 U3 Audio Codec Texas Instruments TLV320AIC29IRGZ

16 1 U2 64K, I2C EEPROM Microchip 24AA64-I/SN

17 1 U1 Dual Output LDO Voltage Regulator Texas Instruments TPS767D301PWPG4

18 1 J7 Screw Terminal Block, 4 Position On Shore ED555/4DSTechnology

Not 1 J6 Screw Terminal Block, 4 Position On Shore ED555/4DSInstalled Technology

19 1 J9 Screw Terminal Block, 5 Position On Shore ED555/5DSTechnology

20 3 J8, J12, J13 Screw Terminal Block, 2 Position On Shore ED555/2DSTechnology

21 1 J10 3.5 mm Audio Jack, T-R-S, SMD CUI Inc. SJ1-3515-SMT

22 1 J11 3.5 mm Audio Jack, T-R-S-G, CUI Inc. SJ-43514Thru-Hole

23 4 J1A, J2A, J4A, 20 Pin SMT Plug Samtec TSM-110-01-L-DV-PJ5A

24 4 J1B, J2B, J4B, 20 pin SMT Socket Samtec SSW-110-22-F-D-VS-J5B K



www.ti.com


Table 7. TLV320AIC29EVM Bill of Materials (continued)

Item Qty Value Ref. Des. Description Vendor Part number

25 1 J3A 10 Pin SMT Plug Samtec TSM-105-01-L-DV-P

26 1 J3B 10 pin SMT Socket Samtec SSW-105-22-F-D-VS-K

27 1 N/A TLV320AIC29EVM PWB (must be Texas Instruments 6478197RoHS compliant)

Not 4 NI D1, D2, D3, D4 Schottky Barrier Diode, Series Diodes Inc. BAT54S-7-FInstalled Configuration

28 3 JMP1, JMP2, 2 Position Jumper , 0 .1" spacing Samtec TSW-102-07-L-SJMP11

Not 2 JMP3, JMP4 2 Position Jumper , 0 .1" spacing Samtec TSW-102-07-L-SInstalled

29 2 JMP13, JMP14 3 Position Jumper , 0 .1" spacing Samtec TSW-103-07-L-S

30 2 JMP10, JMP15 3 X 2 Position Header, 0 .1" spacing Samtec TSW-103-07-L-D

31 6 JMP5-JMP9, Bus Wire, 18-22 GaugeJMP12

32 1 MK1 Omnidirectional Microphone Cartridge Knowles Acoustics MD9745APZ-F

33 1 SW1 4PDT Right Angle Switch E-Switch EG4208

Not 42 TP3-TP19, Miniature Test Point Terminal Keystone 5000Installed TP21-TP33, Electronics

TP35-TP46

34 4 TP1, TP2, TP20, Miniature Test Point Large Loop Keystone 5011TP34 Terminal Electronics

35 10 N/A Jumper Top Samtec SNT-100-BK-T



www.ti.com

5.2 TLV320AIC29 EVM (Daughter) Board Layout


Figure 10. Component Layout



www.ti.com


Figure 11. Top PCB Layer



www.ti.com


Figure 12. Power/Ground Plane 1



www.ti.com


Figure 13. Power/Ground Plane 2



www.ti.com


Figure 14. Bottom PCB Layer



www.ti.com

5.3 Schematics


Figure 15. Bottom Silkscreen and Solder Mask

Schematic diagrams of the TSC2111EVM/TLV320AIC29EVM daughter board show the TLV320AIC29analog connections to the external Input/output devices (such as the headphone, or microphone); and thedigital connections to the USB-MODEVM board and other external digital devices through its connectors.



www.ti.com

IOV

DD

C28

10u

F

C27

10u

F

+3.3

VA

C4

10u

F

R3

100K

R26

2.2

K

J10

SJ1-3

515-S

MT

C10

0.1

uF

C6

10u

F

R22

NI

R27

0

1 2 3

JM

P13

MIC

BIA

SS

EL

+3.3

VA

TP

20

DV

SS

TP

41

MIC

BIA

S_H

ND

C5

10u

FD

OU

T

DIN

WC

LK

BC

LK

MC

LK

SC

LK

SS

MO

SI

MIS

O

PIN

TD

AV

+1.8

VD

IOV

DD

C37

47u

F

C36

47u

F

MK

1

MD

9745A

PZ

-FR

9

0

R10 0

R11 0

R12 0

C21

0.1

uF

C22

0.1

uF

C23

0.1

uF

C24

0.1

uF

1 2 3 4

J7

ED

555/4

DS

VB

AT

AU

X1

AU

X2

GN

D

R15 2

20

R13 0

R14 0

C20

0.1

uF

C25

0.1

uF

C26

0.1

uF

1 2 3 4

J6

ED

555/4

DS

TO

UC

HS

CR

EE

N

EX

TE

RN

AL

INP

UT

S

EX

TM

ICIN

MIC

RO

PH

ON

E

X-

Y+

X+

Y-

C31

10u

F

+3.9

VA

SW

1

ES

W_E

G4208

R8

2.7

K

C35

0.1

uF

C11

0.1

uF

C8

0.1

uF

C15

0.1

uF

C16

0.1

uF

C14

0.1

uF

C9

0.1

uF

CE

LL

I/O

CP

IN/C

PIN

+

CP

OU

T/C

PO

UT

+

BU

ZZ

IN/C

PIN

-

12

J12

OU

T32

12

J13

OU

T8

PLU

S

MIN

US

PLU

S

MIN

US

TP

9

CP

_IN

TP

26

CP

_O

UT

TP

25

BU

ZZ

_IN

TP

7

VB

AT

TP

10

AU

X2

TP

8

AU

X1

TP

3

X-

TP

4

Y+

TP

5

X+

TP

6

Y-

TP

18

IOV

DD

TP

19

DV

DD

TP

12

SD

IN

TP

13

LR

CLK

TP

11

SD

OU

T

TP

14

BC

LK

TP

17

MC

LK

TP

16

BV

DD

TP

27

AV

DD

1

TP

42

MIC

IN_H

ND

TP

29

MIC

IN_H

ED

TP

31

MIC

BIA

S_H

ED

TP

46

OU

T32N

TP

43

SP

K2

TP

44

SP

K1

TP

33

SP

KF

C

TP

45

VG

ND

TP

35

OU

T8P

TP

32

OU

T8N

TP

36

GP

IO2

TP

38

GP

IO1

TP

21

PW

R_

DN

Z

TP

22

RE

SE

TZ

TP

37

PE

N_IR

QZ

TP

23

SP

IDO

UT

TP

24

SP

I_C

SZ

TP

39

SP

IDIN

TP

40

SP

ICLK

TP

34

AV

SS

TP

30

MIC

_D

ET

EC

T_IN

C12

0.1

uF

C13

0.1

uF

R4

100K

R20

NI

R21

NI

R23

NI

R24

NI

IOV

DD

1 2

J8

ED

555/2

DS

R16

NI

R18

NI

R17

NI

R19

NI

EX

TV

RE

F

135

246

JM

P15

DIF

F.M

ICIN

PU

T

AU

X1

AU

X2

C18

0.1

uF

C19

0.1

uF

12

JM

P12

C2

0th

rou

gh

C2

6are

no

tin

sta

lled

,b

ut

can

be

ad

de

dfo

rn

ois

efilte

rin

g.

J11

CU

I_S

J-4

3514-S

MT

HE

AD

SE

TIN

PU

T

12

JM

P3

JP

R-2

X1

12

JM

P4

JP

R-2

X1

C33

NI

R25

0C

32

NI

C34

NI

RE

SE

T

R1

6th

rou

gh

R1

9,JM

P3

an

dJM

P4

are

no

tin

sta

lled

,b

utca

nb

eu

se

d

for

resis

tance

measu

rem

ents

on

the

AU

Xp

ins.

R2

0,R

21,R

23

an

dR

24

are

no

t

insta

lled

,b

utcan

be

use

das

pu

llu

ps

or

pu

lld

ow

ns

on

the

GP

IOlin

es.

C3

2,C

33,an

dC

34

are

no

tin

sta

lled

,b

utcan

be

use

dto

filte

r n

ois

e

on

mic

rop

ho

ne

bia

s

ou

tpu

ts.

JM

P1

5is

use

dto

se

lect

AU

Xin

pu

tsfo

rd

iffe

ren

tial

mic

rop

ho

ne

inp

utm

od

e.

C17

0.1

uF

C30

10u

F

C29

10u

F

12

JM

P9

TP

28

AV

DD

2

D1A

NI

D1B

NI

D2A

NI

D3B

NI

D3A

NI

D4A

NI

D2B

NI

D4B

NI

+3.3

VA

D1

thro

ug

hD

4a

ren

otin

sta

lled

,b

utcan

be

ad

de

d

for

extr

aE

SD

pro

tectio

n,o

rfo

rre

du

cin

gto

uch

pan

eln

ois

e.

12

JM

P5

12

JM

P8

12

JM

P6

12

JM

P7

TP

15

DR

VD

D

PW

R_

DW

N

PLE

AS

EN

OT

E:

Com

po

nents

within

dashed

box

are

no

tin

clu

ded

on

the

AIC

29

vers

ion

ofth

eboard

.

IOVDD1

X+

9

Y+

10

X-

11

Y-

12

PWR_DN2

VB

AT

15

CP

_IN

/CP

_IN

+20

CP

_O

UT

/CP

_O

UT

+19

BU

ZZ

_IN

/CP

_IN

-18

VR

EF

14

AU

X1

17

PINTDAV37

MISO40

MOSI39

SS38

SCLK41

AVDD26

AVSS27

DVSS48

DVDD47

RESET3

BVDD34

DRVDD29

MCLK42

BCLK46

WCLK45

SDIN44

SDOUT43

DRVSS132

GPIO15

GPIO24

AU

X2

16

DRVSS236

AVSS113

OU

T8P

35

OU

T8N

33

MIC

BIA

S_H

ND

22

MIC

IN_H

ND

21

MIC

_D

ET

EC

T_IN

25

MIC

IN_H

ED

23

MIC

BIA

S_H

ED

24

SP

K1

27

SP

K2

28

SP

KF

C30

VG

ND

/CP

_O

UT-

31

OU

T32N

26

AVDD18

U3

TS

C2111IR

GZ

/TLV

320A

IC29IR

GZ GP

IO1

GP

IO2

1 2 3 4 5

J9

ED

555/5

DS

CP

OU

T-

1 2 3

JM

P14

JP

R-1

X3

CP

_IN

+

CP

_IN

-

CP

_O

UT

+

CP

_O

UT-

X-

Y+

X+

Y-

VB

AT

AU

X1

AU

X2

RE

F+

SP

K1

OU

T32N

OU

T8P

OU

T8N

SP

KF

C

VG

ND

SP

K2

MIC

BIA

S_H

ND

MIC

IN_H

ND

MIC

BIA

S_H

ED

MIC

_D

ET

EC

T_IN

MIC

IN_H

ED


Figure 16. TSC2111EVM/TLV320AIC29EVM Schematic, Page 1



www.ti.com

GP

IO0

2

DG

ND

4

GP

IO1

6

GP

IO2

8

DG

ND

10

GP

IO3

12

GP

IO4

14

SC

L16

DG

ND

18

SD

A20

CN

TL

1

CLK

X3

CLK

R5

FS

X7

FS

R9

DX

11

DR

13

INT

15

TO

UT

17

GP

IO5

19

J4

DA

UG

HT

ER

-SE

RIA

L

12

JM

P1

A0(+

)2

A1(+

)4

A2(+

)6

A3(+

)8

A4

10

A5

12

A6

14

A7

16

RE

F-

18

RE

F+

20

A0(-

)1

A1(-

)3

A2(-

)5

A3(-

)7

AG

ND

9

AG

ND

11

AG

ND

13

VC

OM

15

AG

ND

17

AG

ND

19

J1

DA

UG

HT

ER

-AN

ALO

G

-VA

2

-5V

A4

AG

ND

6

VD

18

+5V

D10

+V

A1

+5V

A3

DG

ND

5

+1.8

VD

7

+3.3

VD

9

J3

DA

UG

HT

ER

-PO

WE

R

GP

IO0

2

DG

ND

4

GP

IO1

6

GP

IO2

8

DG

ND

10

GP

IO3

12

GP

IO4

14

SC

L16

DG

ND

18

SD

A20

CN

TL

1

CLK

X3

CLK

R5

FS

X7

FS

R9

DX

11

DR

13

INT

15

TO

UT

17

GP

IO5

19

J5

DA

UG

HT

ER

-SE

RIA

L

A0(+

)2

A1(+

)4

A2(+

)6

A3(+

)8

A4

10

A5

12

A6

14

A7

16

RE

F-

18

RE

F+

20

A0(-

)1

A1(-

)3

A2(-

)5

A3(-

)7

AG

ND

9

AG

ND

11

AG

ND

13

VC

OM

15

AG

ND

17

AG

ND

19

J2

DA

UG

HT

ER

-AN

ALO

G

MC

LK

BC

LK

WC

LK

DIN

DO

UT

MIS

O

MO

SI

SS

SC

LK

RE

SE

T

GP

IO1

GP

IO2

SD

A

SC

L

TP

1

AG

ND

TP

2

DG

ND

J1A

(TO

P)

=S

AM

_T

SM

-110-0

1-L

-DV

-P

J1B

(BO

TT

OM

)=

SA

M_

SS

W-1

10-2

2-F

-D-V

S-K

J4A

(TO

P)

=S

AM

_T

SM

-110-0

1-L

-DV

-P

J4B

(BO

TT

OM

)=

SA

M_

SS

W-1

10-2

2-F

-D-V

S-K

J2A

(TO

P)

=S

AM

_T

SM

-110-0

1-L

-DV

-P

J2B

(BO

TT

OM

)=

SA

M_

SS

W-1

10-2

2-F

-D-V

S-K

J5A

(TO

P)

=S

AM

_T

SM

-110-0

1-L

-DV

-P

J5B

(BO

TT

OM

)=

SA

M_

SS

W-1

10-2

2-F

-D-V

S-K

J3A

(TO

P)

=S

AM

_T

SM

-105-0

1-L

-DV

-P

J3B

(BO

TT

OM

)=

SA

M_

SS

W-1

05-2

2-F

-D-V

S-K

VB

AT

AU

X1

X+

X-

CP

_IN

+

CP

_IN

-

+1.8

VD

+3.3

VD

AU

X2

Y+

Y-

CP

_O

UT

+

CP

_O

UT-

OU

T8N

OU

T8P

SP

K2

SP

K1

MIC

BIA

S_H

ED

MIC

_D

ET

EC

T_IN

VG

ND

OU

T32N

MIC

IN_H

ED

SP

KF

C

+5V

A

VC

C8

VS

S4

SDA5

SCL6

A01

A12

A23

WP7

U2

24A

A64I/S

N

C7

0.1

uF

IOV

DD

R7

2.7

K

12

JM

P21

2

JM

P11

RE

SE

T

PIN

TD

AV

PW

R_

DW

N+

3.3

VA

C2

10u

F

C1

0.3

3u

F

R1

100K

R2

100K

C3

10u

F

1G

ND

3

1E

N4

1IN

5

1IN

6

2G

ND

9

2E

N10

2IN

11

2IN

12

2O

UT

17

2O

UT

18

2R

ES

ET

22

1O

UT

23

1O

UT

24

1R

ES

ET

28

1F

B25

U1

TP

S767D

301P

WP

R5

69.8

K

R6

30.1

K

+3.9

VA

+5V

A

12

34

56

JM

P10

IOV

DD

IOV

DD

+3.3

VD+

5V

D

+1.8

VD

+5V

D

RE

F+

MIC

IN_H

ND

MIC

BIA

S_H

ND

R29

2.7

K

R28

2.7

K

IOV

DD


Figure 17. TSC2111EVM/TLV320AIC29EVM Schematic, Page 2



www.ti.com

J9

CU

I-S

TA

CK

PJ102-B

YE

LL

OW

2.5

MM

6V

DC

-10V

DC

IN

C15

0.1

uF

CSCHNE32

CRESET34

CSYNC35

CDATI36

CSCLK37

MCLKO139

MCLKO240

RESET41

VREN42

SDA43

SCL44

XTA

LO

46

XTA

LI

47

PL

LF

ILI

48

PL

LF

ILO

1

MC

LK

I3

PU

R5

DP

6

DM

7

MRESET9

DV

SS

4

DV

SS

16

DV

SS

28

AV

SS

45

TEST10

EXTEN11

CDATO38

RSTO12

NC20

NC22

P3.013

P3.114

P3.2/XINT15

P3.317

P3.418

P3.519

AV

DD

2D

VD

D33

DV

DD

21

DV

DD

8P

1.0

23

P1.1

24

P1.2

25

P1.3

26

P1.4

27

P1.5

29

P1.6

30

P1.7

31

U8

TA

S1020B

PF

B

VC

C1

D-

2D

+3

GN

D4

J7

897-3

0-0

04-9

0-0

00000

R9

1.5

K

R10

27.4

R11

27.4

C13

47pF

C14

47pF

1

2

3

JM

P6

PW

R S

ELE

CT

C20 1

00pF

C21

.001uF

R1

2

3.0

9K

X1

MA

-505 6

.000M

-C0

C18

33pF

C19

33pF

+3.3

VD

VC

C8

VS

S4

SDA5

SCL6

A01

A12

A23

WP7

U1

24LC

64I/S

N

+3.3

VD C

9

1uF

TP

9

TP

10

R3

2.7

K

R5

2.7

K

+3.3

VD

MC

LK

BC

LK

LR

CLK

I2S

DIN

I2S

DO

UT

INT

MIS

O

MO

SI

SS

SC

LK

R1

3

649

+3.3

VD

R4

10

C10

1uF

C11

1uF

C12

1uF

US

BS

LA

VE

CO

NN

EX

TP

WR

IN

6.0

0 M

HZ

RE

D

1O

E1

1A

2

1Y

3

2O

E4

2A

5

2Y

6

GN

D7

3Y

8

3A

9

3O

E10

4Y

11

4A

12

4O

E13

VC

C14

U3

SN

74LV

C125A

PW

1O

E1

1A

2

1Y

3

2O

E4

2A

5

2Y

6

GN

D7

3Y

8

3A

9

3O

E10

4Y

11

4A

12

4O

E13

VC

C14

U4

SN

74

LV

C125A

PW

24

5 3

U5

SN

74LV

C1G

07D

BV

IOV

DD

IOV

DD

C23

1uF

R6

2.7

K

C22

1uF

IOV

DD

C27

1uF

+3.3

VD

24

5 3

U7

SN

74LV

C1G

07D

BV

C26

1uF

R7

2.7

K

+3

.3V

D

+3.3

VD

IOV

DD

+1.8

VD

+3.3

VD

IOV

DD

R8

2.7

K

+3.3

VD

24

5 3

U6

SN

74LV

C1G

07D

BV

IOV

DD

C25

1uF

TP

11

MR

ES

ET

3.3

VD

EN

AB

LE

1.8

VD

EN

AB

LE

C17

0.3

3uF

C7

10uF

1G

ND

3

1E

N4

1IN

5

1IN

6

2G

ND

9

2E

N10

2IN

11

2IN

12

2O

UT

17

2O

UT

18

2R

ES

ET

22

1O

UT

23

1O

UT

24

1R

ES

ET

28

U9

TP

S767D

318P

WP

R18

100K

R17

100K

+3.3

VD

C8

10uF

D5

SM

L-L

X0603IW

-TR

D2

SM

L-L

X0

60

3Y

W-T

R

D4

SM

L-L

X0

60

3G

W-T

R

R19

220

GR

EE

N

US

B I2S

US

B M

CK

US

B S

PI

US

B S

PI

US

B I2S

US

B M

CK

+1.8

VD

RE

SE

T

C24

1uF

US

BA

CT

IVE

US

B R

ST

US

B R

ST

2 4 6

1 3 5 78

910

11

12

J1

5

EX

TE

RN

AL

SP

I

2 4 6

1 3 5 78

910

11

12

J14

EX

TE

RN

AL

AU

DIO

DA

TA

PW

R_

DW

N

J10

EX

TM

CLK

R20

75

IOV

DD

1 2 3 4 5 6 7 8

16

15

14

13

12

11

10 9

SW

2

SW

DIP

-8

EX

TM

CK

2 4

1 3

J6

EX

TE

RN

AL

I2C

IOV

DD

Q1

ZX

MN

6A

07F

Q2

ZX

MN

6A

07F

12

34

56

JM

P7

IOV

DD

SE

LE

CT

+5V

D

SD

A

SC

L

+5V

D R15

10K

R16

10K

14

23

SW

1

RE

GU

LA

TO

R E

NA

BLE

VIN

3V

OU

T2

GND1

U2

RE

G1117-5

D1

DL4001

C16

0.3

3uF

C6

10uF

P3.3

P3.4

P3.5

P1.0

P1.1

P1.2

P1.3

J8

ED

555/2

DS

TP

6

D3

SM

L-L

X0

60

3G

W-T

R

R14

390

GR

EE

N

A0

A1

A2

12

JM

P8

12

JM

P9

12

JM

P10

12

JM

P11

12

JM

P12

12

JM

P13

12

JM

P14

24

1

5 3

U10

SN

74LV

C1G

125

DB

V

C28

1uF

RA

1

10

K


Figure 18. USB Board Schematic, Page 1



www.ti.com

GP

IO0

2

DG

ND

4

GP

IO1

6

GP

IO2

8

DG

ND

10

GP

IO3

12

GP

IO4

14

SC

L16

DG

ND

18

SD

A20

CN

TL

1

CLK

X3

CLK

R5

FS

X7

FS

R9

DX

11

DR

13

INT

15

TO

UT

17

GP

IO5

19

J12

DA

UG

HT

ER

-SE

RIA

L

+5V

D

+5V

A

12

JM

P2

12

JM

P1

JP

R-2

X1

+5V

A+

5V

D

J2

+5V

A

J3

+5V

D

+5V

A+

5V

DC

2

10uF

C3

10uF

J4

+1.8

VD

J5

+3.3

VD

C4

10uF

C5

10uF

J1

-5V

A

C1

10uF

A0(+

)2

A1(+

)4

A2(+

)6

A3(+

)8

A4

10

A5

12

A6

14

A7

16

RE

F-

18

RE

F+

20

A0(-

)1

A1(-

)3

A2(-

)5

A3(-

)7

AG

ND

9

AG

ND

11

AG

ND

13

VC

OM

15

AG

ND

17

AG

ND

19

J11

DA

UG

HT

ER

-AN

AL

OG

GP

IO0

2

DG

ND

4

GP

IO1

6

GP

IO2

8

DG

ND

10

GP

IO3

12

GP

IO4

14

SC

L16

DG

ND

18

SD

A20

CN

TL

1

CLK

X3

CLK

R5

FS

X7

FS

R9

DX

11

DR

13

INT

15

TO

UT

17

GP

IO5

19

J22

DA

UG

HT

ER

-SE

RIA

L

+5V

D

+5V

A

A0(+

)2

A1(+

)4

A2(+

)6

A3(+

)8

A4

10

A5

12

A6

14

A7

16

RE

F-

18

RE

F+

20

A0(-

)1

A1(-

)3

A2(-

)5

A3(-

)7

AG

ND

9

AG

ND

11

AG

ND

13

VC

OM

15

AG

ND

17

AG

ND

19

J21

DA

UG

HT

ER

-AN

AL

OG

+1.8

VD

+3.3

VD

+1.8

VD

+3.3

VD

1

2

3

JM

P5

12

JM

P3

12

JM

P4

R2

2.7

K

R1 2.7

K

IOV

DD

-5V

A

-5V

A

-5V

A

MC

LK

BC

LK

LR

CLK

I2S

DIN

I2S

DO

UT

MIS

O

MO

SI

SS

SC

LK

RE

SE

T

INT

PW

R_D

WN

P3.3

P3.4

P3.5

P1.0

SD

A

SC

L

P1.1

P1.2

P1.3

TP

1T

P2

TP

3

TP

5

TP

4

TP

7

AG

ND

TP

8

DG

ND

R21

390

R22

390

D7

SM

L-L

X0

60

3G

W-T

R

GR

EE

N

D6

SM

L-L

X0

60

3G

W-T

R

GR

EE

N

J11

A(T

OP

) =

SA

M_

TS

M-1

10

-01

-L-D

V-P

J11B

(B

OT

TO

M)

= S

AM

_S

SW

-110-2

2-F

-D-V

S-K

J1

2A

(TO

P)

= S

AM

_T

SM

-11

0-0

1-L

-DV

-PJ12B

(B

OT

TO

M)

= S

AM

_S

SW

-110-2

2-F

-D-V

S-K

J1

3A

(TO

P)

= S

AM

_T

SM

-10

5-0

1-L

-DV

-P

J13B

(B

OT

TO

M)

= S

AM

_S

SW

-105-2

2-F

-D-V

S-K

J2

1A

(TO

P)

= S

AM

_T

SM

-11

0-0

1-L

-DV

-P

J21B

(B

OT

TO

M)

= S

AM

_S

SW

-110-2

2-F

-D-V

S-K

J2

2A

(TO

P)

= S

AM

_T

SM

-11

0-0

1-L

-DV

-PJ22B

(B

OT

TO

M)

= S

AM

_S

SW

-110-2

2-F

-D-V

S-K

J2

3A

(TO

P)

= S

AM

_T

SM

-10

5-0

1-L

-DV

-PJ23B

(B

OT

TO

M)

= S

AM

_S

SW

-105-2

2-F

-D-V

S-K

-VA

2

-5V

A4

AG

ND

6

VD

18

+5V

D10

+V

A1

+5V

A3

DG

ND

5

+1.8

VD

7

+3.3

VD

9

J13

DA

UG

HT

ER

-PO

WE

R

-VA

2

-5V

A4

AG

ND

6

VD

18

+5V

D10

+V

A1

+5V

A3

DG

ND

5

+1.8

VD

7

+3.3

VD

9

J23

DA

UG

HT

ER

-PO

WE

R


Figure 19. USB Board Schematic, Page 2



IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TI’s termsand conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of allparameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible fortheir products and applications using TI components. To minimize the risks associated with customer productsand applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or processin which TI products or services are used. Information published by TI regarding third-party products or servicesdoes not constitute a license from TI to use such products or services or a warranty or endorsement thereof.Use of such information may require a license from a third party under the patents or other intellectual propertyof the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is withoutalteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproductionof this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable forsuch altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for thatproduct or service voids all express and any implied warranties for the associated TI product or service andis an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and applicationsolutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio

Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DSP dsp.ti.com Broadband www.ti.com/broadband

Interface interface.ti.com Digital Control www.ti.com/digitalcontrol

Logic logic.ti.com Military www.ti.com/military

Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork

Microcontrollers microcontroller.ti.com Security www.ti.com/security

Telephony www.ti.com/telephony

Video & Imaging www.ti.com/video

Wireless www.ti.com/wireless

Mailing Address: Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

Copyright 2006, Texas Instruments Incorporated

http://amplifier.ti.com

http://dataconverter.ti.com

http://dsp.ti.com

http://interface.ti.com

http://logic.ti.com

http://power.ti.com

http://microcontroller.ti.com

http://www.ti.com/audio

http://www.ti.com/automotive

http://www.ti.com/broadband

http://www.ti.com/digitalcontrol

http://www.ti.com/military

http://www.ti.com/opticalnetwork

http://www.ti.com/security

http://www.ti.com/telephony

http://www.ti.com/video

http://www.ti.com/wireless

TLV320AIC29EVM and TLV320AIC29EVM-PDK User's Guide · 2019. 11. 15. · Connect 2 ~ 3: from...

Documents

Transcript of TLV320AIC29EVM and TLV320AIC29EVM-PDK User's Guide · 2019. 11. 15. · Connect 2 ~ 3: from...