TLC: Transmission Line Caches Brad Beckmann David Wood Multifacet Project University of...

TLC: Transmission Line Caches

Brad Beckmann

David Wood

Multifacet Project

http://www.cs.wisc.edu/multifacet/

University of Wisconsin-Madison

12/3/03

Beckmann & Wood

MICRO ’03 - TLC: Transmission Line Caches 2

Overview

• Problem: Global interconnect• Opportunity: On-chip transmission lines

– What are they?– Why now?

• Application: Large on-chip caches• Solution: TLC: Transmission Line Caches

+ Consistent high performance+ Simple logical design+ Less substrate area– Circuit verification– Wafer manufacturing cost

Beckmann & Wood


Outline

• Problem: Global interconnect

• Opportunity: On-chip transmission lines

• Application: Large on-chip caches

• Solution: TLC: Transmission Line Caches

• Evaluation

• Conclusions

Beckmann & Wood


Global Interconnect Problem

• Global interconnect latency → Bottleneck– RC delay dominant– Held constant using repeaters– Doesn’t scale with transistors

• Large structures particularly hurt– Partitioning mitigates intra-partition delay – Performance dominated by inter-partition delay

Beckmann & Wood


Conventional Solution

• ↑ wire size → ↓ RC delay+ 3x size → 3x reduced delay+ ↑ wire segment length– 3x channel area– Doesn’t scale

• Intrinsic repeater delay• Inductive effects

A Better Solution?

Beckmann & Wood


Outline




• Solution: TLC - Transmission Line Caches

• Evaluation

• Conclusions

Beckmann & Wood


RC vs. TL CommunicationConventional Global RC Wire

On-chip Transmission Line

Voltage Voltage

DistanceVt

Driver Receiver

Voltage Voltage

DistanceVt

Driver Receiver

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RC Wire vs. TL Design

RC delay dominated

ReceiverDriver

On-chip Transmission Line

Conventional Global RC Wire

LC delay dominated

~0.375 mm

~10 mm

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On-chip Transmission Lines

• Why now? → 2010 technology– Relative RC delay ↑– Improve latency by 10x or more

• What are their limitations?– Require thick wires and dielectric spacing– Increase wafer cost

Presents a different Latency/Bandwidth Tradeoff

Beckmann & Wood


Link Latency

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0.5 1 1.5 2 2.5 3

Length (cm)

Lat

ency

(cy

cles

)

Repeated RC

Single TL

Link Latency

0

10

20

30

40

50

0.5 1 1.5 2 2.5 3

Length (cm)

Lat

ency

(cy

cles

)

Repeated RC

Single TL

Latency Comparison

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Bandwidth Comparison

2 transmission line signals

50 conventional signals

Key observation• Transmission lines – route over large structures• Conventional wires – substrate area & vias for repeaters

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Outline




• Solution: TLC: Transmission Line Caches

• Evaluation

• Conclusions

Beckmann & Wood


Texas Non-uniform Cache Architectures (NUCA)

Bank

Switch

SNUCA – statically partitions addresses across the banks

CacheController

Request 0x….3Request 0x….C

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Texas DNUCA Solution

A BIssues with DNUCA• Locating cache blocks

• Power consumed accessing distant banks

• 15% of total area devoted to routing channels

Frequently requested blocks migrate towards the cache controller

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Outline





• Evaluation

• Conclusions

Beckmann & Wood


TLC - Transmission Line Cache

512 KBBank

TLC Cache Controller

TL Drivers &Receivers

TL link2x8 bytes

High bandwidth, low latency interface between the controller and banks

Beckmann & Wood


TLC Cache Controller

Repeaters

Multi-cycledelay

CentralCache

ControllerLogic

TransmissionLines

Latches

TransmissionLineTransceivers

Transmission Lines

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Outline





• Evaluation

• Conclusions

Beckmann & Wood


Methodology

• Assumptions– ITRS projection for 2010

• 45 nm technology• Low-k (2.1) intermetal dielectric

– 10 GHz operational frequency• Physical Evaluation

– Linpar RLC extractor– Hspice W element transmission line

• Performance Evaluation– Full system simulation– Simics extended with an Out-of-Order processor and

memory system timing models

Beckmann & Wood


Cache Characteristics

Cache

Design

Total Size

Banks Bank Size Bank Access

Time

Uncontended

Latency

SNUCA 16 MB 32 512 KB 8 cycles 9 – 32 cycles

DNUCA 16 256 64 3 3 – 47

TLC 16 32 512 8 10 – 16

• Exclusive write-back caches

• 4 wide, 30 stage pipeline, OoO processor

• 300 cycle memory latency

Beckmann & Wood


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Benchmarks

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SNUCA

DNUCA

TLC

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SNUCA

DNUCA

TLC

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SNUCA

DNUCA

TLC

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SNUCA

DNUCA

TLC

Performance

SpecINT SpecFP Commercial

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Substrate Area

Cache

Design

Storage

Area

Channel

Area

Controller Area

Total

Area

D-NUCA 92 mm2 17 mm2 1.1 mm2 110 mm2

TLC 77 3.1 10 91*

• On-chip transmission lines allow direct routing from the driver to receiver without repeaters

• Facilitates compact layout• Devotes less substrate area to the routing channels

* 18% reduction

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Link Utilization

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Benchmarks

Lin

k U

tiliz

ati

on

(%

)

TLC

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Optimized TLC Designs

• Utilize fewer transmission lines– Base design: requires 2k transmission lines– Opt designs: require 1k, 500, & 350

• Reduce manufacturing cost

• Increase logic complexity

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Benchmarks

Lin

k U

tiliz

ati

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(%

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TLC

TLCopt 1000

TLCopt 500

TLCopt 350

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Benchmarks

Lin

k U

tiliz

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TLC

TLCopt 1000

TLCopt 500

TLCopt 350

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Benchmarks

Lin

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ati

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(%

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TLC

TLCopt 1000

TLCopt 500

TLCopt 350

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Benchmarks

Lin

k U

tiliz

atio

n (%

)

TLC

TLCopt 1000

TLCopt 500

TLCopt 350

Link Utilization (TLC Family)

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Performance (TLC Family)

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TLC

TLCopt 1000

TLCopt 500

TLCopt 350

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Conclusions 1

• Transmission lines offer a different latency/bandwidth tradeoff

• Advantages– Lower latency for global links– Direct routing over large structures

• Limitations– Large, sparsely populated, metal layers– Greater circuit verification effort

Beckmann & Wood


Conclusions 2

• Possible application: TLC• Advantages

– Consistent high performance– Simpler logical design– 18% less substrate area– Less power in the communication network

• Disadvantages– Circuit verification– Wafer cost

Beckmann & Wood


Other Applications?

Beckmann & Wood


TL link2x126 bitsTL link2x64 bitsTL link2x44 bits

Optimized TLC Designs

1 MBBank

TLCopt 1000

• Blocks are partitioned across 2 banks

• Each transmission line link is 126 bits wide

• 1008 total data TLs

TLCopt 500




TLCopt Cache Controller

TLCopt 350




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Equake Performance

Misses per 1K Instructions

012345678

TLCLRU

TLC 4-way

TLC 8-way

TLC 16-way

TLC 32-way

DNUCA

Cache Design

Mis

ses

per

1K

In

str.

Executed Cycles

0.E+001.E+082.E+083.E+084.E+085.E+086.E+087.E+08

TLC LR

U

TLC 4-

way

TLC 8-

way

TLC 16

-way

TLC 32

-way

DNUCA

Cache Design

Cyc

les

Beckmann & Wood


Additional Transceiver Delay

TLC: Transmission Line Caches Brad Beckmann David Wood Multifacet Project University of...

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