Title, Note, Block Diagram€¦ · 5 5 4 4 3 3 2 2 1 1 d d c c b b a a max10 i2c1 master aux1 hsc...
Transcript of Title, Note, Block Diagram€¦ · 5 5 4 4 3 3 2 2 1 1 d d c c b b a a max10 i2c1 master aux1 hsc...
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DESCRIPTION
31
30
3233
36
3738
39
404142
43444546474849
5051525354
3435
55
56
57
58
59
60
61
6263
20
28
27
56
29
21
3
4
7
98
1112
1413
1516
18
17
19
10
22
21
23
24
26
25
PAGE
6465
66
Title, Note, Block Diagram
Diag - Power Tree
Diag - Power SequenceDiag - I2CDiag - Clock
S10 DX ConfigurationS10 DX Bank 2A,B,C,I,FS10 DX Bank 2JS10 DX Bank 2K,L,M,NS10 DX Bank 3A,B,C,D
S10 DX Bank 3H,LDiag - JTAG
S10 DX Xcvr GXER 9AS10 DX Xcvr GXBL 10A,10B
S10 DX Bank 3I,J,K
S10 DX Xcvr GXBR 11B,11CS10 DX Bank WHRDiag - Reset Tree
S10 DX Power
S10 DX Ground
PCIe Edge Gold Fingers
Board System Clocks
Max10 System Controller
Diag - Board Outline
QSFP2 User PB, SW, I/OsUSB Blaster IITemp Sense & Power Monitor
Title, Note, Block Diagram
UPI0 LINK
UPI1 LINKUPI2 LINK
zQSFP Port Controller
QSFP1
DDR4_CH0_Part1
DDR4_CH0_part2DDR4_CH0_part3DDR4_CH0_part4DDR4_CH1_part1
DDR4_CH1_part2
DDR4_CH1_part3DDR4_CH1_part4
DDR4/DDRT Dimms-CH0
DDR4/DDRT Dimms-CH1Power-S10_VCCH_GXEPower-S10_VCCH_GXPPower-S10_VCCCLK_GXE
12V AUX 2 HotswapBlankBlank
S10 DecouplingPower-1.8VPower- S10 VCCPT_1.8V
12V_PCIE Hotswap12V_AUX 1 HotswapFast Power-Down Discharge
Power - VCCcore part1
Power - 5VPower - Max10 BMC
Power - VCCcore part4
Power - VCCcore part3Power - VCCcore part2
Power - 2.4V VCCPFUSE_SDMPower - 3.3V_REG_INSTPower - VCCERAM
Power-1V2_DDR4_CH11Power - 2V5_DDR4, DDR4_VTT
Power-1V2_DDR4_CH00
Level Translators 1
67
68
69 Level Translators 2
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
1 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
1 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
1 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
12VATX 2x4(150W)
12.5A
12VPCIe Slot
(65W)
HSCMAX16550
U217
12V_AUX2
HSCMAX16550
U96
12V_AUX2_IN
LTC4357Ideal Diode
Ctlr
5V0 12V_PCIE_IN
240W POWER ADAPTER
20A
iSL68137 + 5X iSL99227
0.85V@110A
ER2120QI5.0V@2A
U99
5V
1A
EM2130H3.3V@30A
U101
3.3V_REG_INST
3.3V
VCC_EN
3.3V_REG_EN
EM22600.9V@60A
U230
S10_VCCRT_GXP
LC
S10_VCCRT _GXE
S10_VCCPLLDIG_SDMF
BEAD
LC
VCCERAM_EN
0.9V@53A
0p9V
93.5W
41.79A
7.6A
4A
0.5A
4.5A
0.01A
Group 1
Group 2
Group 3
Power-up Sequence
Power on
U97
U136
S10DX FPGA DEVKIT PWR TREE
3.3V_REG
Power-down Sequence
Group 3
Group 2
Group 1
EM2130H1.8V@30A
U113
S10_G2_1.8V
1.8V_EN
1.8V@18A
BEAD
S10_VCCFUSE_GXP0.01A
BEAD
10.2A
19.6A
2.7A
5.4A
S10 (U1) VCCERAM
S10 (U1) S10_VCCPLLDIG_SDM
S10 (U1) S10_VCCFUSE_GXP
S10 (U1) VCCRT_GXP
S10 (U1) VCCRT_GXE
S10 (U1) VCCRTPLL_GXE
S10 (U1) S10_VCCPT, VCCBAT
S10 (U1) S10_VCCPLL_SDM, S10_VCCADC, S10_VCCA_PLL
S10 (U1) VCC, VCCP
5V0
M10_VCCINT
NC
P4
55
60
VCC, VCCP
2.45A EN63A01.8V@12A
U186
LC
S10_VCCH_GXP_LOW
VCCH_GXP_EN
S10_VCCCLK_GXP
EN63821.1V@8A
U184
S10_VCCH_GXE
1.1V @2.62A
VCCH_GXE_EN
U78
BEAD
S10_VCCCLK_GXE
2.5V@1A
VCCCLK_GXE _EN
0.17A
0.46A
0.87A
BEAD
0.8A
S10 (U1) VCCH_GXP
S10 (U1) VCCCLK_GXP
S10 (U1) VCCH_GXE
S10 (U1) VCCCLK_GXE
S10_VCCCLK_GXE_LOW 2.5V
EP53F8QI2,[email protected]
U76
VCCFUSEWR_SDM
EN6382QI1.8V@8A
U188
1V8
VCCFUSE_EN
VCCIO_1V8_EN
[email protected]@0.3A
U116
BEA
D
BEA
D
BEAD
BEAD
MAX10_VCC_1.2V
1.2V@1A
MAX10_VCCIO_2.5V
S10 (U1) VCCPFUSEWR_SDM
S10 (U1) S10_VCCIO_SDM, S10_VCCBAT, S10_VCCIO_2I, S10_VCCIO_2J, S10_VCCIO_2N, S10_VCCIO_3L, S10_VCCIO_3H
1.8V
U163 2V5_DDR4_CH00
EN63A0 1.2V@12A
(U159)
EV1320QI0.6V@2A
U164
0.6V@1A
U192
1.2V @8A
DDR 4_CH00_EN
U1652V5_DDR4_CH11
EN63A0 1.2V@12A
(U157)
EV1320QI0.6V@2A
U166
0.6V@1A
U193
1.2V @8A
2v5_DDR4_CH00
0V6_DDR4_VTT_CH00
0V6_DDR4_VREF_CH00
S10_1V2OUT_CH00
2v5_DDR4_CH11
0V6_DDR4_VTT_CH11
S10_1V2OUT_CH11
0V6_DDR4_VREF_CH11
2.9A
0.2A
0.08A
DDR 4_CH11_EN
0.36A
3.3V_ZQSFP1TPS2557 (U51)
TPS2557 (U52) BEAD
BEAD
3.3V_ZQSFP2
U203
QSFP1 (J16)
QSFP2 (J18)
MAX10_VCC_1.2V
MAX10_VCCA_2.5V
M10_1V2_VCCDPLL
MAX10_VCCA_ADC_2.5V
11.3A
6A3.2A
0.7A
8.3A
S10_G2_1.8V_FLT
M10_3.3V
Monitored Power Rails
VCC/VCCP
0.9V (U230)
3.3V (U101)
12V_AUX2
12V_PCIE_IN
VCCPT (U113)
U79
MAX10_VCCIO_1.8V
M10_3.3V
12V_PCIe_SLOT
3.3V_REG_INST
LT
C4
35
9U
93
IN
OUT
7.8A
12V_DDRT_DIMM01
12V_DDRT_DIMM00
J42
2.5V_DDR4_CH00_EN2.5V_DDR4_CH11_EN
0V6_DDR4_VREF_CH00_EN
0V6_DDR4_VREF_CH11_EN
17A
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
2 69Thursday, July 11, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
2 69Thursday, July 11, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
2 69Thursday, July 11, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power Sequence Diagram
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
3 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
3 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
3 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MAX10
I2C1Master
AUX1HSCU92
AUX2HSC
U217
40h 41h
PCIEHSCU96
42h
I2C1
EM21400.9VU230
EM21303.3V
U101
44h
EM21301.8VU113
FXMA2101U34
3.3V 1.8V
OE
S10DX
I2C1_1V8 Bank 2I
I2C2Master
Si5332AU7
6Ah
3.3V
3.3V
FXMA2101U86
3.3V
1.8V
Si5391AU9
74h
I2C2_1V8
M2428SEEPROM
U94
5Fh/0Bh
FPC202RHURQSFP PORT CTRL
U50
02h/1Eh
BMC_I2C2_DISEN
I2C3Master
3.3V
MAX65818Ch
Temp Sensor
U32
9Ah
FXMA2102 U8
3.3V 1.8V
BMC_I2C3_DIS OE
SDMVID
Enpirion dongle
MAX3378U3
3.3V 2.5VI2C_DDR4T_0_2V52.5V
DIMM0J73
PWRMGTFXMA2101
U841.8V3.3V
ISL68137U104
60h
VCC CoreVID
I2C_LVC3
MAX3378U2
Bank 2J
Bank 2I
Bank 2I
I2C_DDR4T_0_S101.8V2.5V
DIMM1J74
I2C2
ATX PWR IN PCIE 12V IN
UPI / PCIE Clocks E-Tile/ FPGA clocks
BMC_I2C2_DIS
BMC_I2C1_DIS
I2C Isolator
zQSFP1 J15
zQSFP2 J18
ZQSFP1_3V3
ZQSFP2_3V3
I2C3
I2CSlave
PCIE EDGE CONNJ9
PCIE_EDGE_SMB
1.8V
1.8V
1.8V
1.8V
1.8V
UPI0_PCIE
UPI1_PCIE
UPI2_PCIE
UPI0 I2CMAX3378U198,U199
UPI0 J55
UPI1J55
UPI2J55
3.3V 1.8V
I2C Level Shifter
I2C Level Shifter
I2C Level Shifter
I2C Level Shifter
AVS_I2C
VcoreAVS
3.3V
I2C Level Shifter
USB ConnCN1
USB PHYCY7C6801
U26
FX2_I2CI2C
ON-BOARD USB BLASTER II
3.3V
3.3V
31h 47h
PCA9534I/O EXPANDER
U232
27h (7 bit addr )
4Eh (8 bit addr)
9ZML1252EU117
D8
DDR4 clocks I/O expander for clock controls
HDRJ17
EM_I2C
R342/R343
I2C1
ZQSFP1_3V3
PAC19324Ch Power
MonitorU233
7Bh
Optional Path
I2C & JTAG DIAGRAM
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
4 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
4 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
4 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MAX 10
IO_3/CLK7
PCIe x16 Slot
Si5332A-GM2 (U7)
CLKIN2_P/N
XTAL_OUTXTAL_IN
CLKIN3_P/N
100M_PCIe_REFCLK
S10 DX (ND5+CR3+WHR 2912)
UPI/PCIe2 RX Connector (J41)B35/B36
WHR U11 UPI0
Crete3
REFCLK_GXER9A_CH0_P/N
Fabric
CLK_3L_1_P/N
REFCLK_GXER9A_CH1_P/N
REFCLK_GXER9A_CH3_P/NREFCLK_GXER9A_CH2_P/N
REFCLK_GXPL10B_CH0_P/NREFCLK_GXPL10B_CH2_P/N
WHR U21 UPI1REFCLK_GXPR11B_CH0_P/NREFCLK_GXPR11B_CH2_P/N
WHR U10 PCIeREFCLK_GXPL10A_CH0_P/NREFCLK_GXPL10B_CH2_P/N
OSC_CLK_1OUT0_P/NOUT1_P/N
OUT2_P/NOUT3_P/NOUT4_P/NOUT5_P/N
OUT6_P/NOUT7_P/N
CLK_3L_0_P/N
CLK_133M_DDR4_0_P/N
CLK_133M_DDR4_1_P/N
CLK_133M_DDR4T_0_P/N
CLK_133M_DDR4T_1_P/N
CLK_100M_FPGA_0_P/N
CLK_100M_FPGA_1_P/N
CLK_125M_LVC1_CONFIG
CLK_100M_UPI2_0_P/N
CLK_100M_UPI2_1_P/N
CLK_100M_UPI1_0_P/N
CLK_100M_UPI1_1_P/N
CLK_100M_PCIE_0_P/N
CLK_100M_PCIE_1_P/N
CLK_100M_PCIe_REFCLK_P/N
CLK_100M_UPI0_REFCLK_EP_P/N
UPI/PCIe0 TX Connector (J55)A36/A35
CLK_156.25M_QSFP0_P/NCLK_156.25M_QSFP1_P/N
CLK_50M_MAX10
WHR U22 UPI2REFCLK_GXPR11C_CH0_P/NREFCLK_GXPR11C_CH2_P/N
CLK_100M_UPI0_0_P/N
CLK_100M_UPI0_1_P/N
9ZML1252E2:12 CLK MUX
(U176)
DIF0DIF1DIF2DIF3DIF4DIF5DIF6DIF7DIF8DIF9
DIF10DIF11
DIF_INB
SELA_B#
OE[11:0]#
CLK_MUX_ SEL_4
DIF_INA
IDT9DML0451
2:4 CLK MUX
(U208)
DIF0
DIF_INB
SELA_B#
OE0#
CLK_MUX_ SEL_4
DIF_INA
OE1#OE2#OE3#
DIF1DIF2DIF3
UPI/PCIe1 TX Connector (J38)
UPI/PCIe2 TX Connector (A39)
50MHz XTAL (X3)
CLK_100M_9DML04_P/N
CLK_100M_TEST_P/N (Provides Bench Testing and SSC Testing)
XTAL48_IN/OUT48MHz
XTAL (Y5)
Si5391A (U9)
OUT0A_P/NOUT0_P/NOUT1_P/NOUT2_P/N
OUT3_P/NOUT4_P/NOUT5_P/NOUT6_P/N
OUT7_P/NOUT8_P/NOUT9_P/N
OUT9A_P/N
XTAL_OUT
XTAL_IN
CLK2_100M_PCIe_2J_P/N
CLK2_100M_FPGA_2_P/NCLK_2J_1_P/N
CLK_2J_0_P/N
IN0
CLK2_FPGA_50M50MHz XTAL (X2)
CLK_3J_1_P/NCLK_2L_1_P/N
CLK_3B_1_P/NCLK_2C_1_P/N
CLK_2N_1
CLK_125M_LVC1_MAX10OSCS (X4) IO_3/CLK6
A36/A35
A36/A35
CLK_100M_UPI0_REFCLK_RP_P/N
CLK_100M_UPI1_REFCLK_RP_P/N
CLK_100M_UPI2_REFCLK_RP_P/N
CLK_ MUX_SEL1[1 :0]
CLK_ MUX_SEL0[1 :0]
CLK_312.5M_QSFP0_P/N
CLK_312.5M_QSFP1_P/N
REFCLK_GXER9A_CH8_P/N
CLK_100M_SI5391_P/N
XTAL25_IN/OUT25MHz
XTAL (Y6)
CLK_100M_UPI0_REFCLK_EP_P/N
IDT9DML0451
2:4 CLK MUX
(U190)
DIF0
DIF_INB
SELA_B#
OE0#
CLK_MUX_SEL_3
DIF_INA
OE1#OE2#OE3#
DIF1DIF2DIF3
CLK_100M_9DML04_P/N
UPI/PCIe1 RX Connector (J40)B35/B36
CLK_100M_UPI0_REFCLK_EP_P/N
IDT9DML0451
2:4 CLK MUX
(U176)
DIF0
DIF_INB
SELA_B#
OE0#
CLK_MUX _SEL_3
DIF_INA
OE1#OE2#OE3#
DIF1DIF2DIF3
CLK_100M_9DML04_P/N
UPI/PCIe0 RX Connector (J65)
B35/B36
CLK_3H_1
CLK_2I_1
CLK_100M_FPGA_0_P/N
CLK2_100M_FPGA_0_P/N
Default programming selects CLKIN2 or CLKIN 3
Using 25MHz OSC requires reprogramming
CLK_312.5M_QSFP2_P/N
HIBWBYPMLOBW#
ZML1252 used in ByPass Mode
CLK_SSC[1:0]
Needs to be reprogrammed to support 100MHz
PCIe Edge Reserved (A32/A33)CLK_100M_PCIe_REFCLK_RP_P/N
IN1
Clock Diagram
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
5 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
5 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
5 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 DX Configuration
(Close)(Close)
MSEL2(Open)
MSEL1_LINE
01
x1
0
(Open)
1
JTAG
(Close)
JTAG
MSEL0
(Open) 0
Compatible with Micron MT25QU02GCBB3E12-1SIT
MSEL0_LINE
AVST x8CommentsAVST x8
(OPen)
For Active Serial Configuration
1
MSEL2_LINE
(Close)1
Config Mode
1
11
QSPI_AVST_SEL
(Open)(Close)(Open)
(Open)
(Open)01
(Close)0
MSEL1
0(Open)
Must be close to TCK pin AN22
S10_CONFIG
2Gbit Flash
2.7V - 3.6VAbsmax = 4V
2Gb Serial Flash
SW1 Setting
Install this resistor to disable U84for connection of PMBus to I2C2 bus
Install these two resistors toconnect the PMBus to I2C2 bus
1.8V
1.8V
MAX10_VCCIO_1.8V
1.8V
3.3V_REG_INST
1.8V
1.8V
1.8V
3.3V_REG_INST3.3V_REG_INST
3.3V_REG_INST
S10_1V8_TCK 23S10_1V8_TDI 23S10_1V8_TDO 23S10_1V8_TMS 23
AVST8_CLK 23AVST8_VALID 23AVST8_READY 23AVST8_DATA[0..7] 23
MSEL0 23MSEL1 23MSEL2 23
CLK_125M_LVC1_CONFIG 22
I2C_LVC3_SCL 58I2C_LVC3_SDA 58
QSPI_AVST_SEL23
FPGA_1V8_nCONFIG 23
FPGA_1V8_nSTATUS 23FPGA_1V8_INIT_DONE 23FPGA_1V8_CONF_DONE 23
QSPI_M10_DATA0 23QSPI_M10_DATA1 23QSPI_M10_DATA2 23QSPI_M10_DATA3 23
QSPI_M10_CLK23
QSPI_M10_CS_N23
QSPI_M10_RESETN23
I2C2_SCL 7,22,23,69
I2C2_SDA 7,22,23,69
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
6 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
6 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
6 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R52914.70K
C289 22pF, DNI0402
NP010V
OPEN
SW1
TDA04H0SB1
12345
678
R92.00K
R5410 1K
U66
MT25QL02GCBB8E12-0SIT
T-PBGA24
S#C2
CB2
RESET#/DNUA4
W#/DQ2C4
DQ0D3
DQ1D2
DQ3D4
VCCB4
VSSB3
DNU1A2
DNU2A3
DNU3A5
DNU4B1
DNU5B5
DNU6C1
DNU7C3
DNU8C5
DNU9D1
DNU10D5
DNU11E1
DNU12E2
DNU13E3
DNU14E4
DNU15E5
R5411 1K
R5369 0
SDM BANKS10_DX_ND5_F2912D_EXTERNAL
U1-1
SDM_IO14,AVSTX8_CLK,PWRMGT_SCL,NAND_ADQ7BD28
SDM_IO15,AVSTX8_DATA6,SDMMC_CFG_DATA6,NAND_ADQ4BE29
SDM_IO13,AVSTX8_DATA5,SDMMC_CFG_DATA5,NAND_CE_NBF29
SDM_IO5,INIT_DONE,AS_NCSO0,SDMMC_CFG_CCLK,NAND_WE_N,MSEL0,CONF_DONEBG28
SDM_IO10,AVSTX8_DATA7,SDMMC_CFG_DATA7,NAND_ADQ5BG29
SDM_IO11,AVSTX8_VALID,PWRMGT_SDA,NAND_ADQ6BH28
SDM_IO12,PWRMGT_PWM0,PWRMGT_SDA,NAND_WP_NBJ29
SDM_IO16,INIT_DONE,CONF_DONE,PWRMGT_SDABK27
DNU4BL27 DNU3BN27
DNU1BN31
DNU2BP30
SDM_IO6,AVSTX8_DATA4,AS_DATA3,SDMMC_CFG_DATA3,NAND_ADQ3BA27
SDM_IO1,AVSTX8_DATA2,AS_DATA1,SDMMC_CFG_DATA1,NAND_RE_NBB27
SDM_IO2,AVSTX8_DATA0,AS_CLK,SDMMC_CFG_DATA0,NAND_ADQ0BB28
SDM_IO0,INIT_DONE,PWRMGT_PWM0,PWRMGT_SCLBB29
SDM_IO9,AS_NCSO1,NAND_CLE,MSEL2BC26
NSTATUSBC27
SDM_IO8,AVST_READY,AS_NCSO3,SDMMC_CFG_DATA4,NAND_RBBC28
NCONFIGBD29
SDM_IO7,AS_NCSO2,NAND_ALE,MSEL1BE28
SDM_IO4,AVSTX8_DATA1,AS_DATA0,SDMMC_CFG_CMD,NAND_ADQ1BF30 SDM_IO3,AVSTX8_DATA3,AS_DATA2,SDMMC_CFG_DATA2,NAND_ADQ2BG30
OSC_CLK_1BJ28
TDIBK29
VSIGN_0BL29
TCKBL30
VSIGN_1BM28
VSIGP_0BM29
TMSBM30
VSIGP_1BN28
TDOBN30
RREF_SDMBP31
R310.0K04021%
R69610.0K
R532010.0K
R410.0K04021%
C8750.1uF0402
R67130, DNI
04025%
R1524.70K, DNI04025%
C8740.1uF0402
R5413 1K
R52934.70K
R67140, DNI
R1684.70K, DNI
04025%
R44710.0K0402
1%
R52944.70K
R110.0K
R660410.0K0402
1%
C8320.1uF0402
R67150, DNI
C8310.01uF
0402
R210.0K
U84
FXMA2102UMX
A02
A13 B0
7
B16
VCCA1
GND4
OE5
VCCB8
R1110.0K04021%
R52924.70K
S10_1V8_TDOS10_1V8_TMS
S10_1V8_TCKS10_1V8_TDI
FPGA_1V8_nCONFIGFPGA_1V8_nSTATUSCLK_125M_LVC1_CONFIG
FPGA_1V8_INIT_DONE PWRMGT_SCLAVST8_DATA2AVST8_DATA0AVST8_DATA3AVST8_DATA1
AVST8_DATA4
AVST8_CLKAVST8_READYAVST8_VALID
AVST8_DATA7AVST8_VALID
PWRMGT_SDAAVST8_DATA5AVST8_CLKAVST8_DATA6FPGA_1V8_CONF_DONE
PWRMGT_SCLPWRMGT_SDA
QSPI_AVST_SEL
MSEL0MSEL1MSEL2
MSEL0MSEL1MSEL2
FPGA_1V8_nCONFIGFPGA_1V8_nSTATUSFPGA_1V8_INIT_DONEFPGA_1V8_CONF_DONE
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 DX Bank 2A, B, C, I, F
1.2V
1.2V 1.2V
DDR4 DIMM CH1 IF
I2C 7-bit Addr =0x50 - 0x5FI2C 8-bit Addr =0xA0 - 0xBF
I2C 3V3
I2C 1V8
CLOCK
DQSn/P for x4
DQSn/P for x4
DQSn/P for x4
DQSn/P for x4
DQSn/P for x4
DQSn/P for x4
DQSn/P for x4 DQSn/P for x4
When BMC_I2C2_DISABLE = 1, MAX10BMC is blocked from accessingEEPROM and QSFP Port Controllerover I2C2 bus. This pin should beassigned as open drain output.
VGS(th) = 0.6V / 1V /1.5V
Please J95 and J96 side-by-side
on the solder side of board
128-Kbit Serail EEPROM
DNI
DNI
1.8V
1.8V
1.8V
1.8V
M10_3.3V1.8V
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST1.8V
3.3V_REG_INST
DDR4_DIMM_CH1_C243
DDR4_DIMM_CH1_DQ[71:0]43
DDR4_DIMM_CH1_A[17:0]43
DDR4_DIMM_CH1_DQS_P[17:0]43
DDR4_DIMM_CH1_CKE[1:0]43
DDR4_DIMM_CH1_CK_P[1:0]43
DDR4_DIMM_CH1_DQS_N[17:0]43
DDR4_DIMM_CH1_ODT[1:0]43
DDR4_DIMM_CH1_RESET_N43
DDR4_DIMM_CH1_CK_N[1:0]43
DDR4_DIMM_CH1_CS_N[3:0]43
DDR4_DIMM_CH1_BG[1:0]43
DDR4_DIMM_CH1_BA[1:0]43
DDR4_DIMM_CH1_ACT_N43
DDR4_DIMM_CH1_PAR43
DDR4_DIMM_CH1_ALERT_N43
CLK_133M_DIMM_0_N 22CLK_133M_DIMM_0_P 22
I2C1_1V8_SCL 68I2C1_1V8_SDA 68
ZQSFP_1V8_PORT_INT_N 28ZQSFP_1V8_PORT_EN 28
I2C2_SCL 6,22,23,69I2C2_SDA 6,22,23,69
I2C3_SCL 23,33I2C3_SDA 23,33
I2C2_1V8_SCL 28I2C2_1V8_SDA 28
BMC_I2C1_DISABLE 68
CLK2_100M_FPGA_2I_N 22CLK2_100M_FPGA_2I_P 22
M10_GPIO0_1V8 68
M10_CLK_1V8 68M10_SSN_1V8 68
M10_GPIO1_1V8 68
M10_DATA1_1V8 68M10_DATA0_1V8 68
M10_DATA2_1V8 68M10_DATA3_1V8 68
BMC_I2C2_DISABLE8
BMC_I2C3_DISABLE8
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
7 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
7 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
7 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R54204.70K
R53044.70K
R47 2401%R0201
R400 0
J96
TSM-103-01-L-SV
11
22
33
R307 0
U86
FXMA2102UMX
A02
A13 B0
7
B16
VCCA1
GND4
OE5
VCCB8
R54194.70K
R403 0
IO BANK 2BS10_DX_ND5_F2912D_EXTERNAL
U1-3
IO,PLL_2B_CLKOUT1P,PLL_2B_CLKOUT1,PLL_2B_FB1,LVDS2B_10P,DQS41BG38
IO,PLL_2B_CLKOUT0P,PLL_2B_CLKOUT0,PLL_2B_FB0,LVDS2B_15P,DQ42BL41
IO,LVDS2B_1P,DQ40AW34
IO,LVDS2B_3N,DQ40AW35
IO,LVDS2B_3P,DQ40AW36
IO,LVDS2B_1N,DQ40AY34
IO,LVDS2B_5N,DQ40AY36
IO,LVDS2B_2P,DQ40BA35
IO,LVDS2B_5P,DQ40BA36
IO,LVDS2B_2N,DQ40BB35
IO,LVDS2B_6N,DQ40BC35
IO,LVDS2B_6P,DQ40BC36
IO,LVDS2B_4P,DQS40BD36 IO,LVDS2B_4N,DQSN40BE36
IO,LVDS2B_8N,DQ41BE37
IO,CLK_2B_1N,LVDS2B_12N,DQ41BF36
IO,LVDS2B_8P,DQ41BF37
IO,RZQ_2B,LVDS2B_11P,DQ41BF39 IO,LVDS2B_11N,DQ41BF40
IO,CLK_2B_1P,LVDS2B_12P,DQ41BG37
IO,LVDS2B_9P,DQ41BG39 IO,LVDS2B_9N,DQ41BG40
IO,LVDS2B_7P,DQ41BG42
IO,PLL_2B_CLKOUT1N,LVDS2B_10N,DQSN41BH38
IO,LVDS2B_16P,DQS42BH40
IO,CLK_2B_0P,LVDS2B_13P,DQ42BH41
IO,LVDS2B_7N,DQ41BH42
IO,LVDS2B_18N,DQ42BJ39
IO,LVDS2B_16N,DQSN42BJ40
IO,CLK_2B_0N,LVDS2B_13N,DQ42BJ41
IO,LVDS2B_18P,DQ42BK39
IO,PLL_2B_CLKOUT0N,LVDS2B_15N,DQ42BK41
IO,LVDS2B_17P,DQ42BK42
IO,LVDS2B_14P,DQ42BL39
IO,LVDS2B_20N,DQ43BL40
IO,LVDS2B_17N,DQ42BL42
IO,LVDS2B_14N,DQ42BM39
IO,LVDS2B_20P,DQ43BM40
IO,LVDS2B_19N,DQ43BM42
IO,LVDS2B_23P,DQ43BM43
IO,LVDS2B_24N,DQ43BN40
IO,LVDS2B_22N,DQSN43BN41
IO,LVDS2B_19P,DQ43BN42
IO,LVDS2B_23N,DQ43BN43
IO,LVDS2B_24P,DQ43BP40
IO,LVDS2B_22P,DQS43BP41
IO,LVDS2B_21N,DQ43BP43
IO,LVDS2B_21P,DQ43BP44
R301 0
R52984.70K
R308 0
R383 0 R6476 100
1
2
3Q65SI2302CDS-T1-GE3
SOT23
R290 0
C3110
0.1uF
0402
R49810.0K04021%
R404 0
R6350 100
IO BANK 2CS10_DX_ND5_F2912D_EXTERNAL
U1-4
IO,PLL_2C_CLKOUT1P,PLL_2C_CLKOUT1,PLL_2C_FB1,LVDS2C_10P,DQS37BF34
IO,PLL_2C_CLKOUT0P,PLL_2C_CLKOUT0,PLL_2C_FB0,LVDS2C_15P,DQ38BJ33
IO,LVDS2C_3P,DQ36BA31IO,LVDS2C_3N,DQ36BA32
IO,LVDS2C_5N,DQ36BA34
IO,LVDS2C_1P,DQ36BB32
IO,LVDS2C_4P,DQS36BB33
IO,LVDS2C_5P,DQ36BB34
IO,LVDS2C_1N,DQ36BC32
IO,LVDS2C_4N,DQSN36BC33
IO,LVDS2C_2N,DQ36BD33
IO,LVDS2C_6P,DQ36BD34
IO,LVDS2C_2P,DQ36BE33
IO,LVDS2C_6N,DQ36BE34
IO,RZQ_2C,LVDS2C_11P,DQ37BF35
IO,LVDS2C_7N,DQ37BG33
IO,PLL_2C_CLKOUT1N,LVDS2C_10N,DQSN37BG34
IO,LVDS2C_11N,DQ37BG35
IO,LVDS2C_7P,DQ37BH33
IO,LVDS2C_8P,DQ37BH35IO,LVDS2C_8N,DQ37BH36
IO,CLK_2C_1P,LVDS2C_12P,DQ37BH37
IO,LVDS2C_9P,DQ37BJ34IO,LVDS2C_9N,DQ37BJ35
IO,CLK_2C_1N,LVDS2C_12N,DQ37BJ36
IO,LVDS2C_18N,DQ38BJ38
IO,PLL_2C_CLKOUT0N,LVDS2C_15N,DQ38BK33
IO,LVDS2C_17N,DQ38BK34IO,LVDS2C_16P,DQS38BK36
IO,LVDS2C_14P,DQ38BK37
IO,LVDS2C_18P,DQ38BK38
IO,CLK_2C_0P,LVDS2C_13P,DQ38BL34
IO,LVDS2C_17P,DQ38BL35
IO,LVDS2C_16N,DQSN38BL36
IO,LVDS2C_14N,DQ38BL37
IO,CLK_2C_0N,LVDS2C_13N,DQ38BM34
IO,LVDS2C_19N,DQ39BM35
IO,LVDS2C_20N,DQ39BM37
IO,LVDS2C_23N,DQ39BM38
IO,LVDS2C_19P,DQ39BN35
IO,LVDS2C_22N,DQSN39BN36
IO,LVDS2C_20P,DQ39BN37
IO,LVDS2C_23P,DQ39BN38
IO,LVDS2C_21N,DQ39BP34
IO,LVDS2C_21P,DQ39BP35
IO,LVDS2C_22P,DQS39BP36
IO,LVDS2C_24N,DQ39BP38
IO,LVDS2C_24P,DQ39BP39
R356 0
R50010.0K0402
1%
R6602 1001%0402
IO BANK 2AS10_DX_ND5_F2912D_EXTERNAL
U1-2
IO,PLL_2A_CLKOUT0P,PLL_2A_CLKOUT0,PLL_2A_FB0,LVDS2A_15P,DQ46BH43
IO,PLL_2A_CLKOUT1P,PLL_2A_CLKOUT1,PLL_2A_FB1,LVDS2A_10P,DQS45BH45
IO,LVDS2A_20P,DQ47BE42 IO,LVDS2A_20N,DQ47BE43
IO,LVDS2A_17P,DQ46BF41 IO,LVDS2A_17N,DQ46BF42
IO,LVDS2A_22N,DQSN47BF44
IO,CLK_2A_1P,LVDS2A_12P,DQ45BF45
IO,PLL_2A_CLKOUT0N,LVDS2A_15N,DQ46BG43
IO,LVDS2A_22P,DQS47BG44
IO,CLK_2A_1N,LVDS2A_12N,DQ45BG45
IO,CLK_2A_0P,LVDS2A_13P,DQ46BJ43
IO,LVDS2A_24N,DQ47BJ44
IO,PLL_2A_CLKOUT1N,LVDS2A_10N,DQSN45BJ45
IO,CLK_2A_0N,LVDS2A_13N,DQ46BK43
IO,LVDS2A_24P,DQ47BK44
IO,LVDS2A_1N,DQ44BK54
IO,LVDS2A_21N,DQ47BL44
IO,RZQ_2A,LVDS2A_11P,DQ45BL45
IO,LVDS2A_6N,DQ44BL46
IO,LVDS2A_6P,DQ44BL47
IO,LVDS2A_8N,DQ45BL49
IO,LVDS2A_4N,DQSN44BL50
IO,LVDS2A_2P,DQ44BL51 IO,LVDS2A_2N,DQ44BL52 IO,LVDS2A_1P,DQ44BL54
IO,LVDS2A_21P,DQ47BM44
IO,LVDS2A_11N,DQ45BM45
IO,LVDS2A_16P,DQS46BM47
IO,LVDS2A_9N,DQ45BM48 IO,LVDS2A_8P,DQ45BM49
IO,LVDS2A_4P,DQS44BM50
IO,LVDS2A_5P,DQ44BM52
IO,LVDS2A_3N,DQ44BM53
IO,LVDS2A_23N,DQ47BN45
IO,LVDS2A_19N,DQ47BN46
IO,LVDS2A_16N,DQSN46BN47
IO,LVDS2A_9P,DQ45BN48
IO,LVDS2A_14P,DQ46BN50
IO,LVDS2A_7N,DQ45BN51
IO,LVDS2A_5N,DQ44BN52
IO,LVDS2A_3P,DQ44BN53
IO,LVDS2A_23P,DQ47BP45
IO,LVDS2A_19P,DQ47BP46
IO,LVDS2A_18N,DQ46BP48
IO,LVDS2A_18P,DQ46BP49
IO,LVDS2A_14N,DQ46BP50
IO,LVDS2A_7P,DQ45BP51
J95
TSM-103-01-L-SV
11
22
33
R405 0
R53024.70K
R6436
10.0K
R382 0
R357 0
1
2
3Q64SI2302CDS-T1-GE3
SOT23
R52510.0K,DNI04021%
C11930.1uF
040225VX7R
R396 0
R6603
10.0K
0402
1%
R6592 1001%0402
U94
M24128-BRMN6TPSO8
E01
E12
E23
WC_N7
SDA5 SCL6
VCC8
GND4
C8500.01uF
0402
R49910.0K04021%
C8510.1uF0402
R397 0
IO BANK 2F
IO BANK 2I
S10_DX_ND5_F2912D_EXTERNAL
U1-5
IO,LVDS2F_17P,DQ34AY29IO,LVDS2F_17N,DQ34BA29
IO,PLL_2F_CLKOUT0P,PLL_2F_CLKOUT0,PLL_2F_FB0,LVDS2F_15P,DQ34BB30
IO,CLK_2F_0P,LVDS2F_13P,DQ34BC30IO,CLK_2F_0N,LVDS2F_13N,DQ34BC31
IO,LVDS2F_14P,DQ34BD30IO,LVDS2F_14N,DQ34BD31
IO,LVDS2F_18P,DQ34BE31IO,LVDS2F_18N,DQ34BF31
IO,LVDS2F_16N,DQSN34BF32
IO,LVDS2F_16P,DQS34BG32
IO,LVDS2F_23N,DQ35BH30
IO,LVDS2F_19P,DQ35BH31IO,LVDS2F_19N,DQ35BH32
IO,LVDS2F_23P,DQ35BJ30
IO,LVDS2F_22N,DQSN35BJ31
IO,LVDS2F_22P,DQS35BK31
IO,LVDS2F_20N,DQ35BK32
IO,LVDS2F_20P,DQ35BL31
IO,LVDS2F_21N,DQ35BL32
IO,LVDS2F_21P,DQ35BM33
IO,LVDS2F_24N,DQ35BN33
IO,LVDS2F_24P,DQ35BP33
IO,PLL_2F_CLKOUT0N,LVDS2F_15N,DQ34BA30
IO,LVDS2I_1N,DQ20E32
IO,LVDS2I_1P,DQ20E33
IO,LVDS2I_2N,DQ20A32
IO,LVDS2I_2P,DQ20B32
IO,LVDS2I_3N,DQ20F32
IO,LVDS2I_3P,DQ20G33
IO,LVDS2I_4N,DQSN20C33
IO,LVDS2I_4P,DQS20D33
IO,LVDS2I_5N,DQ20H32
IO,LVDS2I_5P,DQ20G32
IO,LVDS2I_6N,DQ20C32
IO,LVDS2I_6P,DQ20B33
IO,LVDS2I_7N,DQ21K32
IO,LVDS2I_7P,DQ21K33
IO,LVDS2I_8N,DQ21L31
IO,LVDS2I_8P,DQ21K31
IO,LVDS2I_9N,DQ21N32
IO,LVDS2I_9P,DQ21N31
IO,PLL_2I_CLKOUT1N,LVDS2I_10N,DQSN21L32
IO,PLL_2I_CLKOUT1P,PLL_2I_CLKOUT1,PLL_2I_FB1,LVDS2I_10P,DQS21M32
IO,LVDS2I_11N,DQ21P31
IO,RZQ_2I,LVDS2I_11P,DQ21R31
IO,CLK_2I_1P,LVDS2I_12P,DQ21H33
IO,CLK_2I_1N,LVDS2I_12N,DQ21J33
R602210.0K,DNI0402
1%
R52410.0K,DNI0402
1%
R6593
10.0K
0402
1%
U8
FXMA2102UMX
A02
A13 B0
7
B16
VCCA1
GND4
OE5
VCCB8
R398 0
R6023 10.0K0402 1%
R53834.70K
R532110.0K
R53844.70K
C31090.01uF0402
R399 0
R53034.70K
DDR4_DIMM_CH1_A0DDR4_DIMM_CH1_A1DDR4_DIMM_CH1_A2DDR4_DIMM_CH1_A3DDR4_DIMM_CH1_A4DDR4_DIMM_CH1_A5DDR4_DIMM_CH1_A6DDR4_DIMM_CH1_A7DDR4_DIMM_CH1_A8DDR4_DIMM_CH1_A9DDR4_DIMM_CH1_A10DDR4_DIMM_CH1_A11
DDR4_DIMM_CH1_A12DDR4_DIMM_CH1_A13DDR4_DIMM_CH1_A14DDR4_DIMM_CH1_A15DDR4_DIMM_CH1_A16DDR4_DIMM_CH1_A17
DDR4_DIMM_CH1_CK_N0DDR4_DIMM_CH1_CK_P0
DDR4_DIMM_CH1_CK_N1DDR4_DIMM_CH1_CK_P1
DDR4_DIMM_CH1_CKE1DDR4_DIMM_CH1_CKE0
DDR4_DIMM_CH1_RESET_N
DDR4_DIMM_CH1_ACT_N
DDR4_DIMM_CH1_ODT1DDR4_DIMM_CH1_ODT0
DDR4_DIMM_CH1_BG1
DDR4_DIMM_CH1_BG0
DDR4_DIMM_CH1_BA0DDR4_DIMM_CH1_BA1
DDR4_DIMM_CH1_CS_N0
DDR4_DIMM_CH1_CS_N1DDR4_DIMM_CH1_PAR
RZQ_2C
DDR4_DIMM_CH1_DQS_N2DDR4_DIMM_CH1_DQS_P2
DDR4_DIMM_CH1_DQS_N3DDR4_DIMM_CH1_DQS_P3
DDR4_DIMM_CH1_DQS_P5DDR4_DIMM_CH1_DQS_N5
DDR4_DIMM_CH1_DQS_P1DDR4_DIMM_CH1_DQS_N1
DDR4_DIMM_CH1_DQ43DDR4_DIMM_CH1_DQ42
DDR4_DIMM_CH1_DQ14
DDR4_DIMM_CH1_DQ13
DDR4_DIMM_CH1_DQ11
DDR4_DIMM_CH1_DQ61
DDR4_DIMM_CH1_DQ56
DDR4_DIMM_CH1_DQ53DDR4_DIMM_CH1_DQ52
DDR4_DIMM_CH1_DQ48
DDR4_DIMM_CH1_DQ4
DDR4_DIMM_CH1_DQ37
DDR4_DIMM_CH1_DQ39DDR4_DIMM_CH1_DQ38
DDR4_DIMM_CH1_DQ34
DDR4_DIMM_CH1_DQS_N7DDR4_DIMM_CH1_DQS_P7
DDR4_DIMM_CH1_DQS_N6DDR4_DIMM_CH1_DQS_P6
DDR4_DIMM_CH1_DQS_P0DDR4_DIMM_CH1_DQS_N0
DDR4_DIMM_CH1_DQS_P4DDR4_DIMM_CH1_DQS_N4
DDR4_DIMM_CH1_DQ63
DDR4_DIMM_CH1_DQ69
DDR4_DIMM_CH1_DQ70
DDR4_DIMM_CH1_DQS_P8DDR4_DIMM_CH1_DQS_N8
DDR4_DIMM_CH1_CS_N2DDR4_DIMM_CH1_CS_N3DDR4_DIMM_CH1_C2
DDR4_DIMM_CH1_ALERT_N
TEST1TEST2TEST3TEST4
CLK_133M_DIMM_0_PCLK_133M_DIMM_0_N
I2C2_1V8_SCLI2C2_1V8_SDA
I2C2_SDAI2C2_SCL
I2C2_1V8_SDAI2C2_1V8_SCL
I2C3_SCLI2C3_SDA
I2C1_1V8_SCLI2C1_1V8_SDA
I2C3_1V8_SDAI2C3_1V8_SCL
I2C3_OEI2C3_OE
I2C3_SDAI2C3_SCL
ZQSFP_1V8_PORT_INT_NZQSFP_1V8_PORT_EN
BMC_I2C1_DISABLE
I2C2_SDAI2C2_SCL
I2C2_1V8_SDAI2C2_1V8_SCL
BMC_I2C1_DISABLE
ZQSFP_1V8_PORT_ENZQSFP_1V8_PORT_INT_N
CLK2_100M_FPGA_2I_NCLK2_100M_FPGA_2I_P
DDR4_DIMM_CH1_DQ9
DDR4_DIMM_CH1_DQS_N10DDR4_DIMM_CH1_DQS_P10
DDR4_DIMM_CH1_DQS_N11DDR4_DIMM_CH1_DQS_P11
DDR4_DIMM_CH1_DQS_P12DDR4_DIMM_CH1_DQS_N12
DDR4_DIMM_CH1_DQ67
DDR4_DIMM_CH1_DQS_P17DDR4_DIMM_CH1_DQS_N17
DDR4_DIMM_CH1_DQ32DDR4_DIMM_CH1_DQ33
DDR4_DIMM_CH1_DQS_N13DDR4_DIMM_CH1_DQS_P13
DDR4_DIMM_CH1_DQS_N9DDR4_DIMM_CH1_DQS_P9
DDR4_DIMM_CH1_DQ41
DDR4_DIMM_CH1_DQS_N14DDR4_DIMM_CH1_DQS_P14
DDR4_DIMM_CH1_DQ50
DDR4_DIMM_CH1_DQS_P15DDR4_DIMM_CH1_DQS_N15
DDR4_DIMM_CH1_DQ59
DDR4_DIMM_CH1_DQS_N16DDR4_DIMM_CH1_DQS_P16
DDR4_DIMM_CH1_DQ22DDR4_DIMM_CH1_DQ20
DDR4_DIMM_CH1_DQ23DDR4_DIMM_CH1_DQ21
DDR4_DIMM_CH1_DQ18DDR4_DIMM_CH1_DQ19DDR4_DIMM_CH1_DQ16DDR4_DIMM_CH1_DQ17DDR4_DIMM_CH1_DQ29DDR4_DIMM_CH1_DQ28
DDR4_DIMM_CH1_DQ30DDR4_DIMM_CH1_DQ31
DDR4_DIMM_CH1_DQ25DDR4_DIMM_CH1_DQ27DDR4_DIMM_CH1_DQ24DDR4_DIMM_CH1_DQ26DDR4_DIMM_CH1_DQ44DDR4_DIMM_CH1_DQ45
DDR4_DIMM_CH1_DQ47DDR4_DIMM_CH1_DQ46
DDR4_DIMM_CH1_DQ40
DDR4_DIMM_CH1_DQ8
DDR4_DIMM_CH1_DQ10
DDR4_DIMM_CH1_DQ15
DDR4_DIMM_CH1_DQ12
DDR4_DIMM_CH1_DQ58
DDR4_DIMM_CH1_DQ62
DDR4_DIMM_CH1_DQ60
DDR4_DIMM_CH1_DQ57
DDR4_DIMM_CH1_DQ55DDR4_DIMM_CH1_DQ54
DDR4_DIMM_CH1_DQ51DDR4_DIMM_CH1_DQ49
DDR4_DIMM_CH1_DQ6
DDR4_DIMM_CH1_DQ3DDR4_DIMM_CH1_DQ2
DDR4_DIMM_CH1_DQ0DDR4_DIMM_CH1_DQ1
DDR4_DIMM_CH1_DQ5
DDR4_DIMM_CH1_DQ7
DDR4_DIMM_CH1_DQ36
DDR4_DIMM_CH1_DQ35
DDR4_DIMM_CH1_DQ64
DDR4_DIMM_CH1_DQ71
DDR4_DIMM_CH1_DQ66
DDR4_DIMM_CH1_DQ68
DDR4_DIMM_CH1_DQ65
I2C1_1V8_SDAI2C1_1V8_SCLI2C2_1V8_SDAI2C2_1V8_SCLM10_DATA0_1V8M10_DATA1_1V8M10_DATA2_1V8M10_DATA3_1V8M10_CLK_1V8M10_SSN_1V8M10_GPIO0_1V8M10_GPIO1_1V8
I2C3_1V8_SCLI2C3_1V8_SDA
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LED INTERFACE
DDRT DIMM
DDR COMP
S10 DX Bank 2J
CLOCK
1.8V
USER_LED_G[3:0] 31
DDR4_DIMM_CH0_EVENT_N 42DDR4_DIMM_CH0_SAVE_N 42
I2C_DDR4T_0_S10_SDA 42I2C_DDR4T_0_S10_SCL 42
DDR4_CH0_TEN_1V8 36DDR4_CH1_TEN_1V8 40
DDR4_DIMM_CH1_EVENT_N 43DDR4_DIMM_CH1_SAVE_N 43
CLK2_100M_FPGA_2J_0_P 22CLK2_100M_FPGA_2J_0_N 22
PCIE_LVC1V8_PRSNT2n_x16 68PCIE_LVC1V8_PRSNT2n_x8 68PCIE_LVC1V8_PRSNT2n_x4 68PCIE_LVC1V8_PRSNT2n_x1 68
S10_PCIE_EDGE_WAKEn 68S10_PCIE_CLKREQ_N 68
S10_LT_DATA0 68S10_LT_DATA1 68
UPI0_LSIO_RX1_PCIE_1V8 69UPI0_LSIO_RX2_PCIE_1V8 69UPI0_LSIO_RX5_PCIE_1V8 69UPI0_LSIO_RX6_PCIE_1V8 69
UPI1_LSIO_RX1_PCIE_1V8 69UPI1_LSIO_RX2_PCIE_1V8 69UPI1_LSIO_RX5_PCIE_1V8 69UPI1_LSIO_RX6_PCIE_1V8 69
UPI2_LSIO_RX1_PCIE_1V8 69UPI2_LSIO_RX2_PCIE_1V8 69UPI2_LSIO_RX5_PCIE_1V8 69UPI2_LSIO_RX6_PCIE_1V8 69
BMC_I2C3_DISABLE 7
BMC_I2C2_DISABLE 7
CLK2_100M_FPGA_2J_1_N 22CLK2_100M_FPGA_2J_1_P 22
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
8 69Friday, May 31, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
8 69Friday, May 31, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
8 69Friday, May 31, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
IO BANK 2JS10_DX_ND5_F2912D_EXTERNAL
U1-6
IO,PLL_2J_CLKOUT1P,PLL_2J_CLKOUT1,PLL_2J_FB1,LVDS2J_10P,DQS17D35
IO,CLK_2J_1P,LVDS2J_12P,DQ17E36IO,CLK_2J_1N,LVDS2J_12N,DQ17F36IO,RZQ_2J,LVDS2J_11P,DQ17G34
IO,PLL_2J_CLKOUT0N,LVDS2J_15N,DQ18J34
IO,PLL_2J_CLKOUT0P,PLL_2J_CLKOUT0,PLL_2J_FB0,LVDS2J_15P,DQ18K34
IO,CLK_2J_0P,LVDS2J_13P,DQ18K36IO,CLK_2J_0N,LVDS2J_13N,DQ18L36
IO,LVDS2J_23P,DQ19N33
IO,LVDS2J_5P,DQ16A34
IO,LVDS2J_3N,DQ16A35
IO,LVDS2J_1P,DQ16A36IO,LVDS2J_1N,DQ16A37
IO,LVDS2J_5N,DQ16B34
IO,LVDS2J_3P,DQ16B35
IO,LVDS2J_6P,DQ16B37
IO,LVDS2J_2P,DQ16B38
IO,PLL_2J_CLKOUT1N,LVDS2J_10N,DQSN17C35
IO,LVDS2J_4N,DQSN16C36
IO,LVDS2J_6N,DQ16C37
IO,LVDS2J_2N,DQ16C38
IO,LVDS2J_7N,DQ17D34
IO,LVDS2J_4P,DQS16D36
IO,LVDS2J_7P,DQ17E34
IO,LVDS2J_8P,DQ17E37
IO,LVDS2J_11N,DQ17F34
IO,LVDS2J_9N,DQ17F35
IO,LVDS2J_8N,DQ17F37
IO,LVDS2J_9P,DQ17G35
IO,LVDS2J_14P,DQ18G37
IO,LVDS2J_16N,DQSN18H35
IO,LVDS2J_18P,DQ18H36
IO,LVDS2J_14N,DQ18H37
IO,LVDS2J_16P,DQS18J35
IO,LVDS2J_18N,DQ18J36
IO,LVDS2J_21N,DQ19L34
IO,LVDS2J_17N,DQ18L35
IO,LVDS2J_23N,DQ19M33
IO,LVDS2J_21P,DQ19M34
IO,LVDS2J_17P,DQ18M35
IO,LVDS2J_24P,DQ19N35
IO,LVDS2J_20P,DQ19N36
IO,LVDS2J_19N,DQ19P33
IO,LVDS2J_22P,DQS19P34
IO,LVDS2J_24N,DQ19P35
IO,LVDS2J_20N,DQ19P36IO,LVDS2J_19P,DQ19R33
IO,LVDS2J_22N,DQSN19R34
R5723 10.0K
R5729 10.0K
R5737 10.0K
R6394 100
R5730 10.0K
R5738 10.0K
R5722 10.0K
R6351 DNI
R6461 100
USER_LED_G0
USER_LED_G1
USER_LED_G3
USER_LED_G2
I2C_DDR4T_0_S10_SDAI2C_DDR4T_0_S10_SCL
DDR4_DIMM_CH0_EVENT_NDDR4_DIMM_CH0_SAVE_N
I2C_DDR4T_0_S10_SDAI2C_DDR4T_0_S10_SCL
DDR4_DIMM_CH0_EVENT_NDDR4_DIMM_CH0_SAVE_N
DDR4_CH0_TEN_1V8DDR4_CH1_TEN_1V8
CLK2_100M_FPGA_2J_1_NCLK2_100M_FPGA_2J_1_P
DDR4_DIMM_CH1_SAVE_NDDR4_DIMM_CH1_EVENT_N
DDR4_DIMM_CH1_EVENT_NDDR4_DIMM_CH1_SAVE_N
RZQ_2J
CLK2_100M_FPGA_2J_0_NCLK2_100M_FPGA_2J_0_P
PCIE_LVC1V8_PRSNT2n_x1
PCIE_LVC1V8_PRSNT2n_x16PCIE_LVC1V8_PRSNT2n_x8PCIE_LVC1V8_PRSNT2n_x4
S10_PCIE_EDGE_WAKEnS10_PCIE_CLKREQ_NS10_LT_DATA0S10_LT_DATA1
UPI1_LSIO_RX1_PCIE_1V8UPI1_LSIO_RX2_PCIE_1V8UPI1_LSIO_RX5_PCIE_1V8UPI1_LSIO_RX6_PCIE_1V8
UPI2_LSIO_RX1_PCIE_1V8UPI2_LSIO_RX2_PCIE_1V8UPI2_LSIO_RX5_PCIE_1V8UPI2_LSIO_RX6_PCIE_1V8
UPI0_LSIO_RX1_PCIE_1V8UPI0_LSIO_RX2_PCIE_1V8UPI0_LSIO_RX5_PCIE_1V8UPI0_LSIO_RX6_PCIE_1V8
BMC_I2C3_DISABLEBMC_I2C2_DISABLE
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 DX Bank 2K, L, M, N
PUSH BUTTON INTERFACE
1.2V1.2V
1.2V
1.8V
1.8V
DDR4_CH1_DQ[71:0]38,39,40
DDR4_CH1_DM639
DDR4_CH1_DM439
DDR4_CH1_DM739
DDR4_CH1_DM840
DDR4_CH1_DQS4n39DDR4_CH1_DQS4p39
DDR4_CH1_DQS7n39DDR4_CH1_DQS7p39
DDR4_CH1_DQS8n40DDR4_CH1_DQS8p40
DDR4_CH1_DQS6n39DDR4_CH1_DQS6p39
CPU_RESETn 23,31
DDR4_CH1_DM539
DDR4_CH1_DQS5p39DDR4_CH1_DQS5n39
DDR4_CH1_DM338
DDR4_CH1_DQS3p38DDR4_CH1_DQS3n38
DDR4_CH1_DM238DDR4_CH1_DQS2n38DDR4_CH1_DQS2p38
DDR4_CH1_DQS1p38DDR4_CH1_DQS1n38
DDR4_CH1_DM138
DDR4_CH1_DQS0p38DDR4_CH1_DQS0n38
DDR4_CH1_DM038
DDR4_CH1_ALERTn38,39,40
DDR4_CH1_BG138,39,40,41DDR4_CH1_BG038,39,40,41
DDR4_CH1_BA038,39,40,41DDR4_CH1_BA138,39,40,41
DDR4_CH1_A1538,39,40,41DDR4_CH1_A1638,39,40,41
DDR4_CH1_A1238,39,40,41DDR4_CH1_A1338,39,40,41DDR4_CH1_A1438,39,40,41
DDR4_CH1_A1038,39,40,41DDR4_CH1_A1138,39,40,41
DDR4_CH1_A738,39,40,41DDR4_CH1_A838,39,40,41DDR4_CH1_A938,39,40,41
DDR4_CH1_A438,39,40,41DDR4_CH1_A538,39,40,41DDR4_CH1_A638,39,40,41
DDR4_CH1_A238,39,40,41DDR4_CH1_A338,39,40,41
DDR4_CH1_PAR38,39,40,41DDR4_CH1_A038,39,40,41DDR4_CH1_A138,39,40,41
DDR4_CH1_CKp38,39,40,41DDR4_CH1_CKn38,39,40,41
DDR4_CH1_ACTn38,39,40,41DDR4_CH1_ODT38,39,40,41
DDR4_CH1_CKE38,39,40,41
DDR4_CH1_RESETn38,39,40,41DDR4_CH1_CSn38,39,40,41
CLK_133M_DDR4_1_N22CLK_133M_DDR4_1_P22
UPI1_LSIO_RX[6:1] 26UPI1_LSIO_TX[6:1] 26
UPI2_LSIO_TX[6:1] 27UPI2_LSIO_RX[6:1] 27
USER_PB0 31
USB_FPGA_CLK 23
TSENSE_ALERTn_1V8 68
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
9 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
9 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
9 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R294 22.0
IO BANK 2NS10_DX_ND5_F2912D_EXTERNAL
U1-10
IO,CLK_2N_0N,LVDS2N_13N,DQ2E39
IO,CLK_2N_0P,LVDS2N_13P,DQ2D39
IO,CLK_2N_1N,LVDS2N_12N,DQ1H38
IO,CLK_2N_1P,LVDS2N_12P,DQ1G38
IO,LVDS2N_11N,DQ1J40
IO,LVDS2N_14N,DQ2D38
IO,LVDS2N_14P,DQ2E38
IO,LVDS2N_16N,DQSN2D40
IO,LVDS2N_16P,DQS2C40
IO,LVDS2N_17N,DQ2E41
IO,LVDS2N_17P,DQ2F41
IO,LVDS2N_18N,DQ2G40
IO,LVDS2N_18P,DQ2F40
IO,LVDS2N_19N,DQ3B40
IO,LVDS2N_19P,DQ3A40
IO,LVDS2N_1N,DQ0P39
IO,LVDS2N_1P,DQ0R39
IO,LVDS2N_20N,DQ3B39
IO,LVDS2N_20P,DQ3A39
IO,LVDS2N_21N,DQ3A41
IO,LVDS2N_21P,DQ3A42
IO,LVDS2N_22P,DQS3D41
IO,LVDS2N_23N,DQ3B43
IO,LVDS2N_23P,DQ3C43
IO,LVDS2N_24N,DQ3B42
IO,LVDS2N_2N,DQ0N37
IO,LVDS2N_2P,DQ0M37
IO,LVDS2N_3N,DQ0R36
IO,LVDS2N_3P,DQ0R37
IO,LVDS2N_4N,DQSN0M38
IO,LVDS2N_4P,DQS0N38
IO,LVDS2N_5N,DQ0M39
IO,LVDS2N_5P,DQ0L39
IO,LVDS2N_6N,DQ0R38
IO,LVDS2N_6P,DQ0P38
IO,LVDS2N_7N,DQ1G39
IO,LVDS2N_7P,DQ1F39
IO,LVDS2N_8N,DQ1K37
IO,LVDS2N_8P,DQ1L37
IO,LVDS2N_9N,DQ1K39
IO,LVDS2N_9P,DQ1J39
IO,PLL_2N_CLKOUT0N,LVDS2N_15N,DQ2E42
IO,PLL_2N_CLKOUT0P,PLL_2N_CLKOUT0,PLL_2N_FB0,LVDS2N_15P,DQ2F42
IO,PLL_2N_CLKOUT1N,LVDS2N_10N,DQSN1J38
IO,PLL_2N_CLKOUT1P,PLL_2N_CLKOUT1,PLL_2N_FB1,LVDS2N_10P,DQS1K38
IO,RZQ_2N,LVDS2N_11P,DQ1H40
IO,LVDS2N_22N,DQSN3C41
IO,LVDS2N_24P,DQ3C42
C312
2.2uF
0603
IO BANK 2KS10_DX_ND5_F2912D_EXTERNAL
U1-7
IO,CLK_2K_1N,LVDS2K_12N,DQ13H50
IO,CLK_2K_1P,LVDS2K_12P,DQ13H51
IO,PLL_2K_CLKOUT1N,LVDS2K_10N,DQSN13K49
IO,CLK_2K_0N,LVDS2K_13N,DQ14K54
IO,PLL_2K_CLKOUT1P,PLL_2K_CLKOUT1,PLL_2K_FB1,LVDS2K_10P,DQS13L49
IO,RZQ_2K,LVDS2K_11P,DQ13L51
IO,PLL_2K_CLKOUT0N,LVDS2K_15N,DQ14L52
IO,CLK_2K_0P,LVDS2K_13P,DQ14L54
IO,PLL_2K_CLKOUT0P,PLL_2K_CLKOUT0,PLL_2K_FB0,LVDS2K_15P,DQ14M52
IO,LVDS2K_21P,DQ15D53
IO,LVDS2K_23P,DQ15D54
IO,LVDS2K_24P,DQ15E52
IO,LVDS2K_21N,DQ15E53
IO,LVDS2K_23N,DQ15E54
IO,LVDS2K_24N,DQ15F52
IO,LVDS2K_19P,DQ15F54
IO,LVDS2K_20P,DQ15G52
IO,LVDS2K_22P,DQS15G53
IO,LVDS2K_19N,DQ15G54
IO,LVDS2K_20N,DQ15H52
IO,LVDS2K_22N,DQSN15H53
IO,LVDS2K_7N,DQ13J49
IO,LVDS2K_7P,DQ13J50
IO,LVDS2K_16P,DQS14J51
IO,LVDS2K_18P,DQ14J53IO,LVDS2K_18N,DQ14J54
IO,LVDS2K_8N,DQ13K47
IO,LVDS2K_8P,DQ13K48
IO,LVDS2K_16N,DQSN14K51
IO,LVDS2K_14P,DQ14K52IO,LVDS2K_14N,DQ14K53
IO,LVDS2K_1P,DQ12L46IO,LVDS2K_1N,DQ12L47
IO,LVDS2K_11N,DQ13L50
IO,LVDS2K_4N,DQSN12M45
IO,LVDS2K_3N,DQ12M47
IO,LVDS2K_3P,DQ12M48
IO,LVDS2K_9N,DQ13M49
IO,LVDS2K_9P,DQ13M50
IO,LVDS2K_17P,DQ14M53IO,LVDS2K_17N,DQ14M54
IO,LVDS2K_4P,DQS12N45
IO,LVDS2K_5P,DQ12N46IO,LVDS2K_5N,DQ12N47
IO,LVDS2K_2N,DQ12P44
IO,LVDS2K_2P,DQ12P45
IO,LVDS2K_6P,DQ12R44IO,LVDS2K_6N,DQ12T44
R22 2401%R0201
X2
50MHzECS-3518-500-B-xx
VCC4
GND2
OUT3
EN1
R6353 100
C409
0.1uF
0402
R293
10.0K
R212 2401%R0201
IO BANK 2MS10_DX_ND5_F2912D_EXTERNAL
U1-9
IO,RZQ_2M,LVDS2M_11P,DQ5J44
IO,CLK_2M_0N,LVDS2M_13N,DQ6D44
IO,CLK_2M_0P,LVDS2M_13P,DQ6E44
IO,CLK_2M_1N,LVDS2M_12N,DQ5H41
IO,CLK_2M_1P,LVDS2M_12P,DQ5J41
IO,PLL_2M_CLKOUT0N,LVDS2M_15N,DQ6E46
IO,PLL_2M_CLKOUT0P,PLL_2M_CLKOUT0,PLL_2M_FB0,LVDS2M_15P,DQ6F46
IO,PLL_2M_CLKOUT1N,LVDS2M_10N,DQSN5L41
IO,PLL_2M_CLKOUT1P,PLL_2M_CLKOUT1,PLL_2M_FB1,LVDS2M_10P,DQS5K41
IO,LVDS2M_11N,DQ5J43
IO,LVDS2M_14N,DQ6D43
IO,LVDS2M_14P,DQ6E43
IO,LVDS2M_16N,DQSN6G44
IO,LVDS2M_16P,DQS6F44
IO,LVDS2M_17N,DQ6E47
IO,LVDS2M_17P,DQ6F47
IO,LVDS2M_18N,DQ6G45
IO,LVDS2M_18P,DQ6F45
IO,LVDS2M_19N,DQ7C47
IO,LVDS2M_19P,DQ7B47
IO,LVDS2M_1N,DQ4M40
IO,LVDS2M_1P,DQ4L40
IO,LVDS2M_20N,DQ7B44
IO,LVDS2M_20P,DQ7A44
IO,LVDS2M_21N,DQ7B45
IO,LVDS2M_21P,DQ7A45
IO,LVDS2M_22N,DQSN7D45
IO,LVDS2M_22P,DQS7C45
IO,LVDS2M_23N,DQ7A46
IO,LVDS2M_23P,DQ7A47
IO,LVDS2M_24N,DQ7C46
IO,LVDS2M_24P,DQ7D46
IO,LVDS2M_2N,DQ4P40
IO,LVDS2M_2P,DQ4N40
IO,LVDS2M_3N,DQ4T40
IO,LVDS2M_3P,DQ4T39
IO,LVDS2M_4N,DQSN4N41
IO,LVDS2M_4P,DQS4P41
IO,LVDS2M_5N,DQ4V40
IO,LVDS2M_5P,DQ4U40
IO,LVDS2M_6N,DQ4T41
IO,LVDS2M_6P,DQ4R41
IO,LVDS2M_7N,DQ5H42
IO,LVDS2M_7P,DQ5G42
IO,LVDS2M_8N,DQ5L42
IO,LVDS2M_8P,DQ5K42
IO,LVDS2M_9N,DQ5G43
IO,LVDS2M_9P,DQ5H43
IO BANK 2LS10_DX_ND5_F2912D_EXTERNAL
U1-8
IO,PLL_2L_CLKOUT0P,PLL_2L_CLKOUT0,PLL_2L_FB0,LVDS2L_15P,DQ10D50
IO,PLL_2L_CLKOUT1P,PLL_2L_CLKOUT1,PLL_2L_FB1,LVDS2L_10P,DQS9J46
IO,LVDS2L_18P,DQ10A49
IO,LVDS2L_19N,DQ11A50
IO,LVDS2L_19P,DQ11A51
IO,CLK_2L_0P,LVDS2L_13P,DQ10B48
IO,LVDS2L_18N,DQ10B49
IO,LVDS2L_20P,DQ11B50
IO,LVDS2L_21N,DQ11B52
IO,LVDS2L_23N,DQ11B53
IO,CLK_2L_0N,LVDS2L_13N,DQ10C48
IO,LVDS2L_20N,DQ11C50
IO,LVDS2L_22N,DQSN11C51 IO,LVDS2L_21P,DQ11C52
IO,LVDS2L_23P,DQ11C53
IO,LVDS2L_14N,DQ10D48
IO,PLL_2L_CLKOUT0N,LVDS2L_15N,DQ10D49
IO,LVDS2L_22P,DQS11D51
IO,LVDS2L_14P,DQ10E48
IO,LVDS2L_16P,DQS10E49
IO,LVDS2L_24N,DQ11E51
IO,LVDS2L_16N,DQSN10F49
IO,LVDS2L_17N,DQ10F50
IO,LVDS2L_24P,DQ11F51
IO,LVDS2L_7N,DQ9G47
IO,RZQ_2L,LVDS2L_11P,DQ9G48 IO,LVDS2L_11N,DQ9G49
IO,LVDS2L_17P,DQ10G50
IO,CLK_2L_1N,LVDS2L_12N,DQ9H45
IO,PLL_2L_CLKOUT1N,LVDS2L_10N,DQSN9H46
IO,LVDS2L_7P,DQ9H47
IO,LVDS2L_9N,DQ9H48
IO,CLK_2L_1P,LVDS2L_12P,DQ9J45
IO,LVDS2L_9P,DQ9J48
IO,LVDS2L_8N,DQ9K43
IO,LVDS2L_8P,DQ9K44
IO,LVDS2L_5P,DQ8K46
IO,LVDS2L_3P,DQ8L44
IO,LVDS2L_5N,DQ8L45 IO,LVDS2L_4P,DQS8
M42
IO,LVDS2L_1N,DQ8M43
IO,LVDS2L_3N,DQ8M44
IO,LVDS2L_4N,DQSN8N42
IO,LVDS2L_1P,DQ8N43
IO,LVDS2L_6N,DQ8P43
IO,LVDS2L_2P,DQ8R42
IO,LVDS2L_6P,DQ8R43
IO,LVDS2L_2N,DQ8T42
CLK2_FPGA_50MCLKIN_50
RZQ_2L
DDR4_CH1_A16DDR4_CH1_A15DDR4_CH1_A14DDR4_CH1_A13
DDR4_CH1_BG0DDR4_CH1_BA1DDR4_CH1_BA0
DDR4_CH1_A11
DDR4_CH1_A9DDR4_CH1_A10
DDR4_CH1_A12
DDR4_CH1_A8DDR4_CH1_A7DDR4_CH1_A6DDR4_CH1_A5DDR4_CH1_A4DDR4_CH1_A3DDR4_CH1_A2DDR4_CH1_A1DDR4_CH1_A0DDR4_CH1_PARDDR4_CH1_ALERTNDDR4_CH1_CKNDDR4_CH1_CKP
DDR4_CH1_CKE
DDR4_CH1_ODTDDR4_CH1_ACTnDDR4_CH1_CSnDDR4_CH1_RESETnDDR4_CH1_BG1
DDR4_CH1_DQ35DDR4_CH1_DQ32
DDR4_CH1_DQS4PDDR4_CH1_DQS4N
DDR4_CH1_DM4
UPI2_LSIO_RX6
UPI2_LSIO_RX4
UPI2_LSIO_TX5
UPI1_LSIO_RX2UPI1_LSIO_RX1
UPI1_LSIO_RX4UPI1_LSIO_RX3
UPI1_LSIO_RX5UPI1_LSIO_RX6
UPI2_LSIO_RX1UPI2_LSIO_RX2UPI2_LSIO_RX3
UPI2_LSIO_TX1UPI2_LSIO_TX2UPI2_LSIO_TX3UPI2_LSIO_TX4
UPI2_LSIO_RX5
UPI2_LSIO_TX6
RZQ_2F
USB_FPGA_CLKUPI1_LSIO_TX6
UPI1_LSIO_TX4
UPI1_LSIO_TX1UPI1_LSIO_TX2UPI1_LSIO_TX3
UPI1_LSIO_TX5
USER_PB0
CPU_RESETn
CLK_133M_DDR4_1_NCLK_133M_DDR4_1_P
TSENSE_ALERTn_1V8
DDR4_CH1_DQ38DDR4_CH1_DQ37
DDR4_CH1_DQS6PDDR4_CH1_DQS6N
DDR4_CH1_DM6
DDR4_CH1_DQ69DDR4_CH1_DQ70
DDR4_CH1_DQ68
DDR4_CH1_DQ66DDR4_CH1_DQ71
DDR4_CH1_DQ64
DDR4_CH1_DQ67
DDR4_CH1_DM8
DDR4_CH1_DQS8NDDR4_CH1_DQS8P
DDR4_CH1_DQ65
DDR4_CH1_DQ20DDR4_CH1_DQ18
DDR4_CH1_DQ22DDR4_CH1_DQ16
DDR4_CH1_DQS2NDDR4_CH1_DQS2P
DDR4_CH1_DQ19
DDR4_CH1_DM2
DDR4_CH1_DQ23DDR4_CH1_DQ17DDR4_CH1_DQ21
DDR4_CH1_DM5
DDR4_CH1_DQ42
DDR4_CH1_DQ40
DDR4_CH1_DQS5NDDR4_CH1_DQS5P
DDR4_CH1_DQ41
DDR4_CH1_DQ5DDR4_CH1_DQ1
DDR4_CH1_DQ3DDR4_CH1_DQ7
DDR4_CH1_DQS0NDDR4_CH1_DQS0P
DDR4_CH1_DQ4
DDR4_CH1_DM0
DDR4_CH1_DM1
DDR4_CH1_DQ15DDR4_CH1_DQ14
DDR4_CH1_DQ12DDR4_CH1_DQ10
DDR4_CH1_DQ11DDR4_CH1_DQ13
DDR4_CH1_DQ8DDR4_CH1_DQ9DDR4_CH1_DQS1NDDR4_CH1_DQS1P
DDR4_CH1_DQ30DDR4_CH1_DM3
DDR4_CH1_DQ27DDR4_CH1_DQ29
DDR4_CH1_DQS3NDDR4_CH1_DQS3P
DDR4_CH1_DQ25
DDR4_CH1_DQ61
DDR4_CH1_DQ57
DDR4_CH1_DQ59
DDR4_CH1_DQS7PDDR4_CH1_DQS7N
DDR4_CH1_DQ63
DDR4_CH1_DQ62
DDR4_CH1_DQ56
DDR4_CH1_DQ58
DDR4_CH1_DQ60
DDR4_CH1_DM7
DDR4_CH1_DQ45
DDR4_CH1_DQ43DDR4_CH1_DQ47
DDR4_CH1_DQ46
DDR4_CH1_DQ44
DDR4_CH1_DQ31
DDR4_CH1_DQ24
DDR4_CH1_DQ26
DDR4_CH1_DQ28
DDR4_CH1_DQ6DDR4_CH1_DQ0DDR4_CH1_DQ2
DDR4_CH1_DQ51DDR4_CH1_DQ49
DDR4_CH1_DQ48DDR4_CH1_DQ50
DDR4_CH1_DQ52DDR4_CH1_DQ55
DDR4_CH1_DQ54DDR4_CH1_DQ53
DDR4_CH1_DQ34
DDR4_CH1_DQ36DDR4_CH1_DQ39
DDR4_CH1_DQ33
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 DX Bank 3A, B, C, D
1.2V
1.2V
1.2V
DDR4 DIMM CH0 IF
1.2V
CLOCK
DQSn/P for x4
DQSn/P for x4
DQSn/P for x4
DQSn/P for x4
DQSn/P for x4
DQSn/P for x4
DQSn/P for x4
DQSn/P for x4
DQSn/P for x4
DDR4_DIMM_CH0_C242
DDR4_DIMM_CH0_DQ[71:0]42
DDR4_DIMM_CH0_A[17:0]42
DDR4_DIMM_CH0_DQS_P[17:0]42
DDR4_DIMM_CH0_CKE[1:0]42
DDR4_DIMM_CH0_CK_P[1:0]42
DDR4_DIMM_CH0_DQS_N[17:0]42
DDR4_DIMM_CH0_ODT[1:0]42
DDR4_DIMM_CH0_RESET_N42
DDR4_DIMM_CH0_CK_N[1:0]42
DDR4_DIMM_CH0_CS_N[3:0]42
DDR4_DIMM_CH0_BG[1:0]42
DDR4_DIMM_CH0_BA[1:0]42
DDR4_DIMM_CH0_ACT_N42DDR4_DIMM_CH0_PAR42DDR4_DIMM_CH0_ALERT_N42
CLK_133M_DIMM_1_P 22CLK_133M_DIMM_1_N 22
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
10 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
10 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
10 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
IO BANK 3BS10_DX_ND5_F2912D_EXTERNAL
U1-12
IO,PLL_3B_CLKOUT1P,PLL_3B_CLKOUT1,PLL_3B_FB1,LVDS3B_10P,DQS89BG20
IO,PLL_3B_CLKOUT0P,PLL_3B_CLKOUT0,PLL_3B_FB0,LVDS3B_15P,DQ90BL20
IO,LVDS3B_4N,DQSN88BA20
IO,LVDS3B_1N,DQ88BA22
IO,LVDS3B_4P,DQS88BB20
IO,LVDS3B_1P,DQ88BB22
IO,LVDS3B_3N,DQ88BC20
IO,LVDS3B_3P,DQ88BC21
IO,LVDS3B_5N,DQ88BC22
IO,LVDS3B_6P,DQ88BD19 IO,LVDS3B_6N,DQ88BD20 IO,LVDS3B_5P,DQ88BD21
IO,LVDS3B_2N,DQ88BE18
IO,LVDS3B_2P,DQ88BE19
IO,LVDS3B_7N,DQ89BE21
IO,CLK_3B_1P,LVDS3B_12P,DQ89BF19
IO,PLL_3B_CLKOUT1N,LVDS3B_10N,DQSN89BF20
IO,LVDS3B_7P,DQ89BF21
IO,LVDS3B_9N,DQ89BF22
IO,LVDS3B_8N,DQ89BG18
IO,CLK_3B_1N,LVDS3B_12N,DQ89BG19
IO,LVDS3B_9P,DQ89BG22
IO,LVDS3B_8P,DQ89BH18
IO,LVDS3B_16P,DQS90BH20
IO,RZQ_3B,LVDS3B_11P,DQ89BH21 IO,LVDS3B_11N,DQ89BH22
IO,LVDS3B_14P,DQ90BJ18
IO,LVDS3B_18P,DQ90BJ19
IO,LVDS3B_16N,DQSN90BJ20
IO,CLK_3B_0N,LVDS3B_13N,DQ90BJ21
IO,LVDS3B_14N,DQ90BK18
IO,LVDS3B_18N,DQ90BK19
IO,CLK_3B_0P,LVDS3B_13P,DQ90BK21
IO,LVDS3B_17N,DQ90BK22
IO,PLL_3B_CLKOUT0N,LVDS3B_15N,DQ90BL19
IO,LVDS3B_19N,DQ91BL21
IO,LVDS3B_17P,DQ90BL22
IO,LVDS3B_20P,DQ91BM18 IO,LVDS3B_20N,DQ91BM19
IO,LVDS3B_22N,DQSN91BM20
IO,LVDS3B_19P,DQ91BM22
IO,LVDS3B_21N,DQ91BN18
IO,LVDS3B_22P,DQS91BN20
IO,LVDS3B_23N,DQ91BN21
IO,LVDS3B_21P,DQ91BP18
IO,LVDS3B_24N,DQ91BP19
IO,LVDS3B_24P,DQ91BP20
IO,LVDS3B_23P,DQ91BP21
R282401% R0201
IO BANK 3CS10_DX_ND5_F2912D_EXTERNAL
U1-13
IO,PLL_3C_CLKOUT1P,PLL_3C_CLKOUT1,PLL_3C_FB1,LVDS3C_10P,DQS85BH15
IO,PLL_3C_CLKOUT0P,PLL_3C_CLKOUT0,PLL_3C_FB0,LVDS3C_15P,DQ86BK17
IO,LVDS3C_6N,DQ84BC16
IO,LVDS3C_2P,DQ84BC17IO,LVDS3C_2N,DQ84BC18
IO,LVDS3C_6P,DQ84BD15
IO,LVDS3C_4N,DQSN84BD16
IO,LVDS3C_1N,DQ84BD18
IO,LVDS3C_4P,DQS84BE16
IO,LVDS3C_1P,DQ84BE17
IO,LVDS3C_7N,DQ85BF14
IO,LVDS3C_3N,DQ84BF15
IO,LVDS3C_3P,DQ84BF16
IO,LVDS3C_5P,DQ84BF17
IO,LVDS3C_7P,DQ85BG14
IO,PLL_3C_CLKOUT1N,LVDS3C_10N,DQSN85BG15
IO,LVDS3C_5N,DQ84BG17
IO,LVDS3C_8N,DQ85BH12
IO,LVDS3C_8P,DQ85BH13
IO,LVDS3C_9N,DQ85BH16
IO,LVDS3C_9P,DQ85BH17
IO,CLK_3C_1N,LVDS3C_12N,DQ85BJ13
IO,CLK_3C_1P,LVDS3C_12P,DQ85BJ14
IO,LVDS3C_11N,DQ85BJ15
IO,RZQ_3C,LVDS3C_11P,DQ85BJ16
IO,LVDS3C_14P,DQ86BK12IO,LVDS3C_14N,DQ86BK13
IO,LVDS3C_16P,DQS86BK14
IO,PLL_3C_CLKOUT0N,LVDS3C_15N,DQ86BK16
IO,LVDS3C_18P,DQ86BL12
IO,LVDS3C_16N,DQSN86BL14
IO,CLK_3C_0N,LVDS3C_13N,DQ86BL15
IO,CLK_3C_0P,LVDS3C_13P,DQ86BL16
IO,LVDS3C_17N,DQ86BL17
IO,LVDS3C_18N,DQ86BM12
IO,LVDS3C_20N,DQ87BM13
IO,LVDS3C_20P,DQ87BM14
IO,LVDS3C_22P,DQS87BM15
IO,LVDS3C_17P,DQ86BM17
IO,LVDS3C_19P,DQ87BN12IO,LVDS3C_19N,DQ87BN13
IO,LVDS3C_22N,DQSN87BN15
IO,LVDS3C_21N,DQ87BN16
IO,LVDS3C_21P,DQ87BN17
IO,LVDS3C_24N,DQ87BP13
IO,LVDS3C_24P,DQ87BP14
IO,LVDS3C_23N,DQ87BP15
IO,LVDS3C_23P,DQ87BP16
IO BANK 3AS10_DX_ND5_F2912D_EXTERNAL
U1-11
IO,PLL_3A_CLKOUT0p,PLL_3A_CLKOUT0,PLL_3A_FB0,LVDS3A_15p,DQ94,AVST_DATA27BG25
IO,PLL_3A_CLKOUT1p,PLL_3A_CLKOUT1,PLL_3A_FB1,LVDS3A_10p,DQS93,AVST_DATA19BK24
IO,LVDS3A_23n,DQ95AW24
IO,LVDS3A_23p,DQ95AY24
IO,LVDS3A_22n,DQSn95BA24 IO,LVDS3A_21p,DQ95BB23
IO,LVDS3A_22p,DQS95BB24
IO,LVDS3A_20n,DQ95BB25
IO,LVDS3A_21n,DQ95BC23 IO,LVDS3A_20p,DQ95BC25
IO,LVDS3A_19n,DQ95BD23
IO,LVDS3A_24n,DQ95BD25
IO,LVDS3A_24p,DQ95,AVST_CLKBD26
IO,LVDS3A_19p,DQ95BE23
IO,LVDS3A_17p,DQ94,AVST_DATA31BE24
IO,LVDS3A_16n,DQSn94,AVST_DATA28BE26
IO,LVDS3A_14p,DQ94,AVST_DATA25BE27
IO,LVDS3A_17n,DQ94,AVST_DATA30BF24
IO,PLL_3A_CLKOUT0n,LVDS3A_15n,DQ94,AVST_DATA26BF25
IO,LVDS3A_16p,DQS94,AVST_DATA29BF26
IO,LVDS3A_14n,DQ94,AVST_DATA24BF27
IO,RZQ_3A,LVDS3A_11p,DQ93,AVST_VALID,AVST_VALIDBG23
IO,CLK_3A_0n,LVDS3A_13n,DQ94,AVST_DATA22BG24
IO,LVDS3A_18p,DQ94BG27
IO,LVDS3A_11n,DQ93BH23
IO,CLK_3A_0p,LVDS3A_13p,DQ94,AVST_DATA23BH25
IO,LVDS3A_8n,DQ93,AVST_DATA14BH26
IO,LVDS3A_18n,DQ94BH27
IO,LVDS3A_9p,DQ93,AVST_DATA17BJ23
IO,CLK_3A_1p,LVDS3A_12p,DQ93,AVST_DATA21BJ24 IO,CLK_3A_1n,LVDS3A_12n,DQ93,AVST_DATA20BJ25
IO,LVDS3A_8p,DQ93,AVST_DATA15BJ26
IO,LVDS3A_9n,DQ93,AVST_DATA16BK23
IO,LVDS3A_7n,DQ93,AVST_DATA12BK26
IO,PLL_3A_CLKOUT1n,LVDS3A_10n,DQSn93,AVST_DATA18BL24
IO,LVDS3A_6n,DQ92,AVST_DATA10BL25
IO,LVDS3A_7p,DQ93,AVST_DATA13BL26
IO,LVDS3A_5p,DQ92,AVST_DATA9BM23 IO,LVDS3A_5n,DQ92,AVST_DATA8BM24
IO,LVDS3A_6p,DQ92,AVST_DATA11BM25
IO,LVDS3A_3n,DQ92,AVST_DATA4BN22
IO,LVDS3A_3p,DQ92,AVST_DATA5BN23
IO,LVDS3A_4p,DQS92,AVST_DATA7BN25
IO,LVDS3A_2p,DQ92,AVST_DATA3BN26
IO,LVDS3A_1p,DQ92,AVST_DATA1BP23 IO,LVDS3A_1n,DQ92,AVST_DATA0BP24
IO,LVDS3A_4n,DQSn92,AVST_DATA6BP25
IO,LVDS3A_2n,DQ92,AVST_DATA2BP26
IO BANK 3DS10_DX_ND5_F2912D_EXTERNAL
U1-14
IO,CLK_3D_0N,LVDS3D_13N,DQ82BD13
IO,PLL_3D_CLKOUT0N,LVDS3D_15N,DQ82BD14
IO,LVDS3D_18P,DQ82BE11
IO,LVDS3D_16N,DQSN82BE12
IO,CLK_3D_0P,LVDS3D_13P,DQ82BE13
IO,PLL_3D_CLKOUT0P,PLL_3D_CLKOUT0,PLL_3D_FB0,LVDS3D_15P,DQ82BE14
IO,LVDS3D_14P,DQ82BF10
IO,LVDS3D_18N,DQ82BF11
IO,LVDS3D_16P,DQS82BF12
IO,LVDS3D_14N,DQ82BG10
IO,LVDS3D_17N,DQ82BG12
IO,LVDS3D_17P,DQ82BG13
IO,LVDS3D_20N,DQ83BH10
IO,LVDS3D_22N,DQSN83BH11
IO,LVDS3D_20P,DQ83BJ10
IO,LVDS3D_22P,DQS83BJ11
IO,LVDS3D_24N,DQ83BK11
IO,LVDS3D_19N,DQ83BL10
IO,LVDS3D_24P,DQ83BL11
IO,LVDS3D_19P,DQ83BM10
IO,LVDS3D_21N,DQ83BN10
IO,LVDS3D_23N,DQ83BN11
IO,LVDS3D_21P,DQ83BP10
IO,LVDS3D_23P,DQ83BP11
R6354 100
DDR4_DIMM_CH0_A0DDR4_DIMM_CH0_A1DDR4_DIMM_CH0_A2DDR4_DIMM_CH0_A3DDR4_DIMM_CH0_A4DDR4_DIMM_CH0_A5DDR4_DIMM_CH0_A6DDR4_DIMM_CH0_A7DDR4_DIMM_CH0_A8DDR4_DIMM_CH0_A9DDR4_DIMM_CH0_A10DDR4_DIMM_CH0_A11
DDR4_DIMM_CH0_A12DDR4_DIMM_CH0_A13DDR4_DIMM_CH0_A14DDR4_DIMM_CH0_A15DDR4_DIMM_CH0_A16DDR4_DIMM_CH0_A17
DDR4_DIMM_CH0_CK_N0DDR4_DIMM_CH0_CK_P0
DDR4_DIMM_CH0_CK_N1DDR4_DIMM_CH0_CK_P1
DDR4_DIMM_CH0_CKE1DDR4_DIMM_CH0_CKE0
DDR4_DIMM_CH0_RESET_N
DDR4_DIMM_CH0_ACT_N
DDR4_DIMM_CH0_ODT1DDR4_DIMM_CH0_ODT0
DDR4_DIMM_CH0_BG1
DDR4_DIMM_CH0_BG0
DDR4_DIMM_CH0_BA0DDR4_DIMM_CH0_BA1
DDR4_DIMM_CH0_CS_N0
DDR4_DIMM_CH0_CS_N1DDR4_DIMM_CH0_PAR
DDR4_DIMM_CH0_DQS_N1DDR4_DIMM_CH0_DQS_P1
DDR4_DIMM_CH0_DQS_N2DDR4_DIMM_CH0_DQS_P2
DDR4_DIMM_CH0_DQS_P0DDR4_DIMM_CH0_DQS_N0
DDR4_DIMM_CH0_DQS_P7DDR4_DIMM_CH0_DQS_N7
DDR4_DIMM_CH0_DQS_N6DDR4_DIMM_CH0_DQS_P6
DDR4_DIMM_CH0_DQS_N4DDR4_DIMM_CH0_DQS_P4
DDR4_DIMM_CH0_DQS_P8DDR4_DIMM_CH0_DQS_N8
DDR4_DIMM_CH0_DQS_P3DDR4_DIMM_CH0_DQS_N3
RZQ_3B
DDR4_DIMM_CH0_DQS_P5DDR4_DIMM_CH0_DQS_N5
DDR4_DIMM_CH0_CS_N2DDR4_DIMM_CH0_CS_N3DDR4_DIMM_CH0_C2
DDR4_DIMM_CH0_ALERT_N
CLK_133M_DIMM_1_NCLK_133M_DIMM_1_P
DDR4_DIMM_CH0_DQS_N9DDR4_DIMM_CH0_DQS_P9
DDR4_DIMM_CH0_DQS_N10DDR4_DIMM_CH0_DQS_P10
DDR4_DIMM_CH0_DQS_P11DDR4_DIMM_CH0_DQS_N11
DDR4_DIMM_CH0_DQS_N12DDR4_DIMM_CH0_DQS_P12
DDR4_DIMM_CH0_DQS_P17DDR4_DIMM_CH0_DQS_N17
DDR4_DIMM_CH0_DQS_N13DDR4_DIMM_CH0_DQS_P13
DDR4_DIMM_CH0_DQS_P14DDR4_DIMM_CH0_DQS_N14
DDR4_DIMM_CH0_DQS_P15DDR4_DIMM_CH0_DQS_N15
DDR4_DIMM_CH0_DQS_P16DDR4_DIMM_CH0_DQS_N16
DDR4_DIMM_CH0_DQ13DDR4_DIMM_CH0_DQ12
DDR4_DIMM_CH0_DQ8
DDR4_DIMM_CH0_DQ14DDR4_DIMM_CH0_DQ15
DDR4_DIMM_CH0_DQ9
DDR4_DIMM_CH0_DQ10DDR4_DIMM_CH0_DQ11
DDR4_DIMM_CH0_DQ18DDR4_DIMM_CH0_DQ16
DDR4_DIMM_CH0_DQ21DDR4_DIMM_CH0_DQ20
DDR4_DIMM_CH0_DQ19DDR4_DIMM_CH0_DQ17
DDR4_DIMM_CH0_DQ23DDR4_DIMM_CH0_DQ22
DDR4_DIMM_CH0_DQ7DDR4_DIMM_CH0_DQ5
DDR4_DIMM_CH0_DQ4DDR4_DIMM_CH0_DQ6
DDR4_DIMM_CH0_DQ0DDR4_DIMM_CH0_DQ1DDR4_DIMM_CH0_DQ2DDR4_DIMM_CH0_DQ3
DDR4_DIMM_CH0_DQ59DDR4_DIMM_CH0_DQ58DDR4_DIMM_CH0_DQ56DDR4_DIMM_CH0_DQ57
DDR4_DIMM_CH0_DQ61DDR4_DIMM_CH0_DQ60
DDR4_DIMM_CH0_DQ63DDR4_DIMM_CH0_DQ62
DDR4_DIMM_CH0_DQ55DDR4_DIMM_CH0_DQ54
DDR4_DIMM_CH0_DQ53DDR4_DIMM_CH0_DQ52
DDR4_DIMM_CH0_DQ51DDR4_DIMM_CH0_DQ50DDR4_DIMM_CH0_DQ48DDR4_DIMM_CH0_DQ49DDR4_DIMM_CH0_DQ38DDR4_DIMM_CH0_DQ36
DDR4_DIMM_CH0_DQ37DDR4_DIMM_CH0_DQ39
DDR4_DIMM_CH0_DQ33DDR4_DIMM_CH0_DQ34DDR4_DIMM_CH0_DQ35DDR4_DIMM_CH0_DQ32
DDR4_DIMM_CH0_DQ66DDR4_DIMM_CH0_DQ65DDR4_DIMM_CH0_DQ64DDR4_DIMM_CH0_DQ67
DDR4_DIMM_CH0_DQ68DDR4_DIMM_CH0_DQ70
DDR4_DIMM_CH0_DQ71DDR4_DIMM_CH0_DQ69
DDR4_DIMM_CH0_DQ27
DDR4_DIMM_CH0_DQ24
DDR4_DIMM_CH0_DQ26DDR4_DIMM_CH0_DQ25
DDR4_DIMM_CH0_DQ31DDR4_DIMM_CH0_DQ30
DDR4_DIMM_CH0_DQ29DDR4_DIMM_CH0_DQ28
DDR4_DIMM_CH0_DQ43DDR4_DIMM_CH0_DQ41DDR4_DIMM_CH0_DQ42DDR4_DIMM_CH0_DQ40
DDR4_DIMM_CH0_DQ46DDR4_DIMM_CH0_DQ44
DDR4_DIMM_CH0_DQ45DDR4_DIMM_CH0_DQ47
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 DX Bank 3I,J,K
DDR4 CH1 INTERFACE
DDR4_CH0_BA034,35,36,37
DDR4_CH0_A1634,35,36,37DDR4_CH0_A1534,35,36,37DDR4_CH0_A1434,35,36,37
DDR4_CH0_A1334,35,36,37DDR4_CH0_A1234,35,36,37DDR4_CH0_A1134,35,36,37DDR4_CH0_A1034,35,36,37DDR4_CH0_A934,35,36,37DDR4_CH0_A834,35,36,37DDR4_CH0_A734,35,36,37DDR4_CH0_A634,35,36,37DDR4_CH0_A534,35,36,37DDR4_CH0_A434,35,36,37DDR4_CH0_A334,35,36,37DDR4_CH0_A234,35,36,37DDR4_CH0_A134,35,36,37DDR4_CH0_A034,35,36,37
DDR4_CH0_BA134,35,36,37
DDR4_CH0_BG134,35,36,37
DDR4_CH0_PAR34,35,36,37
DDR4_CH0_CKE34,35,36,37
DDR4_CH0_CKp34,35,36,37DDR4_CH0_CKn34,35,36,37
DDR4_CH0_CSn34,35,36,37
DDR4_CH0_ODT34,35,36,37
DDR4_CH0_ACTn34,35,36,37
DDR4_CH0_RESETn34,35,36,37DDR4_CH0_TEN34,35,36
DDR4_CH0_BG034,35,36,37
DDR4_CH0_ALERTn34,35,36
DDR4_CH0_DQ[71:0]34,35,36
DDR4_CH0_DQS0n34DDR4_CH0_DQS0p34
DDR4_CH0_DQS3n34DDR4_CH0_DQS3p34
DDR4_CH0_DQS1n34DDR4_CH0_DQS1p34
DDR4_CH0_DQS8n36DDR4_CH0_DQS8p36
DDR4_CH0_DM034
DDR4_CH0_DM334
DDR4_CH0_DM134
DDR4_CH0_DM836
DDR4_CH0_DQS2n34DDR4_CH0_DQS2p34
DDR4_CH0_DM234
DDR4_CH0_DQS4n35DDR4_CH0_DQS4p35
DDR4_CH0_DM435
DDR4_CH0_DQS5p35DDR4_CH0_DQS5n35
DDR4_CH0_DM535
DDR4_CH0_DQS6p35
DDR4_CH0_DM635DDR4_CH0_DQS6n35
DDR4_CH0_DM735
DDR4_CH0_DQS7p35DDR4_CH0_DQS7n35
CLK_133M_DDR4_0_N22CLK_133M_DDR4_0_P22
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
11 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
11 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
11 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
IO BANK 3IS10_DX_ND5_F2912D_EXTERNAL
U1-16
IO,PLL_3I_CLKOUT0P,PLL_3I_CLKOUT0,PLL_3I_FB0,LVDS3I_15P,DQ62D11
IO,PLL_3I_CLKOUT1P,PLL_3I_CLKOUT1,PLL_3I_FB1,LVDS3I_10P,DQS61K13
IO,LVDS3I_20N,DQ63A10
IO,LVDS3I_23P,DQ63A11IO,LVDS3I_23N,DQ63A12
IO,LVDS3I_24P,DQ63A8IO,LVDS3I_24N,DQ63A9
IO,LVDS3I_20P,DQ63B10
IO,LVDS3I_21P,DQ63B12
IO,LVDS3I_19P,DQ63B13
IO,LVDS3I_22N,DQSN63C10
IO,PLL_3I_CLKOUT0N,LVDS3I_15N,DQ62C11
IO,LVDS3I_21N,DQ63C12
IO,LVDS3I_19N,DQ63C13
IO,LVDS3I_22P,DQS63D10
IO,CLK_3I_0P,LVDS3I_13P,DQ62D13
IO,LVDS3I_14N,DQ62E11
IO,LVDS3I_14P,DQ62E12
IO,CLK_3I_0N,LVDS3I_13N,DQ62E13
IO,LVDS3I_17N,DQ62F10
IO,LVDS3I_17P,DQ62F11
IO,LVDS3I_16P,DQS62F12
IO,LVDS3I_18P,DQ62G10
IO,LVDS3I_16N,DQSN62G12
IO,LVDS3I_9N,DQ61G13
IO,LVDS3I_18N,DQ62H10
IO,LVDS3I_11N,DQ61H11
IO,RZQ_3I,LVDS3I_11P,DQ61H12
IO,LVDS3I_9P,DQ61H13
IO,LVDS3I_5P,DQ60H15
IO,LVDS3I_4P,DQS60H16
IO,LVDS3I_3N,DQ60H17
IO,CLK_3I_1N,LVDS3I_12N,DQ61J10
IO,CLK_3I_1P,LVDS3I_12P,DQ61J11
IO,PLL_3I_CLKOUT1N,LVDS3I_10N,DQSN61J13
IO,LVDS3I_7P,DQ61J14
IO,LVDS3I_5N,DQ60J15
IO,LVDS3I_4N,DQSN60J16IO,LVDS3I_3P,DQ60J18
IO,LVDS3I_1P,DQ60J19IO,LVDS3I_1N,DQ60J20
IO,LVDS3I_8N,DQ61K11
IO,LVDS3I_8P,DQ61K12
IO,LVDS3I_7N,DQ61K14
IO,LVDS3I_6N,DQ60K16
IO,LVDS3I_6P,DQ60K17
IO,LVDS3I_2P,DQ60K18IO,LVDS3I_2N,DQ60K19
R6355 100
IO BANK 3KS10_DX_ND5_F2912D_EXTERNAL
U1-18
IO,PLL_3K_CLKOUT1P,PLL_3K_CLKOUT1,PLL_3K_FB1,LVDS3K_10P,DQS53D21
IO,PLL_3K_CLKOUT0P,PLL_3K_CLKOUT0,PLL_3K_FB0,LVDS3K_15P,DQ54K23
IO,LVDS3K_5P,DQ52A19
IO,LVDS3K_3N,DQ52A20
IO,LVDS3K_1P,DQ52A21 IO,LVDS3K_1N,DQ52A22
IO,LVDS3K_2N,DQ52B18
IO,LVDS3K_5N,DQ52B19
IO,LVDS3K_3P,DQ52B20
IO,LVDS3K_9N,DQ53B22
IO,LVDS3K_2P,DQ52C18
IO,LVDS3K_4N,DQSN52C20
IO,PLL_3K_CLKOUT1N,LVDS3K_10N,DQSN53C21 IO,LVDS3K_9P,DQ53C22
IO,LVDS3K_6P,DQ52D18 IO,LVDS3K_6N,DQ52D19
IO,LVDS3K_4P,DQS52D20
IO,RZQ_3K,LVDS3K_11P,DQ53D23 IO,LVDS3K_11N,DQ53D24
IO,LVDS3K_7N,DQ53D25
IO,CLK_3K_1P,LVDS3K_12P,DQ53E22 IO,CLK_3K_1N,LVDS3K_12N,DQ53E23
IO,LVDS3K_7P,DQ53E24
IO,CLK_3K_0N,LVDS3K_13N,DQ54F24
IO,LVDS3K_8P,DQ53F25
IO,LVDS3K_17N,DQ54G23
IO,CLK_3K_0P,LVDS3K_13P,DQ54G24
IO,LVDS3K_8N,DQ53G25
IO,LVDS3K_17P,DQ54H23
IO,LVDS3K_14P,DQ54H25
IO,PLL_3K_CLKOUT0N,LVDS3K_15N,DQ54J23
IO,LVDS3K_16P,DQS54J24
IO,LVDS3K_14N,DQ54J25
IO,LVDS3K_16N,DQSN54K24
IO,LVDS3K_19N,DQ55L24 IO,LVDS3K_18P,DQ54L25
IO,LVDS3K_23N,DQ55M23
IO,LVDS3K_19P,DQ55M24
IO,LVDS3K_18N,DQ54M25
IO,LVDS3K_23P,DQ55N23
IO,LVDS3K_21N,DQ55N25
IO,LVDS3K_20N,DQ55P23
IO,LVDS3K_22N,DQSN55P24 IO,LVDS3K_21P,DQ55P25
IO,LVDS3K_20P,DQ55R23
IO,LVDS3K_22P,DQS55R24
IO,LVDS3K_24N,DQ55T24
IO,LVDS3K_24P,DQ55T25
IO BANK 3JS10_DX_ND5_F2912D_EXTERNAL
U1-17
IO,PLL_3J_CLKOUT0P,PLL_3J_CLKOUT0,PLL_3J_FB0,LVDS3J_15P,DQ58B14
IO,PLL_3J_CLKOUT1P,PLL_3J_CLKOUT1,PLL_3J_FB1,LVDS3J_10P,DQS57G20
IO,PLL_3J_CLKOUT0N,LVDS3J_15N,DQ58A14
IO,CLK_3J_0N,LVDS3J_13N,DQ58A15
IO,LVDS3J_18N,DQ58A16
IO,LVDS3J_18P,DQ58A17
IO,CLK_3J_0P,LVDS3J_13P,DQ58B15
IO,LVDS3J_14P,DQ58B17
IO,LVDS3J_17N,DQ58C15 IO,LVDS3J_16P,DQS58C16
IO,LVDS3J_14N,DQ58C17
IO,LVDS3J_19N,DQ59D14
IO,LVDS3J_17P,DQ58D15
IO,LVDS3J_16N,DQSN58D16
IO,LVDS3J_19P,DQ59E14
IO,LVDS3J_22N,DQSN59E16
IO,LVDS3J_24N,DQ59E17
IO,LVDS3J_24P,DQ59E18
IO,LVDS3J_9P,DQ57E19
IO,CLK_3J_1P,LVDS3J_12P,DQ57E21
IO,LVDS3J_23N,DQ59F14
IO,LVDS3J_21N,DQ59F15
IO,LVDS3J_22P,DQS59F16
IO,LVDS3J_20P,DQ59F17
IO,LVDS3J_9N,DQ57F19
IO,PLL_3J_CLKOUT1N,LVDS3J_10N,DQSN57F20
IO,CLK_3J_1N,LVDS3J_12N,DQ57F21
IO,LVDS3J_8P,DQ57F22
IO,LVDS3J_23P,DQ59G14
IO,LVDS3J_21P,DQ59G15
IO,LVDS3J_20N,DQ59G17
IO,LVDS3J_11N,DQ57G18
IO,LVDS3J_7P,DQ57G19
IO,LVDS3J_8N,DQ57G22
IO,RZQ_3J,LVDS3J_11P,DQ57H18
IO,LVDS3J_7N,DQ57H20
IO,LVDS3J_5P,DQ56H21 IO,LVDS3J_5N,DQ56H22
IO,LVDS3J_1N,DQ56J21
IO,LVDS3J_1P,DQ56K21
IO,LVDS3J_6N,DQ56K22
IO,LVDS3J_6P,DQ56L22
IO,LVDS3J_4P,DQS56M22
IO,LVDS3J_3N,DQ56N21
IO,LVDS3J_4N,DQSN56N22 IO,LVDS3J_3P,DQ56P21
IO,LVDS3J_2N,DQ56R21
IO,LVDS3J_2P,DQ56R22
R211 2401%R0201
DDR4_CH0_A16DDR4_CH0_A15DDR4_CH0_A14DDR4_CH0_A13
DDR4_CH0_BG0DDR4_CH0_BA1DDR4_CH0_BA0
DDR4_CH0_A11
DDR4_CH0_A9DDR4_CH0_A10
DDR4_CH0_A12
DDR4_CH0_A8DDR4_CH0_A7DDR4_CH0_A6DDR4_CH0_A5DDR4_CH0_A4DDR4_CH0_A3DDR4_CH0_A2DDR4_CH0_A1DDR4_CH0_A0DDR4_CH0_PARDDR4_CH0_ALERTNDDR4_CH0_CKNDDR4_CH0_CKP
DDR4_CH0_CKE
DDR4_CH0_ODTDDR4_CH0_ACTnDDR4_CH0_CSnDDR4_CH0_RESETnDDR4_CH0_BG1
RZQ_3J
CLK_133M_DDR4_0_PCLK_133M_DDR4_0_N
DDR4_CH0_DQ25
DDR4_CH0_DQS3NDDR4_CH0_DQS3P
DDR4_CH0_DM3
DDR4_CH0_DQ24
DDR4_CH0_DQ26DDR4_CH0_DQ28
DDR4_CH0_DQ47DDR4_CH0_DQ46
DDR4_CH0_DQ43DDR4_CH0_DQ41DDR4_CH0_DQ45
DDR4_CH0_DQS5NDDR4_CH0_DQS5P
DDR4_CH0_DQ42DDR4_CH0_DQ40
DDR4_CH0_DQ44
DDR4_CH0_DM5
DDR4_CH0_DQ7DDR4_CH0_DQ5
DDR4_CH0_DQS0PDDR4_CH0_DQS0N
DDR4_CH0_DQ1DDR4_CH0_DM0
DDR4_CH0_DQ9
DDR4_CH0_DM1
DDR4_CH0_DQS1NDDR4_CH0_DQS1P
DDR4_CH0_DQ10
DDR4_CH0_DQ12
DDR4_CH0_DM2
DDR4_CH0_DQ17
DDR4_CH0_DQS2PDDR4_CH0_DQS2N
DDR4_CH0_DQ62DDR4_CH0_DQ63
DDR4_CH0_DQ60DDR4_CH0_DQ59
DDR4_CH0_DQ57DDR4_CH0_DQ58
DDR4_CH0_DQS7NDDR4_CH0_DQS7P
DDR4_CH0_DQ61DDR4_CH0_DQ56
DDR4_CH0_DM7
DDR4_CH0_DQ37DDR4_CH0_DQ38
DDR4_CH0_DQ39DDR4_CH0_DQ32
DDR4_CH0_DQ33DDR4_CH0_DQ35
DDR4_CH0_DM4
DDR4_CH0_DQ34DDR4_CH0_DQ36
DDR4_CH0_DQS4NDDR4_CH0_DQS4P
DDR4_CH0_DQ69
DDR4_CH0_DQ66
DDR4_CH0_DM8
DDR4_CH0_DQS8NDDR4_CH0_DQS8P
DDR4_CH0_DQ68
DDR4_CH0_DQ53
DDR4_CH0_DQ51
DDR4_CH0_DQ49DDR4_CH0_DM6
DDR4_CH0_DQS6PDDR4_CH0_DQS6N
DDR4_CH0_DQ55DDR4_CH0_DQ48
DDR4_CH0_DQ29DDR4_CH0_DQ27DDR4_CH0_DQ31
DDR4_CH0_DQ30
DDR4_CH0_DQ4DDR4_CH0_DQ6
DDR4_CH0_DQ3DDR4_CH0_DQ2
DDR4_CH0_DQ0
DDR4_CH0_DQ13DDR4_CH0_DQ11
DDR4_CH0_DQ15DDR4_CH0_DQ14
DDR4_CH0_DQ8
DDR4_CH0_DQ21
DDR4_CH0_DQ16
DDR4_CH0_DQ18
DDR4_CH0_DQ19
DDR4_CH0_DQ20
DDR4_CH0_DQ23DDR4_CH0_DQ22
DDR4_CH0_DQ50DDR4_CH0_DQ52DDR4_CH0_DQ54
DDR4_CH0_DQ71
DDR4_CH0_DQ70
DDR4_CH0_DQ67
DDR4_CH0_DQ64
DDR4_CH0_DQ65
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 DX Bank 3H, L PARTIAL RECONFIG SIGNALS
UPI INTERFACE
CLOCK
1.8V
1.8V
FPGA_PR_DONE 23FPGA_PR_ERROR 23
FPGA_PR_REQUEST 23
UPI0_LSIO_RX[6:1] 25
UPI0_LSIO_TX[6:1] 25
CLK_100M_FPGA_3L_0_N 22CLK_100M_FPGA_3L_0_P 22
S10_UPI0_NID0_1V8 17,68S10_UPI0_NID1_1V8 17,68
S10_UPI1_NID0_1V8 17,68S10_UPI1_NID1_1V8 17,68
S10_UPI2_NID0_1V8 17,68S10_UPI2_NID1_1V8 17,68
UPI0_PCIe_SCL 68UPI0_PCIe_SDA 68
UPI1_PCIe_SCL 68UPI1_PCIe_SDA 68
UPI2_PCIe_SDA 68UPI2_PCIe_SCL 68
S10_UPI0_PERSTn_SEL 68S10_UPI1_PERSTn_SEL 68S10_UPI2_PERSTn_SEL 68
S10_UPI2_PRNSTn_1V8 68
S10_UPI0_PRNSTn_1V8 68S10_UPI1_PRNSTn_1V8 68
PCIE_Ep_IO 68
UPI0_Ep_IO 68
UPI1_Ep_IO 68
UPI2_Ep_IO 68
CLK_100M_FPGA_3H_P 22CLK_100M_FPGA_3H_N 22
UPI0_Rp_IO 68
UPI1_Rp_IO 68
UPI2_Rp_IO 68
PCIE_Rp_IO 68
CLK_100M_FPGA_3L_1_N 22CLK_100M_FPGA_3L_1_P 22
UPI_MODE_3L 17
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
12 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
12 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
12 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R547110.0K,DNI
R6707 100
IO BANK 3LS10_DX_ND5_F2912D_EXTERNAL
U1-19
IO,PLL_3L_CLKOUT0P,PLL_3L_CLKOUT0,PLL_3L_FB0,LVDS3L_15P,DQ50B24
IO,PLL_3L_CLKOUT1P,PLL_3L_CLKOUT1,PLL_3L_FB1,LVDS3L_10P,DQS49H28
IO,PLL_3L_CLKOUT0N,LVDS3L_15N,DQ50A24
IO,LVDS3L_16N,DQSN50A25
IO,LVDS3L_18P,DQ50A26IO,LVDS3L_18N,DQ50A27
IO,CLK_3L_0N,LVDS3L_13N,DQ50B23
IO,LVDS3L_16P,DQS50B25
IO,LVDS3L_17P,DQ50B27
IO,LVDS3L_20P,DQ51B28
IO,CLK_3L_0P,LVDS3L_13P,DQ50C23
IO,LVDS3L_14P,DQ50C25IO,LVDS3L_14N,DQ50C26
IO,LVDS3L_17N,DQ50C27
IO,LVDS3L_20N,DQ51C28
IO,LVDS3L_21P,DQ51D26
IO,LVDS3L_22P,DQS51D28
IO,LVDS3L_24N,DQ51D29
IO,LVDS3L_21N,DQ51E26
IO,LVDS3L_19P,DQ51E27
IO,LVDS3L_22N,DQSN51E28
IO,LVDS3L_24P,DQ51E29
IO,LVDS3L_8P,DQ49F26
IO,LVDS3L_19N,DQ51F27
IO,LVDS3L_23N,DQ51F29
IO,LVDS3L_8N,DQ49G27
IO,PLL_3L_CLKOUT1N,LVDS3L_10N,DQSN49G28
IO,LVDS3L_23P,DQ51G29
IO,LVDS3L_9N,DQ49H26
IO,LVDS3L_9P,DQ49H27
IO,LVDS3L_7N,DQ49J26
IO,CLK_3L_1N,LVDS3L_12N,DQ49J28
IO,CLK_3L_1P,LVDS3L_12P,DQ49J29
IO,LVDS3L_7P,DQ49K26
IO,LVDS3L_11N,DQ49K27
IO,RZQ_3L,LVDS3L_11P,DQ49K28
IO,LVDS3L_5P,DQ48L26IO,LVDS3L_5N,DQ48L27IO,LVDS3L_4P,DQS48M27
IO,LVDS3L_6N,DQ48M28
IO,LVDS3L_1P,DQ48N26
IO,LVDS3L_4N,DQSN48N27
IO,LVDS3L_6P,DQ48N28
IO,LVDS3L_1N,DQ48P26
IO,LVDS3L_2N,DQ48P28
IO,LVDS3L_3N,DQ48R26
IO,LVDS3L_3P,DQ48R27
IO,LVDS3L_2P,DQ48R28
R6475 100
R34 10.0K
IO BANK 3HS10_DX_ND5_F2912D_EXTERNAL
U1-15
IO,CLK_3H_1N,LVDS3H_12N,DQ65A30
IO,CLK_3H_1P,LVDS3H_12P,DQ65A31
IO,PLL_3H_CLKOUT1P,PLL_3H_CLKOUT1,PLL_3H_FB1,LVDS3H_10P,DQS65B30 IO,PLL_3H_CLKOUT1N,LVDS3H_10N,DQSN65C30
IO,RZQ_3H,LVDS3H_11P,DQ65E31
IO,LVDS3H_4N,DQSN64L30
IO,LVDS3H_4P,DQS64M30
IO,LVDS3H_8P,DQ65A29 IO,LVDS3H_8N,DQ65B29 IO,LVDS3H_7P,DQ65C31 IO,LVDS3H_7N,DQ65D30
IO,LVDS3H_11N,DQ65D31
IO,LVDS3H_9N,DQ65F30
IO,LVDS3H_9P,DQ65F31
IO,LVDS3H_1N,DQ64G30
IO,LVDS3H_1P,DQ64H30
IO,LVDS3H_6P,DQ64H31
IO,LVDS3H_2P,DQ64J30
IO,LVDS3H_6N,DQ64J31
IO,LVDS3H_2N,DQ64K29
IO,LVDS3H_5P,DQ64L29 IO,LVDS3H_5N,DQ64
M29
IO,LVDS3H_3P,DQ64N30 IO,LVDS3H_3N,DQ64P30
R6366 0
R547010.0K,DNI
R30 10.0K
R6367 0
R35 100
R6460 100
R546810.0K
R6364 0
R546910.0K
R6365 0
R6369 0R6368 0
R6359 100
USER_PUPD1
RZQ_3H
USER_PUPD2
FPGA_PR_DONEFPGA_PR_ERROR
FPGA_PR_DONEFPGA_PR_ERROR
FPGA_PR_REQUEST
CLK_100M_FPGA_3L_0_NCLK_100M_FPGA_3L_0_P
S10_UPI0_PERSTn_SELS10_UPI1_PERSTn_SELS10_UPI2_PERSTn_SEL
S10_UPI2_PRNSTn_1V8
S10_UPI0_PRNSTn_1V8S10_UPI1_PRNSTn_1V8
S10_UPI0_NID0_1V8S10_UPI0_NID1_1V8
S10_UPI1_NID0_1V8S10_UPI1_NID1_1V8
S10_UPI2_NID0_1V8S10_UPI2_NID1_1V8
UPI2_PCIe_SDAUPI2_PCIe_SCL
UPI1_PCIe_SDAUPI1_PCIe_SCL
UPI0_PCIe_SDAUPI0_PCIe_SCL
UPI0_LSIO_RX3UPI0_LSIO_RX4UPI0_LSIO_RX5UPI0_LSIO_RX6
UPI0_LSIO_TX1UPI0_LSIO_TX2UPI0_LSIO_TX3UPI0_LSIO_TX4UPI0_LSIO_TX5UPI0_LSIO_TX6
UPI0_LSIO_RX1UPI0_LSIO_RX2
RZQ_3L
UPI1_Ep_IOUPI0_Ep_IOPCIE_Ep_IO
UPI2_Ep_IO
CLK_100M_FPGA_3H_NCLK_100M_FPGA_3H_P
UPI0_Rp_IO
UPI1_Rp_IO
UPI2_Rp_IO
PCIE_Rp_IO
CLK_100M_FPGA_3L_1_NCLK_100M_FPGA_3L_1_P
UPI_MODE_3L
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
JTAG /Configuration/Flash Interface Diagram
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
13 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
13 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
13 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 DX Xcvr GXER 9A
QSFP2 INTERFACE
QSFP2
QSFP1 INTERFACE
QSFP1
CLOCK
QSFP2_RX_P[3:0] 30QSFP2_RX_N[3:0] 30
QSFP2_TX_P[3:0] 30QSFP2_TX_N[3:0] 30
QSFP1_TX_P[3:0] 29
QSFP1_RX_N[3:0] 29QSFP1_RX_P[3:0] 29
QSFP1_TX_N[3:0] 29
CLK_156.25M_QSFP0_N 22CLK_156.25M_QSFP0_P 22
CLK_156.25M_QSFP1_P 22CLK_156.25M_QSFP1_N 22
CLK_312.5M_QSFP0_N 22CLK_312.5M_QSFP0_P 22
CLK_312.5M_QSFP1_P 22CLK_312.5M_QSFP1_N 22
CLK_312.5M_QSFP2_P 22CLK_312.5M_QSFP2_N 22
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
14 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
14 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
14 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
XCVR BANK 9AS10_DX_ND5_F2912D_EXTERNAL
U1-20
GXER9A_RX_CH15PBC7 GXER9A_RX_CH15NBC8
GXER9A_RX_CH14PBD4 GXER9A_RX_CH14NBD5
GXER9A_RX_CH13PBE7 GXER9A_RX_CH13NBE8
GXER9A_RX_CH12PBF4 GXER9A_RX_CH12NBF5
GXER9A_RX_CH3PBG7 GXER9A_RX_CH3NBG8
GXER9A_RX_CH2PBJ7 GXER9A_RX_CH2NBJ8
GXER9A_RX_CH1PBL7 GXER9A_RX_CH1NBL8
GXER9A_RX_CH0PBN7 GXER9A_RX_CH0NBN8
REFCLK_GXER9A_CH2PAT10
REFCLK_GXER9A_CH0PAT11
REFCLK_GXER9A_CH2NAU10
REFCLK_GXER9A_CH0NAU11
REFCLK_GXER9A_CH3PAV10 REFCLK_GXER9A_CH3NAW10
REFCLK_GXER9A_CH1PAW11 REFCLK_GXER9A_CH1NAY11
GXER9A_TX_CH15PBE1GXER9A_TX_CH15NBE2
GXER9A_TX_CH14PBG1GXER9A_TX_CH14NBG2
GXER9A_TX_CH13PBH4GXER9A_TX_CH13NBH5
GXER9A_TX_CH12PBJ1GXER9A_TX_CH12NBJ2
GXER9A_TX_CH3PBK4GXER9A_TX_CH3NBK5
GXER9A_TX_CH2PBL1GXER9A_TX_CH2NBL2
GXER9A_TX_CH1PBM4GXER9A_TX_CH1NBM5
GXER9A_TX_CH0PBP4GXER9A_TX_CH0NBP5
REFCLK_GXER9A_CH8PBC11 REFCLK_GXER9A_CH8NBC10
R6371 100
R6487 100
R6370 100
R6438 100
R6437 100
QSFP1_RX_P0QSFP1_RX_N0
QSFP1_RX_P1QSFP1_RX_N1
QSFP1_RX_N2QSFP1_RX_P2
QSFP1_RX_P3QSFP1_RX_N3
QSFP2_RX_N0QSFP2_RX_P0
QSFP2_RX_P1QSFP2_RX_N1
QSFP2_RX_N2QSFP2_RX_P2
QSFP2_RX_N3QSFP2_RX_P3
CLK_156.25M_QSFP0_PCLK_156.25M_QSFP0_N
CLK_156.25M_QSFP1_PCLK_156.25M_QSFP1_N
QSFP1_TX_N0QSFP1_TX_P0
QSFP1_TX_N1QSFP1_TX_P1
QSFP1_TX_N2QSFP1_TX_P2
QSFP1_TX_N3QSFP1_TX_P3
QSFP2_TX_P0QSFP2_TX_N0
QSFP2_TX_N1QSFP2_TX_P1
QSFP2_TX_N2QSFP2_TX_P2
QSFP2_TX_N3QSFP2_TX_P3
CLK_312.5M_QSFP0_NCLK_312.5M_QSFP0_P
CLK_312.5M_QSFP1_NCLK_312.5M_QSFP1_P
CLK_312.5M_QSFP2_PCLK_312.5M_QSFP2_N
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 DX Xcvr GXPL 10A,10B
PCIE x16 PCIE x16
PCIE x16 INTERFACE
UPI0 INTERFACE
CLOCKs
RESREF = 169 Ohm for 85 Ohm UPI/PCIe or 200 Ohm for 100 Ohm UPI/PCIe
RESREF = 169 Ohm for 85 Ohm UPI/PCIe or 200 Ohm for 100 Ohm UPI/PCIe
PCIE_TX_P[15:0] 21PCIE_TX_N[15:0] 21
PCIE_RX_P[15:0] 21PCIE_RX_N[15:0] 21
UPI0_FPGA_CPU_DP[19:0] 25UPI0_FPGA_CPU_DN[19:0] 25
UPI0_CPU_FPGA_DP[19:0] 25UPI0_CPU_FPGA_DN[19:0] 25
CLK_100M_UPI0_0_P 22CLK_100M_UPI0_0_N 22
CLK_100M_UPI0_1_P 22CLK_100M_UPI0_1_N 22
CLK_100M_PCIE_0_N 22CLK_100M_PCIE_0_P 22
CLK_100M_PCIE_1_P 22CLK_100M_PCIE_1_N 22
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
15 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
15 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
15 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.XCVR BANK 10B
S10_DX_ND5_F2912D_EXTERNAL
U1-22
U11_P_IO_RESREF_0AC41
REFCLK_GXPL10B_CH2NAG44
REFCLK_GXPL10B_CH2PAG45
REFCLK_GXPL10B_CH0NAJ44
REFCLK_GXPL10B_CH0PAJ45
GXPL10B_RX_CH12NAA51
GXPL10B_RX_CH12PAA52
GXPL10B_RX_CH11NAB53
GXPL10B_RX_CH11PAB54
GXPL10B_RX_CH10NAC51
GXPL10B_RX_CH10PAC52
GXPL10B_RX_CH9NAD53
GXPL10B_RX_CH9PAD54
GXPL10B_RX_CH8NAE51
GXPL10B_RX_CH8PAE52
GXPL10B_RX_CH7NAF53
GXPL10B_RX_CH7PAF54
GXPL10B_RX_CH6NAG51
GXPL10B_RX_CH6PAG52
GXPL10B_RX_CH5NAH53
GXPL10B_RX_CH5PAH54
GXPL10B_RX_CH4NAJ51
GXPL10B_RX_CH4PAJ52
GXPL10B_RX_CH3NAK53
GXPL10B_RX_CH3PAK54
GXPL10B_RX_CH2NAL51
GXPL10B_RX_CH2PAL52
GXPL10B_RX_CH1NAM53
GXPL10B_RX_CH1PAM54
GXPL10B_RX_CH0NAN51
GXPL10B_RX_CH0PAN52
GXPL10B_RX_CH19NP53
GXPL10B_RX_CH19PP54
GXPL10B_RX_CH18NR51
GXPL10B_RX_CH18PR52
GXPL10B_RX_CH17NT53
GXPL10B_RX_CH17PT54
GXPL10B_RX_CH16NU51
GXPL10B_RX_CH16PU52
GXPL10B_RX_CH15NV53
GXPL10B_RX_CH15PV54
GXPL10B_RX_CH14NW51
GXPL10B_RX_CH14PW52
GXPL10B_RX_CH13NY53
GXPL10B_RX_CH13PY54
GXPL10B_TX_CH6NAG47
GXPL10B_TX_CH6PAG48
GXPL10B_TX_CH5NAH49
GXPL10B_TX_CH5PAH50
GXPL10B_TX_CH4NAJ47
GXPL10B_TX_CH4PAJ48
GXPL10B_TX_CH3NAK49
GXPL10B_TX_CH3PAK50
GXPL10B_TX_CH2NAL47
GXPL10B_TX_CH2PAL48
GXPL10B_TX_CH1NAM49
GXPL10B_TX_CH1PAM50
GXPL10B_TX_CH0NAN47
GXPL10B_TX_CH0PAN48
GXPL10B_TX_CH12NAA47
GXPL10B_TX_CH12PAA48
GXPL10B_TX_CH11NAB49
GXPL10B_TX_CH11PAB50
GXPL10B_TX_CH10NAC47
GXPL10B_TX_CH10PAC48
GXPL10B_TX_CH9NAD49
GXPL10B_TX_CH9PAD50
GXPL10B_TX_CH8NAE47
GXPL10B_TX_CH8PAE48
GXPL10B_TX_CH7NAF49
GXPL10B_TX_CH7PAF50
GXPL10B_TX_CH19NP49
GXPL10B_TX_CH19PP50
GXPL10B_TX_CH18NR47
GXPL10B_TX_CH18PR48
GXPL10B_TX_CH17NT49
GXPL10B_TX_CH17PT50
GXPL10B_TX_CH16NU47
GXPL10B_TX_CH16PU48
GXPL10B_TX_CH15NV49
GXPL10B_TX_CH15PV50
GXPL10B_TX_CH14NW47
GXPL10B_TX_CH14PW48
GXPL10B_TX_CH13NY49
GXPL10B_TX_CH13PY50
R6423 100
R6418 100
R6464 169,0.1%
XCVR BANK 10AS10_DX_ND5_F2912D_EXTERNAL
U1-21
U10_P_IO_RESREF_0AN41
REFCLK_GXPL10A_CH2NAP44
REFCLK_GXPL10A_CH2PAP45
REFCLK_GXPL10A_CH0NAT44
REFCLK_GXPL10A_CH0PAT45
GXPL10A_RX_CH15NAP53
GXPL10A_RX_CH15PAP54
GXPL10A_RX_CH14NAR51
GXPL10A_RX_CH14PAR52
GXPL10A_RX_CH13NAT53
GXPL10A_RX_CH13PAT54
GXPL10A_RX_CH12NAU51
GXPL10A_RX_CH12PAU52
GXPL10A_RX_CH11NAV53
GXPL10A_RX_CH11PAV54
GXPL10A_RX_CH10NAW51
GXPL10A_RX_CH10PAW52
GXPL10A_RX_CH9NAY53
GXPL10A_RX_CH9PAY54
GXPL10A_RX_CH8NBA51
GXPL10A_RX_CH8PBA52
GXPL10A_RX_CH7NBB53
GXPL10A_RX_CH7PBB54
GXPL10A_RX_CH6NBC51
GXPL10A_RX_CH6PBC52
GXPL10A_RX_CH5NBD53
GXPL10A_RX_CH5PBD54
GXPL10A_RX_CH4NBE51
GXPL10A_RX_CH4PBE52
GXPL10A_RX_CH3NBF53
GXPL10A_RX_CH3PBF54
GXPL10A_RX_CH2NBG51
GXPL10A_RX_CH2PBG52
GXPL10A_RX_CH1NBH53
GXPL10A_RX_CH1PBH54
GXPL10A_RX_CH0NBJ51
GXPL10A_RX_CH0PBJ52
GXPL10A_TX_CH6NBC47
GXPL10A_TX_CH6PBC48
GXPL10A_TX_CH5NBD49
GXPL10A_TX_CH5PBD50
GXPL10A_TX_CH4NBE47
GXPL10A_TX_CH4PBE48
GXPL10A_TX_CH3NBF49
GXPL10A_TX_CH3PBF50
GXPL10A_TX_CH2NBG47
GXPL10A_TX_CH2PBG48
GXPL10A_TX_CH1NBH49
GXPL10A_TX_CH1PBH50
GXPL10A_TX_CH0NBJ47
GXPL10A_TX_CH0PBJ48
GXPL10A_TX_CH15NAP49
GXPL10A_TX_CH15PAP50
GXPL10A_TX_CH14NAR47
GXPL10A_TX_CH14PAR48
GXPL10A_TX_CH13NAT49
GXPL10A_TX_CH13PAT50
GXPL10A_TX_CH12NAU47
GXPL10A_TX_CH12PAU48
GXPL10A_TX_CH11NAV49
GXPL10A_TX_CH11PAV50
GXPL10A_TX_CH10NAW47
GXPL10A_TX_CH10PAW48
GXPL10A_TX_CH9NAY49
GXPL10A_TX_CH9PAY50
GXPL10A_TX_CH8NBA47
GXPL10A_TX_CH8PBA48
GXPL10A_TX_CH7NBB49
GXPL10A_TX_CH7PBB50
R6417 100
R6465 169,0.1%
R6424 100
PCIE_RX_P4PCIE_RX_N4
PCIE_RX_N5PCIE_RX_P5
PCIE_RX_N6PCIE_RX_P6
PCIE_RX_P7PCIE_RX_N7
PCIE_RX_N8PCIE_RX_P8
PCIE_RX_P9PCIE_RX_N9
PCIE_RX_P10PCIE_RX_N10
PCIE_RX_P11PCIE_RX_N11
PCIE_RX_P12PCIE_RX_N12
PCIE_RX_P13PCIE_RX_N13
PCIE_RX_N14PCIE_RX_P14
PCIE_RX_P15PCIE_RX_N15
PCIE_RX_P0PCIE_RX_N0
PCIE_RX_P1PCIE_RX_N1
PCIE_RX_P2PCIE_RX_N2
PCIE_RX_P3PCIE_RX_N3
PCIE_TX_P12PCIE_TX_N12
PCIE_TX_P13PCIE_TX_N13
PCIE_TX_P14PCIE_TX_N14
PCIE_TX_N15PCIE_TX_P15
PCIE_TX_P0PCIE_TX_N0
PCIE_TX_N1PCIE_TX_P1
PCIE_TX_P2PCIE_TX_N2
PCIE_TX_P3PCIE_TX_N3
PCIE_TX_N4PCIE_TX_P4
PCIE_TX_P5PCIE_TX_N5
PCIE_TX_P6PCIE_TX_N6
PCIE_TX_P7PCIE_TX_N7
PCIE_TX_P8PCIE_TX_N8
PCIE_TX_N9PCIE_TX_P9
PCIE_TX_P10PCIE_TX_N10
PCIE_TX_P11PCIE_TX_N11
UPI0_CPU_FPGA_DP1
UPI0_CPU_FPGA_DN0UPI0_CPU_FPGA_DP0
UPI0_CPU_FPGA_DN1
UPI0_CPU_FPGA_DP2UPI0_CPU_FPGA_DN2
UPI0_CPU_FPGA_DP4UPI0_CPU_FPGA_DN4
UPI0_CPU_FPGA_DN3
UPI0_CPU_FPGA_DN6
UPI0_CPU_FPGA_DP7
UPI0_CPU_FPGA_DN5
UPI0_CPU_FPGA_DN7
UPI0_CPU_FPGA_DP3
UPI0_CPU_FPGA_DP5
UPI0_CPU_FPGA_DP6
UPI0_CPU_FPGA_DN12
UPI0_CPU_FPGA_DN9
UPI0_CPU_FPGA_DN11
UPI0_CPU_FPGA_DN8
UPI0_CPU_FPGA_DP9
UPI0_CPU_FPGA_DP8
UPI0_CPU_FPGA_DP11
UPI0_CPU_FPGA_DP13
UPI0_CPU_FPGA_DP10UPI0_CPU_FPGA_DN10
UPI0_CPU_FPGA_DP12
UPI0_CPU_FPGA_DN13
UPI0_CPU_FPGA_DP17
UPI0_CPU_FPGA_DP14UPI0_CPU_FPGA_DN14
UPI0_CPU_FPGA_DP16UPI0_CPU_FPGA_DN16
UPI0_CPU_FPGA_DN15
UPI0_CPU_FPGA_DP18UPI0_CPU_FPGA_DN18
UPI0_CPU_FPGA_DN17
UPI0_CPU_FPGA_DN19
UPI0_CPU_FPGA_DP15
UPI0_CPU_FPGA_DP19
UPI0_FPGA_CPU_DN1UPI0_FPGA_CPU_DP1
UPI0_FPGA_CPU_DN0UPI0_FPGA_CPU_DP0
UPI0_FPGA_CPU_DN2
UPI0_FPGA_CPU_DN4
UPI0_FPGA_CPU_DN6
UPI0_FPGA_CPU_DP2
UPI0_FPGA_CPU_DP3UPI0_FPGA_CPU_DN3
UPI0_FPGA_CPU_DP5UPI0_FPGA_CPU_DN5
UPI0_FPGA_CPU_DP7UPI0_FPGA_CPU_DN7
UPI0_FPGA_CPU_DP4
UPI0_FPGA_CPU_DP6
UPI0_FPGA_CPU_DN9
UPI0_FPGA_CPU_DP11UPI0_FPGA_CPU_DN11
UPI0_FPGA_CPU_DP8
UPI0_FPGA_CPU_DN10
UPI0_FPGA_CPU_DN8
UPI0_FPGA_CPU_DN13
UPI0_FPGA_CPU_DP12UPI0_FPGA_CPU_DN12
UPI0_FPGA_CPU_DP10
UPI0_FPGA_CPU_DP9
UPI0_FPGA_CPU_DP13
UPI0_FPGA_CPU_DN14
UPI0_FPGA_CPU_DP15UPI0_FPGA_CPU_DN15
UPI0_FPGA_CPU_DN19
UPI0_FPGA_CPU_DP16UPI0_FPGA_CPU_DN16
UPI0_FPGA_CPU_DN18
UPI0_FPGA_CPU_DP14
UPI0_FPGA_CPU_DP18
UPI0_FPGA_CPU_DP17UPI0_FPGA_CPU_DN17
UPI0_FPGA_CPU_DP19
CLK_100M_UPI0_0_PCLK_100M_UPI0_0_N
CLK_100M_UPI0_1_NCLK_100M_UPI0_1_P
CLK_100M_PCIE_0_NCLK_100M_PCIE_0_P
CLK_100M_PCIE_1_NCLK_100M_PCIE_1_P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 DX Xcvr GXPR 11B, 11C
UPI_1 FPGA->CPU
UPI2 INTERFACE
UPI1 INTERFACE
UPI_2 FPGA->CPUUPI_1 CPU->FPGA UPI_2 CPU->FPGA
CLOCK
RESREF = 169 Ohm for 85 Ohm UPI/PCIe or 200 Ohm for 100 Ohm UPI/PCIe RESREF = 169 Ohm for 85 Ohm UPI/PCIe or 200 Ohm for 100 Ohm UPI/PCIe
UPI2_FPGA_CPU_DN[19:0] 27UPI2_FPGA_CPU_DP[19:0] 27
UPI2_CPU_FPGA_DN[19:0] 27UPI2_CPU_FPGA_DP[19:0] 27
UPI1_FPGA_CPU_DP[19:0] 26
UPI1_CPU_FPGA_DN[19:0] 26UPI1_CPU_FPGA_DP[19:0] 26
UPI1_FPGA_CPU_DN[19:0] 26
CLK_100M_UPI1_0_P 22CLK_100M_UPI1_0_N 22
CLK_100M_UPI1_1_N 22CLK_100M_UPI1_1_P 22
CLK_100M_UPI2_0_N 22CLK_100M_UPI2_0_P 22
CLK_100M_UPI2_1_P 22CLK_100M_UPI2_1_N 22
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
16 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
16 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
16 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R6422 100
R6463 169,0.1%
XCVR BANK 11CS10_DX_ND5_F2912D_EXTERNAL
U1-24
GXPR11C_RX_CH1PAA3 GXPR11C_RX_CH1NAA4
GXPR11C_RX_CH0PAB1
U22_P_IO_RESREF_0AB12
GXPR11C_RX_CH0NAB2
GXPR11C_RX_CH19PC3 GXPR11C_RX_CH19NC4
GXPR11C_RX_CH18PD1 GXPR11C_RX_CH18ND2
GXPR11C_RX_CH17PE3 GXPR11C_RX_CH17NE4
GXPR11C_RX_CH16PF1 GXPR11C_RX_CH16NF2
GXPR11C_RX_CH15PG3 GXPR11C_RX_CH15NG4
GXPR11C_RX_CH14PH1 GXPR11C_RX_CH14NH2
GXPR11C_RX_CH13PJ3 GXPR11C_RX_CH13NJ4
GXPR11C_RX_CH12PK1 GXPR11C_RX_CH12NK2
GXPR11C_RX_CH11PL3 GXPR11C_RX_CH11NL4
GXPR11C_RX_CH10PM1 GXPR11C_RX_CH10NM2
GXPR11C_RX_CH9PN3 GXPR11C_RX_CH9NN4
GXPR11C_RX_CH8PP1 GXPR11C_RX_CH8NP2
GXPR11C_RX_CH7PR3 GXPR11C_RX_CH7NR4
GXPR11C_RX_CH6PT1
REFCLK_GXPR11C_CH2PT10 REFCLK_GXPR11C_CH2NT11
GXPR11C_RX_CH6NT2
GXPR11C_RX_CH5PU3 GXPR11C_RX_CH5NU4
GXPR11C_RX_CH4PV1
REFCLK_GXPR11C_CH0PV10 REFCLK_GXPR11C_CH0NV11
GXPR11C_RX_CH4NV2
GXPR11C_RX_CH3PW3 GXPR11C_RX_CH3NW4
GXPR11C_RX_CH2PY1 GXPR11C_RX_CH2NY2
GXPR11C_TX_CH0PAA7GXPR11C_TX_CH0NAA8
GXPR11C_TX_CH19PB5GXPR11C_TX_CH19NB6
GXPR11C_TX_CH18PC7GXPR11C_TX_CH18NC8
GXPR11C_TX_CH17PD5GXPR11C_TX_CH17ND6
GXPR11C_TX_CH16PE7GXPR11C_TX_CH16NE8
GXPR11C_TX_CH15PF5GXPR11C_TX_CH15NF6
GXPR11C_TX_CH14PG7GXPR11C_TX_CH14NG8
GXPR11C_TX_CH13PH5GXPR11C_TX_CH13NH6
GXPR11C_TX_CH12PJ7GXPR11C_TX_CH12NJ8
GXPR11C_TX_CH11PK5GXPR11C_TX_CH11NK6
GXPR11C_TX_CH10PL7GXPR11C_TX_CH10NL8
GXPR11C_TX_CH9PM5GXPR11C_TX_CH9NM6
GXPR11C_TX_CH8PN7GXPR11C_TX_CH8NN8
GXPR11C_TX_CH7PP5GXPR11C_TX_CH7NP6
GXPR11C_TX_CH6PR7GXPR11C_TX_CH6NR8
GXPR11C_TX_CH5PT5GXPR11C_TX_CH5NT6
GXPR11C_TX_CH4PU7GXPR11C_TX_CH4NU8
GXPR11C_TX_CH3PV5GXPR11C_TX_CH3NV6
GXPR11C_TX_CH2PW7GXPR11C_TX_CH2NW8
GXPR11C_TX_CH1PY5GXPR11C_TX_CH1NY6
R6420 100
R6419 100
R6462 169,0.1%
XCVR BANK 11BS10_DX_ND5_F2912D_EXTERNAL
U1-23
GXPR11B_RX_CH19PAC3 GXPR11B_RX_CH19NAC4
GXPR11B_RX_CH18PAD1 GXPR11B_RX_CH18NAD2
GXPR11B_RX_CH17PAE3 GXPR11B_RX_CH17NAE4
GXPR11B_RX_CH16PAF1
REFCLK_GXPR11B_CH2PAF10 REFCLK_GXPR11B_CH2NAF11
GXPR11B_RX_CH16NAF2
GXPR11B_RX_CH15PAG3 GXPR11B_RX_CH15NAG4
GXPR11B_RX_CH14PAH1
REFCLK_GXPR11B_CH0PAH10 REFCLK_GXPR11B_CH0NAH11
GXPR11B_RX_CH14NAH2
GXPR11B_RX_CH13PAJ3 GXPR11B_RX_CH13NAJ4
GXPR11B_RX_CH12PAK1 GXPR11B_RX_CH12NAK2
U21_P_IO_RESREF_0AL14
GXPR11B_RX_CH11PAL3 GXPR11B_RX_CH11NAL4
GXPR11B_RX_CH10PAM1 GXPR11B_RX_CH10NAM2
GXPR11B_RX_CH9PAN3 GXPR11B_RX_CH9NAN4
GXPR11B_RX_CH8PAP1 GXPR11B_RX_CH8NAP2
GXPR11B_RX_CH7PAR3 GXPR11B_RX_CH7NAR4
GXPR11B_RX_CH6PAT1 GXPR11B_RX_CH6NAT2
GXPR11B_RX_CH5PAU3 GXPR11B_RX_CH5NAU4
GXPR11B_RX_CH4PAV1 GXPR11B_RX_CH4NAV2
GXPR11B_RX_CH3PAW3 GXPR11B_RX_CH3NAW4
GXPR11B_RX_CH2PAY1 GXPR11B_RX_CH2NAY2
GXPR11B_RX_CH1PBA3 GXPR11B_RX_CH1NBA4
GXPR11B_RX_CH0PBB1 GXPR11B_RX_CH0NBB2
GXPR11B_TX_CH19PAB5GXPR11B_TX_CH19NAB6
GXPR11B_TX_CH18PAC7GXPR11B_TX_CH18NAC8
GXPR11B_TX_CH17PAD5GXPR11B_TX_CH17NAD6
GXPR11B_TX_CH16PAE7GXPR11B_TX_CH16NAE8
GXPR11B_TX_CH15PAF5GXPR11B_TX_CH15NAF6
GXPR11B_TX_CH14PAG7GXPR11B_TX_CH14NAG8
GXPR11B_TX_CH13PAH5GXPR11B_TX_CH13NAH6
GXPR11B_TX_CH12PAJ7GXPR11B_TX_CH12NAJ8
GXPR11B_TX_CH11PAK5GXPR11B_TX_CH11NAK6
GXPR11B_TX_CH10PAL7GXPR11B_TX_CH10NAL8
GXPR11B_TX_CH9PAM5GXPR11B_TX_CH9NAM6
GXPR11B_TX_CH8PAN7GXPR11B_TX_CH8NAN8
GXPR11B_TX_CH7PAP5GXPR11B_TX_CH7NAP6
GXPR11B_TX_CH6PAR7GXPR11B_TX_CH6NAR8
GXPR11B_TX_CH5PAT5GXPR11B_TX_CH5NAT6
GXPR11B_TX_CH4PAU7GXPR11B_TX_CH4NAU8
GXPR11B_TX_CH3PAV5GXPR11B_TX_CH3NAV6
GXPR11B_TX_CH2PAW7GXPR11B_TX_CH2NAW8
GXPR11B_TX_CH1PAY5GXPR11B_TX_CH1NAY6
GXPR11B_TX_CH0PBA7GXPR11B_TX_CH0NBA8
R6421 100
UPI1_FPGA_CPU_DN0UPI1_FPGA_CPU_DP0
UPI1_FPGA_CPU_DP1UPI1_FPGA_CPU_DN1
UPI1_FPGA_CPU_DN2UPI1_FPGA_CPU_DP2
UPI1_FPGA_CPU_DN3
UPI1_FPGA_CPU_DP4
UPI1_FPGA_CPU_DP3
UPI1_FPGA_CPU_DN4
UPI1_FPGA_CPU_DN5UPI1_FPGA_CPU_DP5
UPI1_FPGA_CPU_DN6UPI1_FPGA_CPU_DP6
UPI1_FPGA_CPU_DN7UPI1_FPGA_CPU_DP7
UPI1_FPGA_CPU_DN8UPI1_FPGA_CPU_DP8
UPI1_FPGA_CPU_DN9UPI1_FPGA_CPU_DP9
UPI1_FPGA_CPU_DN10UPI1_FPGA_CPU_DP10
UPI1_FPGA_CPU_DN11UPI1_FPGA_CPU_DP11
UPI1_FPGA_CPU_DN12UPI1_FPGA_CPU_DP12
UPI1_FPGA_CPU_DN13UPI1_FPGA_CPU_DP13
UPI1_FPGA_CPU_DP18UPI1_FPGA_CPU_DN18
UPI1_FPGA_CPU_DP19UPI1_FPGA_CPU_DN19
UPI1_FPGA_CPU_DP14UPI1_FPGA_CPU_DN14
UPI1_FPGA_CPU_DN16
UPI1_FPGA_CPU_DP15UPI1_FPGA_CPU_DN15
UPI1_FPGA_CPU_DP17UPI1_FPGA_CPU_DN17
UPI1_FPGA_CPU_DP16
UPI1_CPU_FPGA_DN1UPI1_CPU_FPGA_DP1
UPI1_CPU_FPGA_DP0UPI1_CPU_FPGA_DN0
UPI1_CPU_FPGA_DN4
UPI1_CPU_FPGA_DN2UPI1_CPU_FPGA_DP2
UPI1_CPU_FPGA_DP5
UPI1_CPU_FPGA_DN3UPI1_CPU_FPGA_DP3
UPI1_CPU_FPGA_DP4
UPI1_CPU_FPGA_DN5
UPI1_CPU_FPGA_DN6UPI1_CPU_FPGA_DP6
UPI1_CPU_FPGA_DN7UPI1_CPU_FPGA_DP7
UPI1_CPU_FPGA_DN8UPI1_CPU_FPGA_DP8
UPI1_CPU_FPGA_DN9UPI1_CPU_FPGA_DP9
UPI1_CPU_FPGA_DN10UPI1_CPU_FPGA_DP10
UPI1_CPU_FPGA_DN11UPI1_CPU_FPGA_DP11
UPI1_CPU_FPGA_DN12UPI1_CPU_FPGA_DP12
UPI1_CPU_FPGA_DN13UPI1_CPU_FPGA_DP13
UPI1_CPU_FPGA_DP18
UPI1_CPU_FPGA_DP19
UPI1_CPU_FPGA_DP17
UPI1_CPU_FPGA_DN18
UPI1_CPU_FPGA_DN19
UPI1_CPU_FPGA_DN14UPI1_CPU_FPGA_DP14
UPI1_CPU_FPGA_DN17
UPI1_CPU_FPGA_DN15UPI1_CPU_FPGA_DP15
UPI1_CPU_FPGA_DN16UPI1_CPU_FPGA_DP16
UPI2_FPGA_CPU_DN0
UPI2_FPGA_CPU_DP1UPI2_FPGA_CPU_DN1
UPI2_FPGA_CPU_DP0
UPI2_FPGA_CPU_DN2
UPI2_FPGA_CPU_DN3UPI2_FPGA_CPU_DP3
UPI2_FPGA_CPU_DP2
UPI2_FPGA_CPU_DN6
UPI2_FPGA_CPU_DN4UPI2_FPGA_CPU_DP4
UPI2_FPGA_CPU_DN7UPI2_FPGA_CPU_DP7
UPI2_FPGA_CPU_DN5UPI2_FPGA_CPU_DP5
UPI2_FPGA_CPU_DP6
UPI2_FPGA_CPU_DN8
UPI2_FPGA_CPU_DN10
UPI2_FPGA_CPU_DP8
UPI2_FPGA_CPU_DN11UPI2_FPGA_CPU_DP11
UPI2_FPGA_CPU_DN9UPI2_FPGA_CPU_DP9
UPI2_FPGA_CPU_DP10
UPI2_FPGA_CPU_DN12UPI2_FPGA_CPU_DP12
UPI2_FPGA_CPU_DN13UPI2_FPGA_CPU_DP13
UPI2_FPGA_CPU_DN15UPI2_FPGA_CPU_DP15
UPI2_FPGA_CPU_DN14UPI2_FPGA_CPU_DP14
UPI2_FPGA_CPU_DN18
UPI2_FPGA_CPU_DN16UPI2_FPGA_CPU_DP16
UPI2_FPGA_CPU_DN19UPI2_FPGA_CPU_DP19
UPI2_FPGA_CPU_DN17UPI2_FPGA_CPU_DP17
UPI2_FPGA_CPU_DP18
UPI2_CPU_FPGA_DP0UPI2_CPU_FPGA_DN0
UPI2_CPU_FPGA_DP1UPI2_CPU_FPGA_DN1
UPI2_CPU_FPGA_DN3
UPI2_CPU_FPGA_DN4UPI2_CPU_FPGA_DP4
UPI2_CPU_FPGA_DN2UPI2_CPU_FPGA_DP2
UPI2_CPU_FPGA_DP5
UPI2_CPU_FPGA_DP3
UPI2_CPU_FPGA_DN7
UPI2_CPU_FPGA_DN5
UPI2_CPU_FPGA_DP7
UPI2_CPU_FPGA_DN6UPI2_CPU_FPGA_DP6
UPI2_CPU_FPGA_DP8
UPI2_CPU_FPGA_DP9
UPI2_CPU_FPGA_DN8
UPI2_CPU_FPGA_DN11
UPI2_CPU_FPGA_DN9
UPI2_CPU_FPGA_DN12UPI2_CPU_FPGA_DP12
UPI2_CPU_FPGA_DN10UPI2_CPU_FPGA_DP10
UPI2_CPU_FPGA_DP13
UPI2_CPU_FPGA_DP11
UPI2_CPU_FPGA_DN13
UPI2_CPU_FPGA_DN15
UPI2_CPU_FPGA_DN16UPI2_CPU_FPGA_DP16
UPI2_CPU_FPGA_DN14UPI2_CPU_FPGA_DP14
UPI2_CPU_FPGA_DP17
UPI2_CPU_FPGA_DP15
UPI2_CPU_FPGA_DN19
UPI2_CPU_FPGA_DN17
UPI2_CPU_FPGA_DN18UPI2_CPU_FPGA_DP18
UPI2_CPU_FPGA_DP19
CLK_100M_UPI1_0_NCLK_100M_UPI1_0_P
CLK_100M_UPI1_1_PCLK_100M_UPI1_1_N
CLK_100M_UPI2_0_PCLK_100M_UPI2_0_N
CLK_100M_UPI2_1_NCLK_100M_UPI2_1_P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 DX Bank WHR
UPI_MODE 10_P
NODE_ID_010
NODE_ID_110
U21_NODE_ID_021
U21_NODE_ID_121
UPI_MODE 21_P
UPI_MODE 11_P
U21_NODE_ID_111
U21_NODE_ID_011
UPI_MODE 22_P
U21_NODE_ID_022
U21_NODE_ID_012
Level Shifter
CPU_ID[0]
CPU_ID[1]
P-Tile UPIx
S_STRAP
ID_0
ID_1
UPI_MODE
UPIx Connector
Pulled down = 2 CPU sockets
Pulled up = 4 CPU sockets
FPGA
Block 3LGPIO
GPIO
1.8V3.3V
1.8V
1.8V
S10_UPI2_NID0_1V8 12,68S10_UPI2_NID1_1V8 12,68
S10_UPI1_NID0_1V8 12,68S10_UPI1_NID1_1V8 12,68
PCIE_Ep 68UPI0_Ep 68UPI1_Ep 68UPI2_Ep 68
DIODEH 33DIODEL 33
S10_UPI0_NID0_1V8 12,68S10_UPI0_NID1_1V8 12,68
UPI_MODE 23
UPI_MODE_3L 12
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
17 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
17 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
17 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R64692.00K
U1-35
S10_DX_ND5_F2912D_EXTERNAL
DNU119AA10
DNU49AA39
DNU50AA40
DNU68AA41 DNU67AA42
DNU64AA44 DNU63AA45
DNU116AB10
DNU99AB18
DNU47AB38
DNU48AB39
DNU45AB40
DNU69AB42
DNU70AB43
DNU65AB44
DNU66AB45
DNU113AC10
DNU115AC11
DNU85AC12
DNU103AC16DNU102AC17
DNU100AC18
DNU40AC38
DNU42AC39
DNU46AC44
DNU44AC45
DNU117AD10
DNU121AD11
DNU108AD17
DNU97AD18
DNU39AD38
DNU43AD44
DNU95AE18
DNU101AF17
DNU38AF38
DNU96AG18
DNU98AH17
DNU93AH18
DNU41AH38
DNU94AJ18
DNU82AK10
DNU83AK11
DNU91AK17
DNU92AK18
DNU81AL10
DNU18AL44
DNU19AL45
DNU89AM18
DNU10AM40
DNU21AM44 DNU20AM45
DNU84AN11
DNU90AN18
DNU80AP10
DNU17AP38 DNU16AT38 DNU15AV38
DNU25AV45
DNU30AW44
DNU24AW45 DNU23AY44
DNU29AY45
DNU14BA41
DNU22BA44
DNU28BA45
DNU11BB37
DNU13BB38
DNU37BB43 DNU36BB44
DNU27BB45
DNU9BC38
DNU5BC41
DNU35BC43
DNU26BC45
DNU12BD38
DNU7BD39 DNU6BD40
DNU8BD41
DNU34BD43 DNU33BD44 DNU32BD45
DNU112T20DNU111U18DNU110U19DNU109U20
DNU107V17DNU106V18DNU105W18
DNU54W39 DNU53W40
DNU56W41 DNU55W43
DNU57W44
DNU58W45
DNU104Y18
DNU52Y38 DNU51Y39
DNU60Y41 DNU59Y42
DNU62Y43 DNU61Y44
DNU86AM11
DNU87AN10
DNU88AP11
DNU72AR17
DNU73BA10
DNU74BB10
DNU75BB40
DNU76BC40
DNU149BM32
DNU71BN2
DNU148BN32
DNU145L10
DNU138L11
DNU126L12
DNU124L14
DNU142L15
DNU140L16
DNU141L17
DNU77L19
DNU144M10
DNU127M12
DNU125M13
DNU139M14
DNU143M15
DNU122M17
DNU128M18
DNU78M19
DNU131N12
DNU123N14
DNU129N16
DNU130N17
DNU136N18
DNU137P18
DNU79P19
DNU147P29
DNU134R18
DNU135R19
DNU146R29
DNU133T17DNU132T19
DNU120Y10
DNU114Y11
DNU118A3
DNU31AV44
I_PIN_PERST_N10_PBB39
I_PIN_PERST_N11_PAD45
I_PIN_PERST_N22_PAA11I_PIN_PERST_N21_PAL11
IO_AUX_RREF21_PAP18
IO_AUX_RREF22_PY17
IO_AUX_RREF20AU17
IO_AUX_RREF10_PAY38
IO_AUX_RREF11_PAK38
R64662.00K
R6716DNI04021%
R64672.00K
R64702.00K
R67210
R67190
R64682.00K
R67200
R6655
10.0K
R67180
R6656
10.0K
UPI0_EpUPI1_EpUPI2_Ep
PCIE_Ep
DIODEHDIODEL
UPI_MODE
S10_UPI1_NID0_1V8S10_UPI1_NID1_1V8
UPI_MODE
S10_UPI0_NID0_1V8S10_UPI0_NID1_1V8
UPI_MODE
S10_UPI2_NID0_1V8S10_UPI2_NID1_1V8
UPI_MODE_3L
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB_PHY_RESETn MAX811PWR-ON RESET
U24
USB PHYU26
Si5391A ClocksU9
CLK0_RSTn
ANDGate
U5
PCIE_3V3_BMC_RST_N
MAX6817
U118
PCIE_3V3_BMC_PERST_NSW_PERSTn
Reset Tree
FX2_RESETn
MAX10
Max_RESETn
S10 DXU1_1
CPU_RESETn
Total Memory 8GB
DDR4512Mbx16
DDR4512Mbx16
DDR4512Mbx16
DDR4
512Mbx16
DDR4512Mx16 X5
DDR4_CH0
DDR4_CH0_RESETn
Total Memory 8GB
DDR4512Mbx16
DDR4512Mbx16
DDR4512Mbx16
DDR4512Mbx16
DDR4512Mx16 X5
DDR4_CH1
DDR4_CH1_RESETn
QSPI FlashU66
QSPI_M10_RESETnPCIE_EDGE_PERSTn PCIE_RERSTn
PCIE_EP
PCIE_Rp_IO
PCIE_EPRP_SEL
SW27
UPI0_PERSTn_SELSW16
1.8V
3 .3V S10_UPI0_PERSTn_SEL
UPI0 (FPGA-CPU) J55
UPI0_EP
UPI0_RP_IO
UPI0_EPRP_SEL
SW24
UPI1_PERSTn_SELSW17
1.8V
3.3V
UPI1_EP
UPI1_RP_IO
UPI1_EPRP_SEL
SW25
UPI2_PERSTn_SEL SW18
1.8V
3.3V
UPI2_EP
UPI2_RP_IO
UPI2_EPRP_SEL
SW26
1.8V
U211
U205
U206
U207
U195
U196
U197
UPI1 (FPGA-CPU) J38
UPI2 (FPGA-CPU) J39
U210
SW28
PCIE_Edge_EPRP_SEL
Ep
Rp
PCIE_Rp_Io_3V3PCIE_Rp_IO
Ep
Rp
PCIe Gold Finger
S10_UPI0_PERSTn_SEL
S10_UPI1_PERSTn_SEL
S10_UPI2_PERSTn_SEL
UPI2_PERSTn
UPI1_PERSTn
UPI0_PERSTn
I_PIN_PERST_N10_P
I_PIN_PERST_N11_P
I_PIN_PERST_N21_P
I_PIN_PERST_N22_P
IO_3L
IO_3LIO_3L
IO_3L
IO_3L
IO_3LUPI2_Ep_IO
UPI1_Ep_IO
UPI0_Ep_IOIO_3L
IO_3L
IO_3L
IO_3L
IO_3L
S10 DXU1_2
Level shifter
U50
QSFP
CTRL
QSFP _1 J15
QSFP _2 J18
ZQSFP1_3V3_RESET_L
ZQSFP2_3V3_RESET_L
I2C2
A0
A0
A0
A0
A0
A0
A0
A1
A1
A1
A1
A1
A1
A1
Default : High , select A1
Default : High , select A1
Default : High , select A1
A0
A1
Default : Low , select A0
Default : Low , select A0
IO_3LPCIE_Ep_IO
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
18 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
18 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
18 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 DX Power
Thermal
0p9V
S10_VCC S10_VCC
S10_VCCPLLDIG_SDM VCCFUSEWR_SDM
S10_VCC
S10_VCC S10_VCC S10_G2_1.8V
1.8V
1V2_DDR4_CH00
1.8V
1V2_DDR4_CH00
1.8V
1V2_DDR4_CH11
1.8V
1.8V
1V2_DDR4_CH11
1.8V
S10_VCCPLLDIG_SDM
S10_G2_1.8V_FLT
S10_G2_1.8V_FLT
S10_G2_1.8V
0V6_DDR4_VREF_CH11
S10_VCCH_GXP
S10_VCCCLK_GXP
S10_VCCH_GXE
S10_VCCH_GXP
S10_VCCCLK_GXE
S10_FUSE_GXP
VCCRTPLL_GXE
S10_VCCRT_GXP
S10_VCCRT_GXE
VCCFUSEWR_SDM
S10_VCCRT_GXP
S10_VCCRT_GXE
S10_VCCRT_GXP
S10_FUSE_GXP
0V6_DDR4_VREF_CH00
S10_VCCH_GXP
S10_VCCH_GXP
S10_VCCRT_GXP
S10_VCCRT_GXP
S10_VCCRT_GXP
S10_G2_1.8V_FLT
S10_VCC_SENSE 58S10_VSS_SENSE 58
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
19 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
19 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
19 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
MH7MH_PTH_4P2_8MM
1
S10_DX_ND5_F2912D_EXTERNAL
U1-26
VCCAR33
VCCAR34
VCCAR36
VCCAT20
VCCAT24
VCCAT25
VCCAU22
VCCAU23
VCCW23
VCCW24
VCCY21
VCCY26
VCCAR23
VCCAR24
VCCAR26
VCCAR27
VCCAR28
VCCAR29
VCCAR31
VCCAR32
VCCAT21
VCCAT22
VCCAT26
VCCAT27
VCCAT29
VCCAT30
VCCAT31
VCCAT32
VCCAT34
VCCAT35
VCCAT36
VCCAU20
VCCAU24
VCCAU25
VCCAU27
VCCAU28
VCCAU29
VCCAU30
VCCAU32
VCCAU33
VCCAU34
VCCAU35
VCCAV27
VCCAV28
VCCAV30
VCCV27
VCCV28
VCCV30
VCCW21
VCCW25
VCCW26
VCCW28
VCCW29
VCCW30
VCCW31
VCCW33
VCCW34
VCCW35
VCCW36
VCCY27
VCCY28
VCCY29
VCCY34
VCCY36
VCCAG33
VCCAG34
VCCAH20
VCCAP29
VCCAP30
VCCAP35
VCCAG30
VCCAG32
VCCAG35
VCCAH21
VCCAH22
VCCAH23
VCCAH32
VCCAH33
VCCAH35
VCCAH36
VCCAJ20
VCCAJ21
VCCAJ24
VCCAJ25
VCCAJ26
VCCAJ28
VCCAJ29
VCCAJ30
VCCAJ31
VCCAJ34
VCCAJ35
VCCAJ36
VCCAK21
VCCAK24
VCCAK26
VCCAK27
VCCAK28
VCCAK29
VCCAK31
VCCAK34
VCCAK36
VCCAL20
VCCAL21
VCCAL22
VCCAL24
VCCAL25
VCCAL26
VCCAL27
VCCAL29
VCCAL30
VCCAL31
VCCAL32
VCCAL34
VCCAL35
VCCAL36
VCCAM20
VCCAM22
VCCAM34
VCCAM35
VCCAN20
VCCAN21
VCCAN35
VCCAN36
VCCAP20
VCCAP21
VCCAP24
VCCAP25
VCCAP26
VCCAP28
VCCAP31
VCCAP34
VCCAP36
VCCAR21
VCCAR22
GNDSENSEAH27 VCCLSENSEAH28
C534
1uF
0201
C824
4.7uF
0603
S10_DX_ND5_F2912D_EXTERNAL
U1-27
VCCPTAA24
VCCPTAA25
VCCPTAA26
VCCPTAA27
VCCPTAA29
VCCPTAA30
VCCPTAA31
VCCPTAB23
VCCPTAB24
VCCPTAB25
VCCPTAB27
VCCPTAB28
VCCPTAB29
VCCPTAB30
VCCPTAB32
VCCPTAM23
VCCPTAM24
VCCPTAM25
VCCPTAM27
VCCPTAM28
VCCPTAM29
VCCPTAM30
VCCPTAM32
VCCPTAM33
VCCPTAN25
VCCPTAN26
VCCPTAN27
VCCPTAN28
VCCPTAN30
VCCPTAN31
VCCPLL_SDMAW25
VCCPLLDIG_SDMAW26
VCCIO_SDMAY26
VREFB3CN0BB17
VREFB3DN0BC13
VREFB2BN0BC37
VREFB3AN0BD24
VREFB2CN0BD35
VREFB3BN0BE22
VREFB2FN0BE32
VREFB2AN0BE44
VREFB3IN0L20
VREFB3JN0L21
VREFB2IN0R32
VREFB3KN0T26
VREFB3HN0T31
VREFB2JN0T34
VREFB2KN0T45
VREFB3LN0U29
VREFB2NN0U38
VREFB2LN0U43
VREFB2MN0V41
VCCIO3BAW21
VCCIO3AAW23
VCCIO2FAW28
VCCIO2FAW29
VCCIO2CAW30
VCCIO2CAW31
VCCIO2BAW33
VCCIO3BAY21
VCCIO3AAY22
VCCIO3AAY23
VCCIO2FAY28
VCCIO2CAY31
VCCIO2BAY32
VCCIO2BAY33
VCCIO3CBA19
VCCIO3BBA21
VCCIO3DBB14
VCCIO3DBB15
VCCIO3CBB18
VCCIO3CBB19
VCCIO3DBC15
VCCIO2ABE38
VCCIO2ABE39
VCCIO2ABE41
VCCIO3IM20
VCCIO3IN20
VCCIO3IP20
VCCIO3JT21
VCCIO3JT22
VCCIO3LT27
VCCIO3HT29
VCCIO3HT30
VCCIO2IT32
VCCIO2JT35
VCCIO2NT36
VCCIO2NT37
VCCIO3JU22
VCCIO3KU23
VCCIO3KU24
VCCIO3KU25
VCCIO3LU27VCCIO3LU28
VCCIO3HU30
VCCIO2IU32
VCCIO2IU33
VCCIO2JU34
VCCIO2JU35
VCCIO2NU37
VCCIO2MU39
VCCIO2LU42
VCCIO2KU44
VCCIO2KU45
VCCIO2MV38
VCCIO2LV42
VCCIO2LV43
VCCIO2KV45
VCCIO2MW38
C809
4.7uF
0603
S10_DX_ND5_F2912D_EXTERNAL
U1-29
VCCH_GXER1AN16
VCCH_GXER1AP16
VCCH_GXER1AT16
VCCH_GXER1AV16
VCCH_GXER1AW16
VCCH_GXPL1AP40VCCH_GXPL1AR39VCCH_GXPL1AT40VCCH_GXPL1AU39VCCH_GXPL1AV40VCCH_GXPL1AW39VCCH_GXPL1AY40
VCCH_GXPL2AD40VCCH_GXPL2AE39VCCH_GXPL2AF40VCCH_GXPL2AG39VCCH_GXPL2AH40VCCH_GXPL2AJ39VCCH_GXPL2AK40
VCCH_GXPR2AD15
VCCH_GXPR2AE16
VCCH_GXPR2AF15
VCCH_GXPR2AG16
VCCH_GXPR2AH15
VCCH_GXPR2AJ16
VCCH_GXPR2AK15
VCCH_GXPR3P15
VCCH_GXPR3R16
VCCH_GXPR3T15
VCCH_GXPR3U16
VCCH_GXPR3V15
VCCH_GXPR3W16
VCCH_GXPR3Y15
C859 0.1uF, DNI0402
C535
1uF
0201
MH5MH_PTH_4P2_8MM
1
C839
1uF
0402
MH2MH_PTH_3P18_6P5MM
1
MH3MH_PTH_3P18_6P5MM
1
R5371 0
MH1MH_PTH_3P18_6P5MM
1
MH6MH_PTH_4P2_8MM
1
S10_DX_ND5_F2912D_EXTERNAL
U1-28
VCCAC21
VCCAC22
VCCAC23
VCCAC25
VCCAC28
VCCAC30
VCCAD28
VCCAD29
VCCAF24
VCCAF25
VCCAG22
VCCAG23
VCCAA20
VCCAA21
VCCAA22
VCCAA32
VCCAA34
VCCAA35
VCCAA36
VCCAB20
VCCAB22
VCCAB33
VCCAB34
VCCAB35
VCCAC20
VCCAC26
VCCAC27
VCCAC31
VCCAC32
VCCAC33
VCCAC35
VCCAC36
VCCAD20
VCCAD21
VCCAD24
VCCAD25
VCCAD26
VCCAD30
VCCAD31
VCCAD34
VCCAD35
VCCAD36
VCCAE21
VCCAE24
VCCAE26
VCCAE27
VCCAE28
VCCAE29
VCCAE31
VCCAE34
VCCAE36
VCCAF20
VCCAF21
VCCAF22
VCCAF26
VCCAF27
VCCAF29
VCCAF30
VCCAF31
VCCAF32
VCCAF34
VCCAF35
VCCAF36
VCCAG20
VCCAG24
VCCAG25
VCCAG27
VCCAG28
VCCAG29
VCCPAD23VCCPAE23
VCCCLK_GXPR3AA16VCCCLK_GXPR3AA17
VCCPAD33
VCCPAE22
VCCPAE32
VCCPAE33
VCCPAJ23
VCCPAJ33
VCCPAK22
VCCPAK23
VCCPAK32
VCCPAK33
VCCCLK_GXPR2AL16VCCCLK_GXPR2AL17
VCCCLK_GXPL2AL39VCCCLK_GXPL2AM38
VCCPAN22
VCCPAN23
VCCPAN32
VCCPAN33
VCCPAP23
VCCPAP33
VCCCLK_GXER1AW18
VCCCLK_GXPL1BA38VCCCLK_GXPL1BA39
VCCPY22
VCCPY23
VCCPY24
VCCPY31
VCCPY32
VCCPY33
C536
1uF
0201
R5364
0, DNI
MH4MH_PTH_3P18_6P5MM
1
C533
1uF
0201
S10_DX_ND5_F2912D_EXTERNAL
U1-25
VCCERAMAA19
VCCERAMAA37
VCCERAMAB19
VCCERAMAB37
VCCERAMAC37
VCCERAMAD19
VCCERAMAE19
VCCERAMAE37
VCCERAMAF19
VCCERAMAF37
VCCERAMAG19
VCCERAMAG37
VCCA_PLLAH25
VCCA_PLLAH26
VCCA_PLLAH30
VCCA_PLLAH31
VCCERAMAH37
VCCERAMAJ19
VCCERAMAK19
VCCERAMAK37
VCCERAMAL19
VCCERAMAL37
VCCERAMAM19
VCCERAMAM37
VCCERAMAN37
VCCERAMAP19
VCCERAMAR18
VCCERAMAR19
VCCERAMAR37
VCCERAMAT19
VCCERAMAT37
VCCERAMAU19
VCCERAMAU37
VCCERAMAV18
VCCERAMAV20
VCCERAMAV21
VCCERAMAV22
VCCERAMAV23
VCCERAMAV25
VCCERAMAV26
VCCERAMAV31
VCCERAMAV32
VCCERAMAV33
VCCERAMAV35
VCCERAMAV36
VCCERAMAV37
VCCERAMAW19
VCCERAMAW20
VCCERAMAY18
VCCERAMAY19
VCCBATBA25
VCCADCBA26
VCCERAMV20
VCCERAMV21
VCCERAMV22
VCCERAMV23
VCCERAMV25
VCCERAMV26
VCCERAMV31
VCCERAMV32
VCCERAMV33
VCCERAMV35
VCCERAMV36
VCCERAMV37
VCCERAMW19
VCCERAMW20
VCCERAMY19
VCCERAMY37
VCCFUSE_GXPAB15VCCFUSE_GXPAC14VCCFUSE_GXPAM39VCCFUSE_GXPAN39
GND_BB11BB11VCCRT_GXER1BB12
VCCRT_GXPL1BB42
GND_BC42BC42
VCCRT_GXPR3P10
GND_P11P11
VCCERAMAU18
VCCRT_GXPR2AD13
VCCRT_GXPL2AD42
VCCRT_GXPR2AE13
VCCRT_GXPR2AE14
VCCRT_GXPL2AE41
VCCRT_GXPL2AE42
VCCRT_GXPR2AF13
VCCRT_GXPL2AF42
VCCRT_GXPR2AG13
VCCRT_GXPR2AG14
VCCRT_GXPL2AG41
VCCRT_GXPL2AG42
VCCRT_GXPR2AH13
VCCRT_GXPL2AH42
VCCRT_GXPR2AJ13
VCCRT_GXPR2AJ14
VCCRT_GXPL2AJ41
VCCRT_GXPL2AJ42
VCCRT_GXPR2AK13
VCCRT_GXPL2AK42
VCCRT_GXER1AN13
VCCRT_GXER1AP13
VCCRT_GXER1AP14
VCCRT_GXPL1AP42
VCCRT_GXER1AR13
VCCRTPLL_GXER1AR15
VCCRT_GXPL1AR41
VCCRT_GXPL1AR42
VCCRT_GXER1AT13
VCCRT_GXER1AT14
VCCRT_GXPL1AT42
VCCRT_GXER1AU13
VCCRTPLL_GXER1AU15
VCCRT_GXPL1AU41
VCCRT_GXPL1AU42
VCCRT_GXER1AV13
VCCRT_GXER1AV14
VCCRT_GXPL1AV42
VCCRT_GXER1AW13
VCCRT_GXER1AW14
VCCRT_GXPL1AW41
VCCRT_GXPL1AW42
VCCRT_GXER1AY13
VCCRT_GXER1AY14
VCCFUSEWR_SDMAY27
VCCRT_GXPL1AY42
VCCRT_GXPR3P13
VCCRT_GXPR3R13
VCCRT_GXPR3R14
VCCRT_GXPR3T13
VCCRT_GXPR3U13
VCCRT_GXPR3U14
VCCRT_GXPR3V13
VCCRT_GXPR3W13
VCCRT_GXPR3W14
VCCRT_GXPR3Y13
VCCRT_GXER1AN14
C537
1uF
0201
R618
0, DNI
MH8MH_PTH_4P2_8MM
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 DX Ground
S10_TEMPDIODE0_P33S10_TEMPDIODE0_N33
S10_TEMPDIODE1_P33S10_TEMPDIODE1_N33
S10_TEMPDIODE2_P33S10_TEMPDIODE2_N33
S10_TEMPDIODE4_P33S10_TEMPDIODE4_N33
S10_TEMPDIODE5_P33S10_TEMPDIODE5_N33
S10_TEMPDIODE6_P33S10_TEMPDIODE6_N33
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
20 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
20 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
20 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
S10_DX_ND5_F2912D_EXTERNAL
U1-32
GND_T52T52
GND_T7T7
GND_T8T8
GND_T9T9
GND_U1U1
GND_U10U10
GND_U11U11
GND_U12U12
GND_U15U15
GND_U17U17
GND_U2U2
GND_U21U21
GND_U26U26
GND_U31U31
GND_U36U36
GND_U41U41
GND_U46U46
GND_U49U49
GND_U5U5
GND_U50U50
GND_U53U53
GND_U54U54
GND_U6U6
GND_U9U9
GND_V12V12
GND_V14V14
GND_V16V16
GND_V19V19
GND_V24V24
GND_V29V29
GND_V3V3
GND_V34V34
GND_V39V39
GND_V4V4
GND_V44V44
GND_V46V46
GND_V47V47
GND_V48V48
GND_V51V51
GND_V52V52
GND_V7V7
GND_V8V8
GND_V9V9
GND_W1W1
GND_W10W10
GND_W11W11
GND_W12W12
GND_W15W15
GND_W17W17
GND_W2W2
GND_W22W22
GND_W27W27
GND_W32W32
GND_W37W37
GND_W42W42
GND_W46W46
GND_W49W49
GND_W5W5
GND_W50W50
GND_W53W53
GND_W54W54
GND_W6W6
GND_W9W9
GND_Y12Y12
GND_Y14Y14
GND_Y16Y16
GND_Y20Y20
GND_Y25Y25
GND_Y3Y3
GND_Y30Y30
GND_Y35Y35
GND_Y4Y4
GND_Y40Y40
GND_Y45Y45
GND_Y46Y46
GND_Y47Y47
GND_Y48Y48
GND_Y51Y51
GND_Y52Y52
GND_Y7Y7
GND_Y8Y8
GND_Y9Y9
GND_AE2AE2
GND_AE20AE20
GND_AE25AE25
GND_AE30AE30
GND_AE35AE35
GND_AE38AE38
GND_AE40AE40
GND_AE43AE43
GND_AE46AE46
GND_AE49AE49
GND_AE5AE5
GND_AE50AE50
GND_AE53AE53
GND_AE54AE54
GND_AE6AE6
GND_AE9AE9
GND_AF12AF12
GND_BG36BG36
GND_BG4BG4
GND_BG41BG41
GND_BG46BG46
GND_BG49BG49
GND_BG5BG5
GND_BG50BG50
GND_BG53BG53
GND_BG54BG54
GND_BG6BG6
GND_BG9BG9
GND_BH1BH1
GND_BH14BH14
GND_BH19BH19
GND_BH2BH2
GND_BH24BH24
GND_BH29BH29
GND_BH3BH3
GND_BH34BH34
GND_BN14BN14
GND_K40K40
GND_H14H14
GND_H19H19
GND_H24H24
GND_H29H29
GND_H3H3
GND_H34H34
GND_H39H39
GND_H4H4
GND_H44H44
GND_H49H49
GND_H54H54
GND_H7H7
GND_H8H8
GND_H9H9
GND_J1J1
GND_J12J12
GND_J17J17
GND_J2J2
GND_J22J22
GND_J27J27
GND_J32J32
GND_J37J37
GND_J42J42
GND_J47J47
GND_N53N53
GND_N54N54
GND_N9N9GND_P12P12GND_P14P14GND_P16P16GND_P17P17GND_P22P22GND_P27P27GND_P3P3GND_P32P32GND_P37P37GND_P4P4GND_P42P42GND_P46P46GND_P47P47GND_P48P48GND_P51P51GND_P52P52GND_P7P7GND_P8P8GND_P9P9GND_R1R1GND_R10R10GND_R11R11GND_R12R12GND_R15R15GND_R17R17GND_R2R2GND_R20R20GND_R25R25GND_R30R30GND_R35R35GND_R40R40GND_R45R45GND_R46R46GND_R49R49GND_R5R5GND_R50R50GND_R53R53GND_R54R54GND_R6R6GND_R9R9GND_T12T12GND_T14T14GND_T16T16GND_T18T18GND_T23T23GND_T28T28GND_T3T3GND_T33T33GND_T38T38GND_T4T4GND_T43T43GND_T46T46GND_T47T47GND_T48T48GND_T51T51
S10_DX_ND5_F2912D_EXTERNAL
U1-30
GND_AK52AK52
GND_AK7AK7
GND_AK8AK8
GND_AK9AK9
GND_AL1AL1
GND_AL12AL12
GND_AL13AL13
GND_AL15AL15
GND_AL18AL18
GND_AL2AL2
GND_AL23AL23
GND_AL28AL28
GND_AL33AL33
GND_AL38AL38
GND_AL40AL40
GND_AL41AL41
GND_AL42AL42
GND_AL43AL43
GND_AL46AL46
GND_AL49AL49
GND_AL5AL5
GND_AL50AL50
GND_AL53AL53
GND_AL54AL54
GND_AL6AL6
GND_AL9AL9
GND_AM10AM10
GND_AM12AM12
GND_AM13AM13
GND_AM14AM14
GND_AM15AM15
GND_AM16AM16
GND_AM17AM17
GND_AM21AM21
GND_AM26AM26
GND_AM3AM3
GND_AM31AM31
GND_AM36AM36
GND_AM4AM4
GND_AM41AM41
GND_AM46AM46
GND_AM47AM47
GND_AM48AM48
GND_AM51AM51
GND_AM52AM52
GND_AM7AM7
GND_AM8AM8
GND_AM9AM9
GND_AN1AN1
GND_AN12AN12
GND_AN15AN15
GND_AN17AN17
GND_AN19AN19
GND_AN2AN2
GND_AN24AN24
GND_AN29AN29
GND_AN34AN34
GND_AN38AN38
GND_AN40AN40
GND_AN42AN42
GND_AN43AN43
GND_AN44AN44
GND_AN45AN45
GND_AN46AN46
GND_AN49AN49
GND_AN5AN5
GND_AN50AN50
GND_AN53AN53
GND_AN54AN54
GND_AN6AN6
GND_AN9AN9
GND_AP12AP12
GND_AP15AP15
GND_AP17AP17
GND_AP22AP22
GND_AP27AP27
GND_AP3AP3
GND_AP32AP32
GND_AP37AP37
GND_AP39AP39GND_AP4AP4GND_AP41AP41GND_AP43AP43GND_AP46AP46GND_AP47AP47GND_AP48AP48GND_AP51AP51GND_AP52AP52GND_AP7AP7GND_AP8AP8GND_AP9AP9GND_AR1AR1GND_AR10AR10GND_AR11AR11GND_AR12AR12GND_AR14AR14GND_AR16AR16GND_AR2AR2GND_AR20AR20
GND_AC13AC13
GND_AC15AC15
GND_AC19AC19
GND_AC2AC2
GND_AC24AC24
GND_AC29AC29
GND_AC34AC34
GND_AC40AC40
GND_AC42AC42
GND_AC43AC43
GND_AC46AC46
GND_AC49AC49
GND_AC5AC5
GND_AC50AC50
GND_AC53AC53
GND_AC54AC54
GND_AC6AC6
GND_AC9AC9
GND_AD12AD12
GND_AD14AD14
GND_AD16AD16
GND_AD22AD22
GND_AD27AD27
GND_AD3AD3
GND_AD32AD32
GND_AD37AD37
GND_AD39AD39
GND_AD4AD4
GND_AD41AD41
GND_AD43AD43
GND_AD46AD46
GND_AD47AD47
GND_AD48AD48
GND_AD51AD51
GND_AD52AD52
GND_AD7AD7
GND_AD8AD8
GND_AD9AD9
GND_AE1AE1
GND_AE10AE10
GND_AE11AE11
GND_AE12AE12
GND_AE15AE15
GND_AE17AE17
TEMPDIODE2PAE44
TEMPDIODE2NAE45
TEMPDIODE1PAM42
TEMPDIODE1NAM43
TEMPDIODE4PBA16
TEMPDIODE4NBA17
TEMPDIODE0PBK28
TEMPDIODE0NBM27
TEMPDIODE6NN10 TEMPDIODE6PN11
GND_AW49AW49 GND_A13
A13 GND_A18A18 GND_A38A38 GND_A4
A4 GND_A43A43 GND_A48A48 GND_A5
A5GND_A52
A52
GND_A53A53
GND_A6A6
GND_A7A7
GND_AA1AA1
GND_AA12AA12
GND_AA13AA13
GND_AA15AA15
GND_AA18AA18
GND_AA2AA2
GND_AA23AA23
GND_AA28AA28
GND_AA33AA33
GND_AA38AA38
GND_AA43AA43
GND_AA46AA46
GND_AA49AA49
GND_AA5AA5
GND_AA50AA50
GND_AA53AA53
GND_AA54AA54
GND_AA6AA6
GND_AA9AA9
GND_AB11AB11
GND_AB13AB13
GND_AB16AB16
GND_AB17AB17
GND_AB21AB21
GND_AB26AB26
GND_AB3AB3
GND_AB31AB31
GND_AB36AB36
GND_AB4AB4
GND_AB41AB41
GND_AB46AB46
GND_AB47AB47
GND_AB48AB48
GND_AB51AB51
GND_AB52AB52
GND_AB7AB7
GND_AB8AB8
GND_AB9AB9
GND_AC1AC1
TEMPDIODE5PAA14
TEMPDIODE5NAB14 S10_DX_ND5_F2912D_EXTERNAL
U1-33
GND_C24C24
GND_C29C29
GND_C34C34
GND_C39C39
GND_C44C44
GND_C49C49
GND_C5C5
GND_C54C54
GND_C6C6
GND_C9C9
GND_D12D12
GND_D17D17
GND_D22D22
GND_D27D27
GND_D3D3
GND_D32D32
GND_D37D37
GND_D4D4
GND_D42D42
GND_D47D47
GND_D52D52
GND_D7D7
GND_D8D8
GND_D9D9
GND_E1E1
GND_E10E10
GND_E15E15
GND_E2E2
GND_E20E20
GND_E25E25
GND_E30E30
GND_E35E35
GND_E40E40
GND_E45E45
GND_E5E5
GND_E50E50
GND_E6E6
GND_E9E9
GND_F13F13
GND_F18F18
GND_F23F23
GND_F28F28
GND_F3F3
GND_F33F33
GND_F38F38
GND_F4F4
GND_F43F43
GND_F48F48
GND_F53F53
GND_F7F7
GND_F8F8
GND_F9F9
GND_G1G1
GND_G11G11
GND_G16G16
GND_G2G2
GND_G21G21
GND_G26G26
GND_G31G31
GND_G36G36
GND_G41G41
GND_G46G46
GND_G5G5
GND_G51G51
GND_G6G6
GND_G9G9
GND_BP28BP28
GND_BP29BP29
GND_BL38BL38
GND_BL4BL4
GND_BL43BL43
GND_BL48BL48
GND_BL5BL5
GND_BL53BL53
GND_BL6BL6
GND_BL9BL9
GND_BM1BM1
GND_BM11BM11
GND_BM16BM16
GND_BM2BM2
GND_BM21BM21
GND_BM26BM26
GND_BM3BM3
GND_BM31BM31
GND_BM36BM36
GND_BM41BM41
GND_BM46BM46
GND_BM51BM51
GND_BM54BM54
GND_BM6BM6
GND_BM7BM7
GND_BM8BM8
GND_BM9BM9
GND_BN1BN1
GND_BN19BN19
GND_BN24BN24
GND_BN29BN29
GND_BN3BN3
GND_BN34BN34
GND_BN39BN39
GND_BN4BN4
GND_BN44BN44
GND_BN5BN5GND_BN54BN54GND_BN6BN6GND_BN9BN9GND_BP12BP12GND_BP17BP17GND_BP2BP2GND_BP22BP22GND_BP27BP27GND_BP3BP3GND_BP32BP32GND_BP37BP37GND_BP42BP42GND_BP47BP47GND_BP52BP52GND_BP53BP53GND_BP6BP6GND_BP7BP7GND_BP8BP8GND_BP9BP9GND_C1C1GND_C14C14GND_C19C19GND_C2C2
GND_AJ40AJ40
GND_AJ38AJ38
GND_AJ37AJ37
GND_AJ32AJ32
GND_AJ27AJ27
GND_AJ22AJ22
GND_AJ2AJ2
GND_AJ17AJ17
GND_AJ15AJ15
GND_AJ12AJ12
GND_AJ11AJ11
GND_AJ10AJ10
GND_AJ1AJ1
GND_AH9AH9
GND_AH8AH8
GND_AH7AH7
GND_K20K20
GND_K25K25
GND_K3K3
GND_K30K30
GND_K35K35
GND_K4K4
GND_K45K45
GND_K50K50
GND_K7K7
GND_K8K8
GND_K9K9
GND_L1L1
GND_L13L13
GND_L18L18
GND_L2L2
GND_L23L23
GND_L28L28
GND_L33L33
GND_L38L38
GND_L43L43
GND_L48L48
GND_L5L5
GND_L53L53
GND_L6L6
GND_L9L9
GND_M11M11
GND_M16M16
GND_M21M21
GND_M26M26
GND_M3M3
GND_M31M31
GND_M36M36
GND_M4M4
GND_M41M41
GND_M46M46
GND_M51M51
GND_M7M7
GND_M8M8
GND_M9M9
GND_N1N1
GND_N13N13
GND_N15N15
GND_N19N19
GND_N2N2
GND_N24N24
GND_N29N29
GND_N34N34
GND_N39N39
GND_N44N44
GND_N48N48
GND_N49N49
GND_N5N5
GND_N50N50
GND_N51N51
GND_N52N52
GND_J5J5
GND_J52J52
GND_J6J6
GND_J9J9
GND_K10K10
GND_K15K15
GND_N6N6
S10_DX_ND5_F2912D_EXTERNAL
U1-31
GND_BB3BB3
GND_BB31BB31
GND_BB36BB36
GND_BB4BB4
GND_BB41BB41
GND_BB46BB46
GND_BB47BB47
GND_BB48BB48
GND_BB5BB5
GND_BB51BB51
GND_BB52BB52
GND_BB6BB6
GND_BB7BB7
GND_BB8BB8
GND_BB9BB9
GND_BC1BC1
GND_BC12BC12
GND_BC14BC14
GND_BC19BC19
GND_BC2BC2
GND_BC24BC24
GND_BC29BC29
GND_BC3BC3
GND_BC34BC34
GND_BC39BC39
GND_BC4BC4
GND_BC44BC44
GND_BC46BC46
GND_BC49BC49
GND_BC5BC5
GND_BC50BC50
GND_BC53BC53
GND_BC54BC54
GND_BC6BC6
GND_BC9BC9
GND_BD1BD1
GND_BD10BD10
GND_BD11BD11
GND_BD12BD12
GND_BD17BD17
GND_BD2BD2
GND_BD22BD22
GND_BD27BD27
GND_BD3BD3
GND_BD32BD32
GND_BD37BD37
GND_BD42BD42
GND_BD46BD46
GND_BD47BD47
GND_BD48BD48
GND_BD51BD51
GND_BD52BD52
GND_BD6BD6
GND_BD7BD7
GND_BD8BD8
GND_BD9BD9
GND_BE10BE10
GND_BE15BE15
GND_BE20BE20
GND_BE25BE25
GND_BE3BE3
GND_BE30BE30
GND_BE35BE35
GND_BE4BE4
GND_BE40BE40
GND_BE45BE45
GND_BE46BE46
GND_BE49BE49
GND_BE5BE5
GND_BE50BE50
GND_BE53BE53
GND_BE54BE54
GND_BE6BE6
GND_BE9BE9
GND_BF1BF1
GND_BF13BF13
GND_BF18BF18
GND_BF2BF2
GND_BF23BF23
GND_BF28BF28
GND_BF3BF3
GND_BF33BF33
GND_BF38BF38
GND_BF43BF43
GND_BF46BF46
GND_BF47BF47
GND_BF48BF48
GND_BF51BF51
GND_BF52BF52
GND_BF6BF6
GND_BF7BF7
GND_BF8BF8
GND_BF9BF9
GND_BG11BG11
GND_BG16BG16
GND_BG21BG21
GND_BG26BG26
GND_BG3BG3
GND_BG31BG31
GND_AR25AR25 GND_AR30AR30 GND_AR35AR35
GND_AR38AR38
GND_AR40AR40
GND_AR43AR43
GND_AR44AR44
GND_AR45AR45
GND_AR46AR46
GND_AR49AR49
GND_AR5AR5
GND_AR50AR50
GND_AR53AR53
GND_AR54AR54
GND_AR6AR6
GND_AR9AR9
GND_AT12AT12
GND_AT15AT15
GND_AT17AT17
GND_AT18AT18
GND_AT23AT23
GND_AT28AT28
GND_AT3AT3
GND_AT33AT33
GND_AT39AT39
GND_AT4AT4
GND_AT41AT41
GND_AT43AT43
GND_AT46AT46
GND_AT47AT47
GND_AT48AT48
GND_AT51AT51
GND_AT52AT52
GND_AT7AT7
GND_AT8AT8
GND_AT9AT9
GND_AU1AU1
GND_AU12AU12
GND_AU14AU14
GND_AU16AU16
GND_AU2AU2
GND_AU21AU21
GND_AU26AU26
GND_AU31AU31
GND_AU36AU36
GND_AU38AU38
GND_AY30AY30GND_AY35AY35GND_AY37AY37GND_AY39AY39GND_AY4AY4GND_AY41AY41GND_AY43AY43GND_AY46AY46GND_AY47AY47GND_AY48AY48GND_AY51AY51GND_AY52AY52GND_AY7AY7GND_AY8AY8GND_AY9AY9GND_B1B1GND_B11B11GND_B16B16GND_B2B2GND_B21B21GND_B26B26GND_B3B3GND_B31B31GND_B36B36GND_B4B4GND_B41B41GND_B46B46GND_B51B51GND_B54B54GND_B7B7GND_B8B8GND_B9B9GND_BA1BA1GND_BA11BA11GND_BA12BA12GND_BA13BA13GND_BA14BA14GND_BA15BA15GND_BA18BA18GND_BA2BA2GND_BA23BA23GND_BA28BA28GND_BA33BA33GND_BA37BA37GND_BA40BA40GND_BA42BA42GND_BA43BA43GND_BA46BA46GND_BA49BA49GND_BA5BA5GND_BA50BA50GND_BA53BA53GND_BA54BA54GND_BA6BA6GND_BA9BA9GND_BB13BB13GND_BB16BB16GND_BB21BB21GND_BB26BB26
S10_DX_ND5_F2912D_EXTERNAL
U1-34
GND_BH46BH46
GND_BH47BH47
GND_BH48BH48
GND_BH51BH51
GND_BH52BH52
GND_BH6BH6
GND_BH7BH7
GND_BH8BH8
GND_BH9BH9
GND_BJ12BJ12
GND_BJ17BJ17
GND_BJ22BJ22
GND_BJ27BJ27
GND_BJ3BJ3
GND_BJ32BJ32
GND_BJ37BJ37
GND_BJ4BJ4
GND_BJ42BJ42
GND_BJ46BJ46
GND_BJ49BJ49
GND_BJ5BJ5
GND_BJ50BJ50
GND_BJ53BJ53
GND_BJ54BJ54
GND_BJ6BJ6
GND_BJ9BJ9
GND_BK1BK1
GND_BK10BK10
GND_BK15BK15
GND_BK2BK2
GND_BK20BK20
GND_BK25BK25
GND_BK3BK3
GND_BK30BK30
GND_BK35BK35
GND_BK40BK40
GND_BK45BK45
GND_BK46BK46
GND_BK47BK47
GND_BK48BK48
GND_BK49BK49
GND_BK50BK50
GND_BK51BK51
GND_BK52BK52
GND_BK53BK53
GND_BK6BK6
GND_BK7BK7
GND_BK8BK8
GND_BK9BK9
GND_BL13BL13
GND_BL18BL18
GND_BL23BL23
GND_BL28BL28
GND_BL3BL3
GND_BL33BL33
GND_AF14AF14
GND_AF16AF16
GND_AF23AF23
GND_AF28AF28
GND_AF3AF3
GND_AF33AF33
GND_AF39AF39
GND_AF4AF4
GND_AF41AF41
GND_AF43AF43
GND_AF45AF45
GND_AF46AF46
GND_AF47AF47
GND_AF48AF48
GND_AF51AF51
GND_AF52AF52
GND_AF7AF7
GND_AF8AF8
GND_AF9AF9
GND_AG1AG1
GND_AG10AG10
GND_AG11AG11
GND_AG12AG12
GND_AG15AG15
GND_AG17AG17
GND_AG2AG2
GND_AG21AG21
GND_AG26AG26
GND_AG31AG31
GND_AG36AG36
GND_AG38AG38
GND_AG40AG40
GND_AG43AG43
GND_AG46AG46
GND_AG49AG49
GND_AG5AG5
GND_AG50AG50
GND_AG53AG53
GND_AG54AG54
GND_AG6AG6
GND_AG9AG9
GND_AH12AH12
GND_AH14AH14
GND_AH16AH16
GND_AH19AH19
GND_AH24AH24
GND_AH29AH29
GND_AH3AH3
GND_AH34AH34
GND_BH39BH39
GND_BH44BH44
GND_AU49AU49
GND_AU5AU5
GND_AU50AU50
GND_AU53AU53
GND_AU54AU54
GND_AU6AU6
GND_AU9AU9
GND_AV11AV11
GND_AV12AV12
GND_AV15AV15
GND_AV17AV17
GND_AV19AV19
GND_AV24AV24
GND_AV29AV29
GND_AV3AV3
GND_AV34AV34
GND_AV39AV39
GND_AV4AV4
GND_AV41AV41
GND_AV43AV43
GND_AV46AV46
GND_AV47AV47
GND_AV48AV48
GND_AV51AV51
GND_AV52AV52
GND_AV7AV7
GND_AV8AV8
GND_AV9AV9
GND_AW1AW1
GND_AW12AW12
GND_AW15AW15
GND_AW17AW17
GND_AW2AW2
GND_AW22AW22
GND_AW27AW27
GND_AW32AW32
GND_AW37AW37
GND_AW38AW38
GND_AW40AW40
GND_AW43AW43
GND_AW46AW46
GND_AW5AW5
GND_AW50AW50
GND_AW53AW53
GND_AW54AW54
GND_AW6AW6
GND_AW9AW9
GND_AY10AY10
GND_AY12AY12
GND_AY15AY15
GND_AY16AY16
GND_AY17AY17
GND_AY20AY20
GND_AY25AY25
GND_AY3AY3
GND_AU40AU40
GND_AU43AU43
GND_AU44AU44
GND_AU45AU45
GND_AU46AU46
GND_A23A23
GND_A28A28
GND_A33A33
GND_AF18AF18
GND_AF44AF44
GND_AH39AH39
GND_AH4AH4
GND_AH41AH41
GND_AH43AH43
GND_AH44AH44
GND_AH45AH45
GND_AH46AH46
GND_AH47AH47
GND_AH48AH48
GND_AH51AH51
GND_AH52AH52
GND_AK12AK12
GND_AJ9AJ9
GND_AJ6AJ6
GND_AJ54AJ54
GND_AJ53AJ53
GND_AJ50AJ50
GND_AJ5AJ5
GND_AJ49AJ49
GND_AJ46AJ46
GND_AJ43AJ43
GND_AK51AK51
GND_AK48AK48
GND_AK47AK47
GND_AK46AK46
GND_AK45AK45
GND_AK44AK44
GND_AK43AK43
GND_AK41AK41
GND_AK4AK4
GND_AK39AK39
GND_AK35AK35
GND_AK30AK30
GND_AK3AK3
GND_AK25AK25
GND_AK20AK20
GND_AK16AK16
GND_AK14AK14
GND_A2A2
GND_BN49BN49
S10_TEMPDIODE1_N
S10_TEMPDIODE4_NS10_TEMPDIODE4_P
S10_TEMPDIODE6_P
S10_TEMPDIODE5_PS10_TEMPDIODE5_N
S10_TEMPDIODE2_PS10_TEMPDIODE2_N
S10_TEMPDIODE1_P
S10_TEMPDIODE6_N
S10_TEMPDIODE0_NS10_TEMPDIODE0_P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCIe Edge x16 Gold Fingers
Link Width DIP Switch
H = 0.40mmPlace on Bottom side
To MAX10From PCIe
From MAX10 To PCIE
To MAX10From PCIe
Schmitt Buffer
From PCIe To MAX10
Schmitt Buffer
SW28 : ON = EP ( Default)OFF = RP
Note: Place near to golden finger
PCIe GEN4 CEM Version 4
12V_PCIE_SLOT
12V_PCIE_SLOT 3.3V_PCIE_SLOT12V_PCIE_SLOT
3.3V_PCIE_SLOT
3.3V_REG_INST
3.3V_REG_INST3.3V_REG_INST
3.3V_REG_INST3.3V_REG_INST
3.3V_REG_INST3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST3.3V_REG_INST
PCIE_TX_P[15:0] 15PCIE_TX_N[15:0] 15
PCIE_RX_P[15:0] 15PCIE_RX_N[15:0] 15
BMC_BUF_TMS 23
BMC_BUF_TCK 23
BMC_BUF_TDI 23
BMC_BUF_TDO23
PCIE_3V3_BMC_RST_N 23
PCIE_EDGE_SMBCLK23PCIE_EDGE_SMBDAT23
PCIE_EDGE_WAKEn23,68
PCIE_PERSTn 68
CLK_100M_PCIe_REFCLK_P 22CLK_100M_PCIe_REFCLK_N 22
PCIE_3V3_BMC_PERST_N 23
PCIE_PRSNT2n_x1 68PCIE_PRSNT2n_x4 68PCIE_PRSNT2n_x8 68PCIE_PRSNT2n_x16 68
PCIE_CLKREQ_N68
CLK_100M_PCIe_REFCLK_RP_P 22CLK_100M_PCIe_REFCLK_RP_N 22
PCIE_Rp_IO_3V368
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
21 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
21 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
21 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C1482 1pF
C21 0.22uF 0201
C1474 1pF
C1478 1pF
C33 0.22uF 0201
R55 0
R481 33.21%0402
C47
0.1uF
0402
C20 0.22uF 0201
R50 0, DNI
R775 49.9
R783 49.9
R779 49.9
C34 0.22uF 0201
C8000.1uF040225VX7R
C8 0.22uF 0201
C7990.1uF040225VX7R
R46010.0K,DNI0402
1%
C23 0.22uF 0201
U21074LVC1G3157GM,115
Y11
GN
D2
Y03
Z4
VCC5
S6
C35 0.22uF 0201
C9 0.22uF 0201
R45010.0K04021%
C32200.1uF040225VX7R
R44810.0K04021%
C22 0.22uF 0201
C1475 1pF
C36 0.22uF 0201
C1479 1pF
C10 0.22uF 0201
R5497100K0402
1%
U68
SN74LVC2G17DCKR
SC70-6
IN_2A3
IN_1A1
VCC5
GND2
OUT_1Y6
OUT_2Y4
C25 0.22uF 0201
U64
SN74LVC2G17DCKR
SC70-6
IN_2A3
IN_1A1
VCC5
GND2
OUT_1Y6
OUT_2Y4
R51510.0K04021%
C37 0.22uF 0201
R780 49.9
C11 0.22uF 0201
R776 49.9
U118
MAX6817EUT+T
GND2
IN11
IN23
OUT24
VCC5
OUT16
C24 0.22uF 0201
C38 0.22uF 0201
R51610.0K04021%
C12 0.22uF 0201
C27 0.22uF 0201
R518 33.21%0402
A&B=Y
U5
SN74LVC1G08_6PIN
A1
B2
GND3
VCC6
NC5
Y4
C1480 1pF
C39 0.22uF 0201
C1476 1pF
OPEN
SW2
TDA04H0SB1
1234 5
678
C26 0.22uF 0201
C1472 1pF
R44910.0K0402
1%
ON
SW28
CVS-01TB
1 2
C40 0.22uF 0201
R781 49.9
C43
0.1uF
0402
R777 49.9
S1
PB Switch1 2
C29 0.22uF 0201
R773 49.9
R531 33.21%0402
C13 0.22uF 0201
C42 0.22uF 0201
R671210.0K0402
1%
R51 0
R665810.0K0402
1%
C28 0.22uF 0201
C8030.1uF040225VX7R
R477 33.21%0402
C44
0.1uF
0402
C1481 1pF
C14 0.22uF 0201
C1473 1pF
C1477 1pF
R669610.0K04021%
C30 0.22uF 0201
R46210.0K0402
1%
R521 33.21%0402
R534 33.21%0402
C19 0.22uF 0201
R774 49.9
R782 49.9
R778 49.9
C31 0.22uF 0201
KEY
X4
X8
X1
X16
J9
PCIE_Slot
+12VB1
+12VB2
+12VB3
GNDB4
SMCLKB5
SMDATB6
GNDB7
+3_3VB8
JTAG_TRSTNB9
+3_3VAUXB10
WAKE_NB11
RSVD1B12
GNDB13
PET0PB14
PET0NB15
GNDB16
PRSNT2n_X1B17
GNDB18
PET1PB19
PET1NB20
GNDB21
GNDB22
PET2PB23
PET2NB24
GNDB25
GNDB26
PET3PB27
PET3NB28
GNDB29
RSVD3B30
PRSNT2n_X4B31
GNDB32
PET4PB33
PET4NB34
GNDB35
GNDB36
PET5PB37
PET5NB38
GNDB39
GNDB40
PET6PB41
PET6NB42
GNDB43
GNDB44
PET7PB45
PET7NB46
GNDB47
PRSNT2n_X8B48
GNDB49
PRSNT1_NA1
+12VA2
+12VA3
GNDA4
JTAG_TCKA5
JTAG_TDIA6
JTAG_TDOA7
JTAG_TMSA8
+3_3VA9
+3_3VA10
PERST_NA11
GNDA12
REFCLK+A13
REFCLK-A14
GNDA15
PER0PA16
PER0NA17
GNDA18
RSVD2A19
GNDA20
PER1PA21
PER1NA22
GNDA23
GNDA24
PER2PA25
PER2NA26
GNDA27
GNDA28
PER3PA29
PER3NA30
GNDA31
RSVD4A32
RSVD5A33
GNDA34
PER4PA35
PER4NA36
GNDA37
GNDA38
PER5PA39
PER5NA40
GNDA41
GNDA42
PER6PA43
PER6NA44
GNDA45
GNDA46
PER7PA47
PER7NA48
GNDA49
PET8PB50
PET8NB51
GNDB52
GNDB53
PET9PB54
PET9NB55
GNDB56
GNDB57
PET10PB58
PET10NB59
GNDB60
GNDB61
PET11PB62
PET11NB63
GNDB64
GNDB65
PET12PB66
PET12NB67
GNDB68
GNDB69
PET13PB70
PET13NB71
GNDB72
GNDB73
PET14PB74
PET14NB75
GNDB76
GNDB77
PET15PB78
PET15NB79
GNDB80
PRSNT2n_X16B81
RSVD6B82
RSVD7A50
GNDA51
PER8PA52
PER8NA53
GNDA54
GNDA55
PER9PA56
PER9NA57
GNDA58
GNDA59
PER10PA60
PER10NA61
GNDA62
GNDA63
PER11PA64
PER11NA65
GNDA66
GNDA67
PER12PA68
PER12NA69
GNDA70
GNDA71
PER13PA72
PER13NA73
GNDA74
GNDA75
PER14PA76
PER14NA77
GNDA78
GNDA79
PER15PA80
PER15NA81
GNDA82
C45
0.1uF
0402
B1
PCI BRACKET
C41 0.22uF 0201
R5498100K0402
1%
C15 0.22uF 0201
C46
0.1uF
0402
C32 0.22uF 0201
R46110.0K0402
1%
PCIE_TX_N1PCIE_TX_P1PEX_TX_CP1
PEX_TX_CN1
PCIE_TX_P2PEX_TX_CP2PEX_TX_CN2
PCIE_TX_N3PCIE_TX_P3PEX_TX_CP3
PEX_TX_CN3
PCIE_TX_N4PCIE_TX_P4PEX_TX_CP4
PEX_TX_CN4
PCIE_TX_N5PCIE_TX_P5PEX_TX_CP5
PEX_TX_CN5
PCIE_TX_N6PCIE_TX_P6PEX_TX_CP6
PEX_TX_CN6
PCIE_TX_N7PCIE_TX_P7PEX_TX_CP7
PEX_TX_CN7
PCIE_TX_N8PCIE_TX_P8PEX_TX_CP8
PEX_TX_CN8
PCIE_TX_N9PCIE_TX_P9PEX_TX_CP9
PEX_TX_CN9
PCIE_TX_N10PCIE_TX_P10PEX_TX_CP10
PEX_TX_CN10
PCIE_TX_N11PCIE_TX_P11PEX_TX_CP11
PEX_TX_CN11
PCIE_TX_P12PEX_TX_CP12PCIE_TX_N12PEX_TX_CN12
PCIE_TX_N13PCIE_TX_P13PEX_TX_CP13
PEX_TX_CN13
PCIE_TX_N14PCIE_TX_P14PEX_TX_CP14
PEX_TX_CN14
PCIE_TX_N15PCIE_TX_P15PEX_TX_CP15
PEX_TX_CN15
PCIE_TX_P0PCIE_TX_N0PEX_TX_CN0
PEX_TX_CP0
CLK_100M_PCIe_REFCLK_PCLK_100M_PCIe_REFCLK_N
PCIE_TX_N2
PB_PERSTn
PCIE_PRSNT2n_x8
PCIE_PRSNT2n_x4
PCIE_PRSNT2n_x1
PCIE_WAKEn_R3.3V_PCIE_AUX
PCIE_PRSNT2n_x16
PCIE_RX_N1PCIE_RX_P1
PCIE_RX_N2PCIE_RX_P2
PCIE_RX_N3PCIE_RX_P3
PCIE_RX_N4PCIE_RX_P4
PCIE_RX_N5PCIE_RX_P5
PCIE_RX_N6PCIE_RX_P6
PCIE_RX_N7PCIE_RX_P7
PCIE_RX_N9PCIE_RX_P9
PCIE_RX_N10PCIE_RX_P10
PCIE_RX_N11PCIE_RX_P11
PCIE_RX_N12PCIE_RX_P12
PCIE_RX_N14PCIE_RX_P14
PCIE_RX_P0PCIE_RX_N0
PCIE_RX_N15PCIE_RX_P15
PCIE_RX_N13PCIE_RX_P13
PCIE_RX_P8PCIE_RX_N8
PCIE_EDGE_WAKEn
PCIE_PRSNT1n
BMC_TCKBMC_TDIBMC_TDOBMC_TMS
BMC_TMS
BMC_TDO
BMC_TDI
BMC_TCK
SW_PERSTn
PCIE_PRSNT2n_x16
PCIE_PRSNT2n_x4PCIE_PRSNT2n_x1
PCIE_PRSNT2n_x8
CLK_100M_PCIe_REFCLK_RP_P
CLK_100M_PCIe_REFCLK_RP_N
PCIE_EDGE_PERSTn
PCIE_RSV2
PCIE_RSV7
PCIE_CLKREQ_NPCIE_RSV2PCIE_RSV3CLK_100M_PCIe_REFCLK_PCLK_100M_PCIe_REFCLK_NPCIE_RSV6PCIE_RSV7PCIE_PRSNT2n_x1PCIE_PRSNT2n_x4PCIE_PRSNT2n_x8PCIE_PRSNT2n_x16
PCIE_RSV6
PCIE_RSV3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Bypass Mode
LP-HCSL 3V3 100 MHz
LP-HCSL 3V3 100 MHz
LP-HCSL 3V3 100 MHz
LP-HCSL 3V3 100 MHz
LP-HCSL 3V3 100 MHz
HCSL 3.3V 100MHz INPUT
Provides Bench Testing
I2C Address = 0x74
Board System Clocks
HCSL 3V3 100MHz
LVDS 3.3V 100 MHz INPUT
Default
Custom Programmed: INPUT1=CLKIN_SEL[0]INPUT2=CLKIN_SEL[1]I2C addres = 0x6A (Default)
Default LVDS 1V8 100 MHz
(DEFAULT)
Default LVDS 1V8 150 MHz
HIGHHIGH LOW
HIGH
CLKIN_SEL[0]
LVCMOS 1V8 125MHz
LOWLOW
Default LVDS 1V8 150 MHz
HIGHCLKIN2
XA/XB
PLL INPUT
LOWCLKIN_SEL[1]
Default LVDS 1V8 150 MHz
CLKIN3
Default LVDS 1V8 150 MHz
DISABLED
Default LVDS 1V8 100 MHz
Default LVPECL 2V5 156.25 MHz
Default LVPECL 2V5 156.25 MHz
A (defautl)
LP-HCSL 3V3 100 MHz
POS_2
LP-HCSL 3V3 100 MHz
BPOS_1
INPUT CHANNELSW SELECT
Default LVPECL 2V5 312.5 MHz
A (defautl)POS_2
INPUT CHANNEL
B
SW SELECT
LP-HCSL 3V3 100 MHz
POS_1LP-HCSL 3V3 100 MHz
Default LVPECL 2V5 312.5 MHz
Default LVPECL 2V5 312.5 MHz
Default LVDS 3.3V 100 MHz
Default LVDS 1V8 100 MHz
Default LVDS 1V8 100 MHz
INPUT CHANNELSW SELECT
LP-HCSL 3V3 100 MHz
A (defautl)POS_2
LP-HCSL 3V3 100 MHzB
POS_1
LP-HCSL 3V3 100 MHz
LP-HCSL 3V3 100 MHzI2C ADDR = D8H
LP-HCSL 3V3 100 MHz
LP-HCSL 3V3 100 MHz
LP-HCSL 3V3 100 MHz
LP-HCSL 3V3 100 MHz
SW14 PCIe REFCLK/TEST CLK Select
OFF = PCIe REFCLK (Default)
ON = 100MHz TEST REFCLK
1.8V3.3V_REG 3.3V_REG
3.3V_REG
S10_VCCCLK_GXE_LOW
3.3V_REG
1.8V1.8V
3.3V_REG
3.3V_REG 3.3V_REG
3.3V_REG
3.3V_REG3.3V_REG
3.3V_REG
3.3V_REG 3.3V_REG
3.3V_REG3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG 3.3V_REG
3.3V_REG
3.3V_REG3.3V_REG
3.3V_REG3.3V_REG
3.3V_REG
3.3V_REG3.3V_REG
3.3V_REG
CLK0_OEn23CLK0_RSTn23
CLK_100M_FPGA_3H_P 12CLK_100M_FPGA_3H_N 12
CLK_125M_LVC1_CONFIG 6
CLK_156.25M_QSFP1_P 14CLK_156.25M_QSFP1_N 14
CLK_133M_DDR4_0_P 11CLK_133M_DDR4_0_N 11
CLK_156.25M_QSFP0_P 14CLK_156.25M_QSFP0_N 14 I2C2_SCL6,7,22,23,69 CLK_133M_DDR4_1_P 9
I2C2_SDA6,7,22,23,69 CLK_133M_DDR4_1_N 9
CLK_312.5M_QSFP0_P 14 CLK_133M_DIMM_0_P 7CLK_312.5M_QSFP0_N 14 CLK_133M_DIMM_0_N 7
CLK_133M_DIMM_1_P 10CLK_312.5M_QSFP1_P 14 CLK_133M_DIMM_1_N 10CLK_312.5M_QSFP1_N 14
CLK_100M_FPGA_3L_0_P 12CLK_100M_FPGA_3L_0_N 12
CLK_312.5M_QSFP2_P 14CLK_312.5M_QSFP2_N 14
CLK2_100M_FPGA_2I_P 7CLK2_100M_FPGA_2I_N 7
CLK2_100M_FPGA_2J_0_P 8CLK2_100M_FPGA_2J_0_N 8
CLK_100M_UPI0_REFCLK_EP_P25CLK_100M_UPI0_REFCLK_EP_N25
CLK_100M_UPI0_1_P 15CLK_100M_UPI0_1_N 15
CLK0_LOL 23 CLK_100M_UPI0_0_P 15CLK_100M_UPI0_0_N 15
CLK_100M_UPI1_REFCLK_EP_P26CLK_100M_UPI1_REFCLK_EP_N26
CLK_100M_UPI1_1_P 16CLK_100M_PCIE_0_P 15 CLK_100M_UPI1_1_N 16CLK_100M_PCIE_0_N 15
CLK_100M_UPI1_0_P 16CLK_100M_PCIE_1_P 15 CLK_100M_UPI1_0_N 16CLK_100M_PCIE_1_N 15
CLK_100M_UPI0_REFCLK_RP_P 25CLK_100M_UPI0_REFCLK_RP_N 25
CLK_100M_UPI1_REFCLK_RP_P 26CLK_100M_UPI1_REFCLK_RP_N 26
CLK_100M_UPI2_REFCLK_RP_P 27CLK_100M_UPI2_REFCLK_RP_N 27
CLK_100M_PCIe_REFCLK_RP_P 21CLK_100M_PCIe_REFCLK_RP_N 21
I2C2_SDA6,7,22,23,69I2C2_SCL6,7,22,23,69
CLK_100M_PCIe_REFCLK_P21CLK_100M_PCIe_REFCLK_N21
CLK_100M_UPI2_REFCLK_EP_P27CLK_100M_UPI2_REFCLK_EP_N27
CLK_100M_UPI2_1_P 16CLK_100M_UPI2_1_N 16
CLK_100M_UPI2_0_P 16CLK_100M_UPI2_0_N 16
Si5391_CLK_SEL069
Si5391_CLK_SEL169
Si5332_CLK_SEL069
Si5332_CLK_SEL169
UPI0_CLK_SEL69
UPI1_CLK_SEL69
UPI2_CLK_SEL69
CLK2_100M_FPGA_2J_1_P 8CLK2_100M_FPGA_2J_1_N 8
CLK_100M_FPGA_3L_1_P 12CLK_100M_FPGA_3L_1_N 12
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA Hollister Ridge Board
Custom
22 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA Hollister Ridge Board
Custom
22 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA Hollister Ridge Board
Custom
22 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C3002
1uF0402
R5720
42.2
R6471 0
C2990
1uF0402
C2005 0.1uF 0402
R5709
1K04021%
C3007
0.1uF0402
C2050 0.1uF 0402
C19950.1uF0402
C2024 0.1uF 0402
R5719
1K
C2972
1uF0402
C198910uF0603
R5623 20
L54
BLM15AG221SN1
R303 0
C2021 0.1uF 0402
C1966
10uF0603
L44
BLM15AG221SN1
R5724
42.2,DNI
C2991
1uF0402
C2037 0.1uF 0402
C3003
1uF0402
C3115 0.1uF
C199910uF0603
R6327 DNI 0402
C2013 0.1uF 0402
R6483 0
R6317 0
C2999
0.1uF0402
C3118 0.1uF
C198010uF0603
C3008
0.1uF0402
C2973
1uF0402
C19970.1uF0402
C3012 0.1uF
L51 BLM21AG601SN1D
R6383 DNI 0402
C1967
0.1uF0402
R5721
42.2,DNI
R6479 0
R6312 0
C3004
1uF0402
C199210uF0603
C197610uF0603
R6699 0
R6322 0
R5755 DNI
R6348 0
R5718
1K04021%
R5703 1R
R6344 0
R6610DNI
C2036 0.1uF 0402
C3009
0.1uF0402
C3000
0.1uF0402
C2974
1uF0402
R6391
49.9
R625910.0K
C2038 0.1uF 0402
C1968
0.1uF0402
R5741
42.2
C19900.1uF0402
R6305 0
C2987
1uF0402
R570512k
C2007 0.1uF 0402
R5725
1K04021%
R6401 10.0K
C19981uF
0402
C198710uF0603
C3112 0.1uF
ONSW14CVS-01TB
12
C2020 0.1uF 0402
C3001
0.1uF0402
R6395
49.9
C2975
1uF0402
C2976
0.1uF0402
R5706
42.2
R6311 0
R6488 0
R634110.0K
R5739
42.2
C1969
0.1uF0402
R5694 2.2R
C2018 0.1uF 0402
R6607DNI
R6492 0
R6352 0
C2049 0.1uF 0402
R6700 0
C3014
0.1uF0402
C19820.1uF
0402
Y548MHz
7M48072002
13
24
R5702 1R
R5751 DNI
R5701 1R
C3019 0.1uF
C19930.1uF0402
C2980
0.1uF0402
C19960.1uF0402
SI5332A-C-GM2
U7
VD
D_D
IG1
CLKIN_22
CLKIN_2B3
VD
D_X
TA
L4
XA/CLKIN15
XB6
CLKIN_37
CLKIN_3B8
VD
DA
9
INPUT110
SCLK11
SDATA12
OUT0B13OUT014V
DD
O0
15
OUT1B16OUT117
VD
DO
118
INPUT219
INPUT320
OUT2B21OUT222
OUT3B23OUT324
VD
DO
225
OUT4B26OUT427
VD
DO
328
OUT5B29OUT530
INPUT431
INPUT532
VD
DO
433
OUT6B34OUT635
INPUT636
INPUT737
OUT7B38OUT739
VD
DO
540
GND41
R5712
42.2
R6342
10.0K
9ZML1252EKILF
U117
VDDA1
GN
DA
2
^SEL_A_B#3
^VHIBW_BYPM_LOBW#4 CKPWRGD_PD#5
DIF_INB6
DIF_INB#7
GN
D1
8
VDDR9
DIF_INA10
DIF_INA#11
VSADR0_TRI12
SMBDAT13
SMBCLK14
VSADR1_TRI15
NC116
FBOUT_NC#17 FBOUT_NC18
^OE0#19
^OE1#20
NC221
GN
D2
22
DIF_023
DIF_0#24
DIF_125
DIF_1#26
GN
D3
27
VD
D1
28
DIF_229
DIF_2#30
DIF_331
DIF_3#32
NC333
GN
D4
34
^OE2#35
^OE3#36
^OE4#37
^OE5#38
GN
D5
39
VD
DIO
140
DIF_441
DIF_4#42
DIF_543
DIF_5#44
VD
D2
45
GN
D6
46
DIF_647
DIF_6#48
DIF_749
DIF_7#50
GN
D7
51
VD
DIO
252
^OE6#53
^OE7#54
^OE8#55
^OE9#56
NC457
GN
D8
58
DIF_859
DIF_8#60
DIF_961
DIF_9#62
GN
D9
63
VD
D3
64
DIF_1065
DIF_10#66
DIF_1167
DIF_11#68
NC569
GN
D10
70
^OE10#71
^OE11#72
EP
AD
73
R5695 1R
R5742
42.2,DNI
R6608DNI
C1972
0.1uF0402
C198610uF0603
R6329 DNI 0402
C2982
1uF0402
C3015 0.1uF
R6400 84.51%0402
R6478 10.0K
R6482 0
R6491 0
C2997
1uF0402
C20011uF
0402
C19880.1uF
0402
C2016 0.1uF 0402
R5713
42.2,DNI
U190
9DML0451AKILF
DIF_INA1
DIF_INA#2
VD
DR
3.3
3
VD
DR
3.3
4
DIF_INB5
DIF_INB#6
GN
DR
7
vSW_MODE8
^OE0#9
DIF010
DIF0#11
^OE1#12
DIF113
DIF1#14
GN
D15
VD
D3.3
16
DIF217
DIF2#18
^OE2#19
DIF320
DIF3#21
^OE3#22
^SEL_A_B#23
GN
DR
24
EP
AD
25
L43
BLM15AG221SN1
C2981
0.1uF0402
R6412 10.0K
R5740
42.2,DNI
R6313 0
R6325 DNI 0402
C2002 0.1uF 0402
R6345 0
C1973
0.1uF0402
U208
9DML0451AKILF
DIF_INA1
DIF_INA#2
VD
DR
3.3
3
VD
DR
3.3
4
DIF_INB5
DIF_INB#6
GN
DR
7
vSW_MODE8
^OE0#9
DIF010
DIF0#11
^OE1#12
DIF113
DIF1#14
GN
D15
VD
D3.3
16
DIF217
DIF2#18
^OE2#19
DIF320
DIF3#21
^OE3#22
^SEL_A_B#23
GN
DR
24
EP
AD
25
R6403 10.0K
R6477 10.0K
R6609
DNI
C2983
1uF0402
C2017 0.1uF 0402
R5704 2.2R
L50
BLM15AG221SN1
R6384DNI0402
R5715 2.2R
C20000.1uF0402
R5714
42.2,DNI
R6324 0
R6472 0
R638600402
R625810.0K
C20311uF0402
Si5391A-A-GM
U9
IN11
IN1B2
IN_SEL03
IN_SEL14
SYNCB5
RSTB6
X17
XA8
XB9
X210
OEB11
INTRB12
VD
DA
13
IN214
IN2B15
SCLK16
A1/SDO17
SDA/SDIO18
A0/CSB19
OUT0AB20OUT0A21
VD
DO
022
OUT0B23OUT024
FDEC25
VD
DO
126
OUT1B27OUT128
VD
DO
229
OUT2B30OUT231
VD
D1
32
VD
DO
333
OUT3B34OUT335
VD
DO
436
OUT4B37OUT438
I2C_SEL39
VD
DO
540
OUT5B41OUT542
VD
DO
643
OUT6B44OUT645
VD
D2
46
LOLB47
FINC48
VD
DO
749
OUT7B50OUT751
VD
DO
852
OUT8B53OUT854
OUT9B55OUT956
VD
DO
957
OUT9AB58OUT9A59
VD
D3
60
FB_IN61
FB_INB62
IN063
IN0B64
GND65
C2023 0.1uF 0402
R6389
42.2
R6306 0
C2984
1uF0402
C2032 0.1uF 0402
R609110.0K
R6316 0
C2027 0.1uF 0402
Y625.00MHz
13
24
R6385DNI0402
C2019 0.1uF 0402
R6343 0
R6402 84.51%0402
R6314 0
C198110uF0603
C19830.1uF
0402
C2022 0.1uF 0402
C2993
1uF0402
R638700402
R6390
42.2
C2004 0.1uF 0402
C3117 0.1uF
C3017 0.1uF
R5700 1R
R6481 0
C2985
1uF0402
C197510uF0603
R6489 0
L46
BLM15AG221SN1
C2014 0.1uF 0402
C3116 0.1uF
R5696 1R
R571010.0K
L45
BLM15AG221SN1
C19940.1uF0402
C2028 0.1uF 0402
R6682DNI
C2994
1uF0402
R6310 0
R634710.0K
C3223 0.1uF
C3020 0.1uF
C2977
0.1uF0402
C2025 0.1uF 0402
R6326 DNI 0402
C301318pF0402
C3111 0.1uF
C2986
1uF0402
L52BLM18KG601SN1D
U176
9DML0451AKILF
DIF_INA1
DIF_INA#2
VD
DR
3.3
3
VD
DR
3.3
4
DIF_INB5
DIF_INB#6
GN
DR
7
vSW_MODE8
^OE0#9
DIF010
DIF0#11
^OE1#12
DIF113
DIF1#14
GN
D15
VD
D3.3
16
DIF217
DIF2#18
^OE2#19
DIF320
DIF3#21
^OE3#22
^SEL_A_B#23
GN
DR
24
EP
AD
25
C301618pF0402
C19910.1uF0402
R292 0
L53
BLM15AG221SN1
R6320 10.0K
R6339
10.0K
C2988
1uF0402
R6413 1001%0402
R6404 10.0K
R6349 0
C19840.1uF
0402
C2003 0.1uF 0402
C3005
0.1uF0402
C2995
1uF0402
C2978
0.1uF0402
R6331DNI0402
R6683
DNI
R6382 DNI 0402
R6346 0
C2992
1uF0402
R6340
10.0K C197410uF0603
C2006 0.1uF 0402
R6336 0
R6480 0
L47
BLM15AG221SN1
C2989
1uF0402
R6484 0
C3224 0.1uF
R5754 DNI
R6333 DNI 0402
C2026 0.1uF 0402
R5708
42.2
C2996
1uF0402
C2015 0.1uF 0402
C198510uF0603
C3006
0.1uF0402
R6315 0
R6323 DNI 0402
C2979
0.1uF0402
R6332DNI0402
R6321 10.0K
C3018 0.1uF
C196510uF0603
C2998
0.1uF0402
CLK_100M_SI5391_PCLK_100M_SI5391_N
CLK_100M_9ZML1252E_P8CLK_100M_9ZML1252E_N8
CLK_MUX_SEL_0CLK_100M_9ZML1252E_P7 CLK_MUX_SEL_1CLK_100M_9ZML1252E_N7 CLK_SSC0
CLK_SSC1
CLK_100M_TEST_PCLK_100M_TEST_N
CLK0_OEn
CLK0_RSTn
I2C2_SDAI2C2_SCL
CLK_100M_UPI0_REFCLK_EP_PCLK_100M_UPI0_REFCLK_EP_N
CLK_100M_SI5391_PCLK_100M_SI5391_N
VDD_DIFF
CLK_100M_UPI1_REFCLK_EP_PCLK_100M_UPI1_REFCLK_EP_N
VDDA
VDDR
VSADR0VSADR1
CLK_100M_9ZML1252E_P7CLK_100M_9ZML1252E_N7
CLK_100M_9ZML1252E_P8 CLK_100M_UPI2_REFCLK_EP_PCLK_100M_9ZML1252E_N8 CLK_100M_UPI2_REFCLK_EP_N
CLK_100M_TEST_PCLK_100M_TEST_N CLK_100M_9ZML1252E_P9
CLK_100M_9ZML1252E_N9
CLK_100M_9ZML1252E_P10CLK_100M_9ZML1252E_N10
CLK_100M_9ZML1252E_P11CLK_100M_9ZML1252E_N11
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Max 10 System Controller
PUSH BUTTON INTERFACE
MAX10 DIPSWITCH
AVST_READY must be doubleregistered inside MAX10 forsyncronization to AVST_CLK
P1V2
1.8V 3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
USB Blaster II
FPGA S10 interface
3.3V
CLOCK
1.8V
S10 Jtag
I2C MASTER 1 AND 2
MAX16550 HSC interface
EXT UBII JTAG_Header
BMC JTAG from PCIE Conn
PWR SEQUENCE
QSPI FLASH
IO Expander to MAX10
3.3V
AVST x8
PCIe I2C
FAN CONTROL
ENABLE VREF DDR4
UPI
VCCcore AVS Bus
VCC = 2.7V - 3.6VAbsmax = 4.6V
NIOS Flash
PGM CONFIG & PGM SEL ONLY FOR DEBUG
PULL UP/DOWN OPTIONS FOR BUS CONFIGURATION BETWEEN MAX10 AND FPGA
64M-Bit Serial Flash
1-8 : JTAG DEBUG MODE
CLOSE(0)
2-7 : JTAG_INPUT_SOURCE
OPEN(1)
PCIe BMC On-Board UBII (Default)
SW33 Position
3-6 : UPI MODE4-5 : MAX10 JTAG ENABLE
Normal ModeI (Default) EXT BUII
USB_DISABLEn = 0 : External JTAGUSB_DISABLEn = 1 : On-Board UBII/PCIe EP Edge
(TMS)(TCK)
(TDI)(TDO)
0 = NC <--> COM 1 = NO <--> COM
JTAG for MAX10 pass through JTAG for MAX10 update2 Sockets (default) 4 Sockets
M10_1V2_VCCDPLL
M10_1V2_VCCDPLL
MAX10_VCC_1.2V
MAX10_VCC_1.2V
MAX10_VCC_1.2V
MAX10_VCCIO_1.8V
MAX10_VCCIO_1.8V
MAX10_VCCIO_2.5V
MAX10_VCCIO_1.8V
MAX10_VCC_1.2V M10_VCCINT
M10_VCCINT
MAX10_VCCA_2.5V
MAX10_VCCA_ADC_2.5V
MAX10_VCCA_ADC_2.5VMAX10_VCCA_2.5V
MAX10_VCCIO_1.8V
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
1.8V
I2C2_SCL 6,7,22,69I2C2_SDA 6,7,22,69
CPU_RESETn 9,31
CLK0_OEn 22
MAX_RESETn 31MAX_CONF_DONE 31
MSEL0 6MSEL1 6MSEL2 6
FPGA_PR_REQUEST 12
FAN_PWM 33
FPGA_PR_ERROR 12
TSENSE_ALERTn 33,68OVERTEMPn 33
FX2_PA[7:0] 32
USB_T_CLK 32FX2_FLAGA 32
FX2_SCL 32FX2_SDA 32
FX2_SLRDn 32FX2_SLWRn 32FX2_RESETn 32
FX2_PB[7:0] 32FX2_PD[7:0] 32
FX2_FLAGB 32FX2_FLAGC 32
S10_1V8_TMS 6S10_1V8_TDO 6
S10_1V8_TDI 6S10_1V8_TCK 6
AUX2_HSC_FAULT_N 49
PCIE_HSC_FAULT_N 55AUX2_HSC_ALERT_N 49
PCIE_HSC_ALERT_N 55
BMC_BUF_TCK 21BMC_BUF_TDI 21
BMC_BUF_TDO 21BMC_BUF_TMS 21
QSPI_M10_DATA1 6QSPI_M10_DATA0 6
QSPI_M10_DATA2 6QSPI_M10_DATA3 6
QSPI_M10_CLK 6QSPI_M10_CS_N 6QSPI_M10_RESETN 6
PCIE_3V3_BMC_RST_N 21
AVST8_DATA[0..7] 6
AVST8_CLK 6AVST8_VALID 6AVST8_READY 6
AUX2_HSC_MAX10_PG 49PCIE_HSC_MAX10_PG 553.3V_REG_INST_PG 63
VCC_PG 58
VCCERAM_PG 62
3.3V_REG_PG 63
1.8V_PG 50
DDR4_CH00_PG 67
2.5V_DDR4_CH00_PG 65
DDR4_CH11_PG 66
VCCFUSE_PG 64
VCCIO_1V8_PG 51
PCIE_EDGE_SMBCLK 21PCIE_EDGE_SMBDAT 21
I2C1_SDA 42,49,55,63,68I2C1_SCL 42,49,55,63,68
VCC_EN 53,58VCCERAM_EN 53,62
1.8V_EN 50,533.3V_REG_EN 53,63DDR4_CH00_EN 53,67DDR4_CH11_EN 53,66
VCCFUSE_EN 642.5V_DDR4_CH00_EN 53,65
CLK0_RSTn 22
QSPI_AVST_SEL 6
CLK0_LOL 22
0V6_DDR4_VREF_CH00_PG 650V6_DDR4_VREF_CH11_PG 65
PCIE_EDGE_WAKEn 21,68
FPGA_PR_DONE 12
MAX10_PS_ON 49
2.5V_DDR4_CH11_PG 65
VCCH_GXP_PG 45VCCH_GXE_PG 44
I2C3_SDA 7,33I2C3_SCL 7,33
M10_DATA[3:0] 68
VCCH_GXP_EN 45,53
VCCH_GXE_EN 44,53VCCCLK_GXE_EN 46,53
VCCIO_1V8_EN 51,532.5V_DDR4_CH11_EN 53,65
FAN_TACH 33
0V6_DDR4_VREF_CH00_EN 650V6_DDR4_VREF_CH11_EN 65
VCCRT_GXE_EN 53
AVS_SDA 58AVS_MDA 58AVS_CLK 58
TWARN_0V89_FPGA 58
PCIE_3V3_BMC_PERST_N 21
M10_SSN 68M10_CLK 68M10_GPIO1 68M10_GPIO0 68
PWRGD_OUT 31
USB_PHY_RESETn 32
VCCCLK_GXE_PG 46
USB_FPGA_CLK 9
FPGA_1V8_nCONFIG 6FPGA_1V8_nSTATUS 6FPGA_1V8_INIT_DONE 6FPGA_1V8_CONF_DONE 6
FPGA_CONF_DONE_LED 31
UPI_MODE 17
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
23 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
23 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
23 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C109
0.1uF0402
C137
0.1uF0402
R6709 10.0K
R6288 10.0K
R406 10.0K
J2
70247-1051
2468
10
13579
R89 0
C105
0.1uF0402
R439 10.0K
R6439 4.70K 1%0402
R6449 10.0K,DNI
C106
0.1uF0402
C172
0.1uF0402
C3160 0.1uF0402 25V
X6S
C136
0.1uF0402
U11-10
10M50DAF256C7G
IO_2_M3/CLK0N/DIFFIO_RX_L28NM3
IO_2_L3/CLK0P/DIFFIO_RX_L28PL3
IO_2_J6/CLK1N/DIFFIO_RX_L36NJ6
IO_2_K6/CLK1P/DIFFIO_RX_L36PK6
IO_2_N2/DPCLK0/DIFFIO_RX_L38NN2
IO_2_P1/DPCLK1/DIFFIO_RX_L38PP1
IO_3_P9/CLK6N/DIFFIO_TX_RX_B18NP9
IO_3_P8/CLK6P/DIFFIO_TX_RX_B18PP8
IO_3_M8/CLK7N/DIFFIO_TX_RX_B20NM8
IO_3_M9/CLK7P/DIFFIO_TX_RX_B20PM9
IO_6_J11/CLK2P/DIFFIO_RX_R38PJ11
IO_6_J12/CLK2N/DIFFIO_RX_R38NJ12
IO_6_J15/CLK3P/DIFFIO_RX_R40PJ15
IO_6_J16/CLK3N/DIFFIO_RX_R40NJ16
IO_6_G11/DPCLK3/DIFFIO_RX_R50P/DQS2RG11
IO_6_G12/DPCLK2/DIFFIO_RX_R50N/DQSN2RG12
IO_8_D9/CLK4P/DIFFIO_RX_T38PD9
IO_8_C9/CLK4N/DIFFIO_RX_T38NC9
IO_8_F9/DIFFIO_RX_T40PF9
IO_8_E9/CLK5N/DIFFIO_RX_T40NE9
IO_1B_J1/VREFB1N0J1
IO_2_M1/VREFB2N0M1
IO_3_T7/VREFB3N0T7
IO_4_T13/VREFB4N0T13
IO_5_R16/VREFB5N0R16
IO_6_B15/VREFB6N0B15
IO_7_A15/VREFB7N0A15
IO_8_A9/VREFB8N0A9
C132
0.1uF0402
R6088 0
R392 0
R669810.0K0402
1%
R6704 10.0K,DNI
X4
125MHzECS-3518-1250-B-TR
VCC4
GND2
OUT3
EN1
R6450 10.0K,DNI
C160
10uF0603
R433 10.0K
C173
0.1uF0402
R6597 0
R510 4.70K 1%0402
U11-1
10M50DAF256C7G
VCC__K8K8
VCC__K10K10
VCC__J9J9
VCC__J8J8
VCC__J7J7
VCC__H9H9
VCC__H8H8
VCC__H10H10
VCC__G9G9
VCC__G7G7
VCCINT__F6F6
VCCD_PLL1__M5M5
VCCD_PLL2__D13D13
VCCD_PLL3__D4D4
VCCD_PLL4__N13N13
VCCIO1A__H4H4
VCCIO1A__G4G4
VCCIO1B__J4J4
VCCIO2__L4L4
VCCIO2__K4K4
VCCIO3__N8N8
VCCIO3__N7N7
VCCIO3__N6N6
VCCIO4__N11N11
VCCIO4__N10N10
VCCIO5__M13M13
VCCIO5__L13L13
VCCIO5__K13K13
VCCIO6__J13J13
VCCIO6__H13H13
VCCIO6__G13G13
VCCIO6__F13F13
VCCIO7__D11D11
VCCIO7__D10D10
VCCIO8__D8D8
VCCIO8__D7D7
VCCIO8__C7C7
VCCA1__L5L5
VCCA2__E12E12
ADC_VREF__E4E4
VCCA3__D5D5
VCCA_ADC__E5E5
VCCA4__M12M12
U41
W25Q64JVSSIM
WSOIC-8
CS1
DO/IO12
WP/IO23
GND4
DI/IO05
CLK6
RST/HLD/IO37
VCC8
R6087 20
R6253 10.0K
U11-11
10M50DAF256C7G
IO_1B_G6/JTAGENG6
IO_1B_H2/TMS/DIFFIO_RX_L17NH2
IO_1B_H3/TCK/DIFFIO_RX_L17PH3
IO_1B_G1/TDI/DIFFIO_RX_L18NG1
IO_1B_H1/TDO/DIFFIO_RX_L18PH1
IO_8_B10/DEV_CLRN/DIFFIO_RX_T42NB10
IO_8_B8/DEV_OE/DIFFIO_RX_T44PB8
IO_8_F8/CONFIG_SELF8
INPUT_ONLY_8_E8/NCONFIGE8
IO_8_C5/CRC_ERROR/DIFFIO_RX_T48NC5
IO_8_F7/NSTATUS/DIFFIO_RX_T50PF7
IO_8_E7/CONF_DONE/DIFFIO_RX_T50NE7
C134
0.1uF0402
R44 4.70K
R320 0
R6703 10.0K
C627
100uFC2012
R6443 4.70K 1%0402
C411
0.1uF0402
R438 10.0K
R6708 10.0K
R6451 10.0K,DNI
U11-2
10M50DAF256C7G
IO_1A_F5/ADC1IN1/DIFFIO_RX_L1NF5
IO_1A_C4/ADC2IN1/DIFFIO_RX_L2NC4
IO_1A_F4/ADC1IN2/DIFFIO_RX_L1PF4
IO_1A_C3/ADC2IN8/DIFFIO_RX_L2PC3
IO_1A_H5/ADC1IN3/DIFFIO_RX_L3NH5
IO_1A_E3/ADC2IN3/DIFFIO_RX_L4NE3
IO_1A_G5/ADC1IN4/DIFFIO_RX_L3PG5
IO_1A_F2/ADC2IN4/DIFFIO_RX_L4PF2
IO_1A_G2/ADC1IN5/DIFFIO_RX_L5NG2
IO_1A_C2/ADC2IN5/DIFFIO_RX_L6NC2
IO_1A_F1/ADC1IN6/DIFFIO_RX_L5PF1
IO_1A_B2/ADC2IN6/DIFFIO_RX_L6PB2
IO_1A_E1/ADC1IN7/DIFFIO_RX_L7NE1
IO_1A_B1/ADC2IN7/DIFFIO_RX_L8NB1
IO_1A_D1/ADC1IN8/DIFFIO_RX_L7PD1
IO_1A_C1/ADC2IN2/DIFFIO_RX_L8PC1
IO_1B_J5/DIFFIO_RX_L20NJ5
IO_1B_H6/DIFFIO_RX_L20PH6
IO_1B_J3/DIFFIO_RX_L22NJ3
IO_1B_J2/DIFFIO_RX_L22PJ2
C162
0.1uF0402
R440 10.0K
R200 20
R90 0
R5581 20
R393 0
C165
0.1uF0402
R298 22.0
R322 0
R5400 10.0K
C316
2.2uF0603
C102
0.1uF0402
R511 4.70K 1%0402
R6440 4.70K 1%0402
R437 10.0K
U11-5
10M50DAF256C7G
IO_4_M11/PLL_B_CLKOUTN/DIFFIO_TX_RX_B57NM11
IO_4_L10/PLL_B_CLKOUTP/DIFFIO_TX_RX_B57PL10
IO_4_P10/DIFFIO_TX_RX_B34NP10
IO_4_R11/DIFFIO_RX_B35NR11
IO_4_P11/DIFFIO_TX_RX_B34PP11
IO_4_R12/DIFFIO_RX_B35PR12
IO_4_M10/DIFFIO_TX_RX_B36NM10
IO_4_L9/DIFFIO_TX_RX_B36PL9
IO_4_T12T12
IO_4_P13/DIFFIO_TX_RX_B37NP13
IO_4_P12/DIFFIO_TX_RX_B37PP12
L49
BLM15AG221SN1
C481uF040225VX5R
R389 0
R445 10.0K
R505 20
R6711240 0402
1%
C184 0.1uF0402 25V
X6S
C131
0.1uF0402
R4110.0K04021%
C176
10uF0603
TP3TESTPOINT
1TP
U11-7
10M50DAF256C7G
IO_6_D14/PLL_R_CLKOUTP/DIFFIO_RX_R69PD14
IO_6_C14/PLL_R_CLKOUTN/DIFFIO_RX_R69NC14
IO_6_J14/DIFFIO_RX_R39PJ14
IO_6_K15/DIFFIO_RX_R39NK15
IO_6_H15/DIFFIO_RX_R41PH15
IO_6_H16/DIFFIO_RX_R41NH16
IO_6_D16/DIFFIO_RX_R42PD16
IO_6_C16/DIFFIO_RX_R42NC16
IO_6_H11/DIFFIO_RX_R44P/DQ2RH11
IO_6_H12/DIFFIO_RX_R44N/DQ2RH12
IO_6_G14/DIFFIO_RX_R46P/DQ2RG14
IO_6_G16/DIFFIO_RX_R47P/DQ2RG16
IO_6_G15/DIFFIO_RX_R46N/DM2RG15
IO_6_F16/DIFFIO_RX_R47N/DQ2RF16
IO_6_B16B16
IO_6_F14/DIFFIO_RX_R51P/DQ2RF14
IO_6_E15/DIFFIO_RX_R52P/DQ2RE15
IO_6_E14/DIFFIO_RX_R51N/DQ2RE14
IO_6_E16/DIFFIO_RX_R52N/DQ2RE16
IO_6_D15/DIFFIO_RX_R70P/CK_6D15
IO_6_C15/DIFFIO_RX_R70N/CK#_6C15
U49
TS3A5018RSVR
UQFN-16
COM12
COM25
COM37
COM410
NO11
NO24
NO38
NO411
NC116
NC23
NC39
NC412
EN13
GND6
IN15
V+14
C171
0.1uF0402
C144
0.1uF0402
U11-12
10M50DAF256C7G
GND__A1A1
GND__A16A16
GND__B14B14
GND__C11C11
GND__C8C8
ANAIN1__D2D2
GND__D3D3
GND__D6D6
GND__E13E13
REFGND__E2E2
GND__E6E6
GND__F15F15
ANAIN2__F3F3
GND__G10G10
GND__G3G3
GND__G8G8
GND__H14H14
GND__H7H7
GND__J10J10
GND__K1K1
GND__K16K16
GND__K3K3
GND__K7K7
GND__K9K9
GND__L14L14
GND__M4M4
GND__N12N12
GND__N15N15
GND__N9N9
GND__P3P3
GND__P7P7
GND__R13R13
GND__T1T1
GND__T10T10
GND__T16T16
R3710.0K0402
1%
C129
0.1uF0402
R6073 20
R4010.0K0402
1%
U11-6
10M50DAF256C7G
IO_5_P14/RUP/DIFFIO_RX_R1PP14
IO_5_R14/RDN/DIFFIO_RX_R1NR14
IO_5_T14/DIFFIO_RX_R2PT14
IO_5_T15/DIFFIO_RX_R2NT15
IO_5_L11/DIFFIO_RX_R25P/DQ1RL11
IO_5_L12/DIFFIO_RX_R25N/DQ1RL12
IO_5_N14/DIFFIO_RX_R27P/DQ1RN14
IO_5_M15/DIFFIO_RX_R28P/DQ1RM15
IO_5_P15/DIFFIO_RX_R27N/DM1RP15
IO_5_M14/DIFFIO_RX_R28N/DQ1RM14
IO_5_N16/DIFFIO_RX_R29PN16
IO_5_R15R15
IO_5_P16/DIFFIO_RX_R29NP16
IO_5_K11/DIFFIO_RX_R30P/DQ1RK11
IO_5_K12/DIFFIO_RX_R30N/DQ1RK12
IO_5_K14/DIFFIO_RX_R32P/DQS1RK14
IO_5_M16/DIFFIO_RX_R33P/DQ1RM16
IO_5_L15/DIFFIO_RX_R32N/DQSN1RL15
IO_5_L16/DIFFIO_RX_R33N/DQ1RL16
C139
0.1uF0402
C410
0.1uF0402
R86 0
R432 10.0KR430 10.0K
R6252 10.0K
C168
0.1uF0402
R394 0
R6089 0
U11-8
10M50DAF256C7G
IO_7_D12/DIFFIO_RX_T1PD12
IO_7_C13/DIFFIO_RX_T2PC13
IO_7_E11/DIFFIO_RX_T1NE11
IO_7_C12/DIFFIO_RX_T2NC12
IO_7_F11/DIFFIO_RX_T17PF11
IO_7_A14A14
IO_7_F12/DIFFIO_RX_T17NF12
IO_7_F10/DIFFIO_RX_T28PF10
IO_7_E10/DIFFIO_RX_T28NE10
IO_7_B13/DIFFIO_RX_T30PB13
IO_7_A13/DIFFIO_RX_T30NA13
R49310.0K0402
1%
C104
0.1uF0402
R197 20
R513 4.70K 1%0402
C169
0.1uF0402
C107
0.1uF0402
R528 20
R670510.0K0402
1%
OPEN
SW33
TDA04H0SB1
12345
678
R6441 4.70K 1%0402
C164
0.1uF0402
C163
0.1uF0402
R429 10.0K
C142
0.1uF0402
R297 10.0K
R47010.0K0402
1%
C174
0.1uF0402
R42810.0K04021%
C103
0.1uF0402
R6077 20
L48
BLM15AG221SN1
R6444 10.0K,DNI
C135
0.1uF0402
C167
0.1uF0402
R443 10.0K
C130
0.1uF0402
R6445 10.0K,DNI
R6287 10.0K
L42
BLM15AG221SN1
R395 0
C133
0.1uF0402
C138
0.1uF0402
R1610.0K,DNI
04021%
R199 20
C490.1uF040225VX7R
U11-3
10M50DAF256C7G
IO_2_N3/PLL_L_CLKOUTN/DIFFIO_RX_L59NN3
IO_2_N4/PLL_L_CLKOUTP/DIFFIO_RX_L59PN4
IO_2_L1/DIFFIO_RX_L29NL1
IO_2_K2/DIFFIO_RX_L29PK2
IO_2_M2/DIFFIO_RX_L37NM2
IO_2_L2/DIFFIO_RX_L37PL2
IO_2_N1N1
IO_2_K5/DIFFIO_RX_L41NK5
IO_2_L6/DIFFIO_RX_L41PL6
R6446 10.0K,DNI
R671010.0K0402
1%
C315
2.2uF0603
R6256 20
R388 0
L4
BLM15AG221SN1
R434 10.0K
C145
0.1uF0402
R441 10.0K
U11-9
10M50DAF256C7G
IO_8_B3/PLL_T_CLKOUTP/DIFFIO_RX_T52PB3
IO_8_A4/PLL_T_CLKOUTN/DIFFIO_RX_T52NA4
IO_8_B12/DIFFIO_RX_T41PB12
IO_8_B11/DIFFIO_RX_T41NB11
IO_8_C10/DIFFIO_RX_T42PC10
IO_8_A11/DIFFIO_RX_T43PA11
IO_8_A12/DIFFIO_RX_T43NA12
IO_8_A10A10
IO_8_B7/DIFFIO_RX_T44NB7
IO_8_B9/DIFFIO_RX_T45PB9
IO_8_A8/DIFFIO_RX_T45NA8
IO_8_B6/DIFFIO_RX_T46PB6
IO_8_A7/DIFFIO_RX_T47PA7
IO_8_C6/DIFFIO_RX_T46NC6
IO_8_A6/DIFFIO_RX_T47NA6
IO_8_B5/DIFFIO_RX_T48PB5
IO_8_B4/DIFFIO_RX_T49PB4
IO_8_A5/DIFFIO_RX_T49NA5
IO_8_A3/DIFFIO_RX_T51PA3
IO_8_A2/DIFFIO_RX_T51NA2
C108
0.1uF0402
U11-4
10M50DAF256C7G
IO_3_P4/DIFFIO_TX_RX_B1NP4
IO_3_P2/DIFFIO_RX_B2NP2
IO_3_N5/DIFFIO_TX_RX_B1PN5
IO_3_R1/DIFFIO_RX_B2PR1
IO_3_M6/DIFFIO_TX_RX_B3NM6
IO_3_R3/DIFFIO_RX_B4NR3
IO_3_L7/DIFFIO_TX_RX_B3PL7
IO_3_R2/DIFFIO_RX_B4PR2
IO_3_R4/DIFFIO_TX_RX_B5NR4
IO_3_T3/DIFFIO_RX_B6NT3
IO_3_P5/DIFFIO_TX_RX_B5PP5
IO_3_T2/DIFFIO_RX_B6PT2
IO_3_R6/DIFFIO_TX_RX_B13NR6
IO_3_T5/DIFFIO_RX_B14NT5
IO_3_R5/DIFFIO_TX_RX_B13PR5
IO_3_T4/DIFFIO_RX_B14PT4
IO_3_M7/DIFFIO_TX_RX_B15NM7
IO_3_L8/DIFFIO_TX_RX_B15PL8
IO_3_T6T6
IO_3_R7/DIFFIO_TX_RX_B16NR7
IO_3_T8/DIFFIO_RX_B17NT8
IO_3_P6/DIFFIO_TX_RX_B16PP6
IO_3_R8/DIFFIO_RX_B17PR8
IO_3_T9/DIFFIO_RX_B19NT9
IO_3_R9/DIFFIO_RX_B19PR9
IO_3_T11/DIFFIO_TX_RX_B22NT11
IO_3_R10/DIFFIO_TX_RX_B22PR10
X3
50MHzECS-3518-500-B-xx
VCC4
GND2
OUT3
EN1
C141
0.1uF0402
R442 10.0K
R660010.0K0402
1%
R6447 10.0K,DNI
C143
0.1uF0402
C140
0.1uF0402
R6080 20
R72 10
R300 22.0
R203240 0402
1%
R6442 4.70K 1%0402
C161
10uF0603
R6448 10.0K,DNI
C170
0.1uF0402
C193
0.1uF0402
C166
10uF0603
C128
0.1uF0402
R444 10.0K
MAX10_CONF_DONE
AVST8_CLK
FPGA_PR_ERRORFPGA_PR_DONEFPGA_PR_REQUEST
I2C1_SCLI2C1_SDA
FX2_PA0FX2_PA1FX2_PA2FX2_PA3FX2_PA4FX2_PA5FX2_PA6FX2_PA7FX2_PB0FX2_PB1FX2_PB2FX2_PB3FX2_PB4FX2_PB5FX2_PB6FX2_PB7
FX2_FLAGCFX2_FLAGBFX2_FLAGA
FX2_RESETn
FX2_PD4FX2_PD5
CLK0_OEN
USB_DISABLEn
MAX10_JTAGEN
FX2_PD6FX2_PD7
FX2_SLWRnFX2_SLRDnFX2_SDAFX2_SCL
USB_DISABLEn
EXT_UBII_TCKEXT_UBII_TDOEXT_UBII_TMS
EXT_UBII_TDI
AVS_MDAAVS_CLK
PCIE_HSC_ALERT_NPCIE_HSC_FAULT_NAUX2_HSC_ALERT_NAUX2_HSC_FAULT_N
CLK_MAX10_50M
CLK_MAX10_50M
MAX_CONF_DONE
QSPI_M10_DATA0
QSPI_M10_DATA3QSPI_M10_DATA2QSPI_M10_DATA1
MAX_RESETNFAN_PWM
QSPI_M10_CLKQSPI_M10_CS_N
QSPI_M10_RESETN
PCIE_3V3_BMC_RST_N
MSEL0
I2C2_SCLI2C2_SDA
AVST8_DATA0AVST8_DATA1AVST8_DATA2AVST8_DATA3AVST8_DATA4AVST8_DATA5AVST8_DATA6AVST8_DATA7
AVST8_READYAVST8_VALID
M10_DATA2M10_DATA0
M10_DATA0
AUX2_HSC_MAX10_PGPCIE_HSC_MAX10_PG3.3V_REG_INST_PGVCC_PGVCCERAM_PG
1.8V_PG
2.5V_DDR4_CH00_PG3.3V_REG_PG
VCCIO_1V8_PGDDR4_CH11_PGDDR4_CH00_PGVCCFUSE_PG
PCIE_EDGE_SMBDATPCIE_EDGE_SMBCLK
ADC_VREF
FAN_TACH
QSPI_AVST_SEL
CLK0_LOL
0V6_DDR4_VREF_CH00_PG0V6_DDR4_VREF_CH11_PG
MSEL1
PCIE_EDGE_WAKEn
S10_1V8_TDIS10_1V8_TMSS10_1V8_TCKS10_1V8_TDO
MSEL2
CLK_125M_LVC1_MAX10
M10_DATA3M10_SSN
MAX10_PS_ON
M10_CLKM10_GPIO1
0V6_DDR4_VREF_CH00_EN0V6_DDR4_VREF_CH11_EN
VCCH_GXP_EN
VCCH_GXE_EN
VCCCLK_GXE_EN
2.5V_DDR4_CH11_EN
I2C3_SCLI2C3_SDA
M10_DATA1
M10_GPIO0
M10_DATA1M10_DATA2M10_DATA3M10_SSNM10_CLKM10_GPIO1M10_GPIO0
CLK_125M_LVC1_MAX10
AVS_SDA
TWARN_0V89_FPGA
PCIE_3V3_BMC_PERST_N
SPI_CS#
SPI_DQ1 SPI_DQ3
SPI_DQ2 SPI_CLK
SPI_DQ0
SPI_CS#SPI_CLKSPI_DQ0SPI_DQ1
OVERTEMPnTSENSE_ALERTn
BMC_BUF_TCKBMC_BUF_TDI
CPU_RESETnBMC_BUF_TMS
USB_PHY_RESETn
USB_MAX_JTAGSEL
USB_FPGA_CLK
VCCH_GXE_PGVCCH_GXP_PG
SPI_DQ2SPI_DQ3
2.5V_DDR4_CH11_PG
JTAG_INPUT_SOURCE
JTAG_INPUT_SOURCE
USB_T_CLK
MAX10_CONFIG_SEL
MAX10_CONFIG_SEL
FPGA_1V8_nCONFIGFPGA_1V8_nSTATUSFPGA_1V8_INIT_DONEFPGA_1V8_CONF_DONE
FPGA_CONF_DONE_LED
MAX10_JTAGEN
USB_MAX_TCKUSB_MAX_TMSUSB_MAX_TDI
FX2_PD0 USB_MAX_TDOFX2_PD1FX2_PD2FX2_PD3
USB_MAX_JTAGSEL
USB_MAX_TMSUSB_MAX_TCKUSB_MAX_TDIUSB_MAX_TDO
MAX10_NCONFIGMAX10_NSTATUS
MAX10_NSTATUS
MAX10_NCONFIG
MAX10_CONF_DONE
BMC_BUF_TDO
EXT_UBII_TCKEXT_UBII_TMSEXT_UBII_TDIEXT_UBII_TDO
EXT_UBII_TCKEXT_UBII_TDOEXT_UBII_TMSEXT_UBII_TDI
USB_MAX_JTAGSEL
VCC_ENVCCERAM_ENPWRGD_OUTVCCRT_GXE_EN
1.8V_EN3.3V_REG_ENDDR4_CH00_ENDDR4_CH11_EN2.5V_DDR4_CH00_ENVCCFUSE_ENVCCIO_1V8_ENCLK0_RSTn
UPI_MODE
UPI_MODE
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10DX Devkit Board Diagram
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
24 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
24 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
24 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A ATDV UPI0
UPI0 LINKS
Note:LSIO signals carry 3.3V in PCIe mode or 1.8V in UPI mode.Default mode is PCIe
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
UPI0_CPU_FPGA_DP[19:0] 15UPI0_CPU_FPGA_DN[19:0] 15
UPI0_FPGA_CPU_DP[19:0] 15UPI0_FPGA_CPU_DN[19:0] 15
UPI0_LSIO_TX[6:1] 12
UPI0_LSIO_RX[6:1] 12
UPI0_PRNSTn_3V3 68UPI0_PERSTn 68UPI0_SDA_3V3 68UPI0_SCL_3V3 68UPI0_NID0_3V3 68UPI0_NID1_3V3 68
CLK_100M_UPI0_REFCLK_RP_P 22CLK_100M_UPI0_REFCLK_RP_N 22
CLK_100M_UPI0_REFCLK_EP_N 22CLK_100M_UPI0_REFCLK_EP_P 22
UPI0_LSIO_RX1_PCIE 69UPI0_LSIO_RX2_PCIE 69UPI0_LSIO_RX5_PCIE 69UPI0_LSIO_RX6_PCIE 69
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
25 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
25 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
25 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R6146 10.0K0402 1%
U10-G274-250T
J65
A1A1
A2A2
A3A3
A4A4
A5A5
A6A6
A7A7
A8A8
A9A9
A10A10
A11A11
A12A12
A13A13
A14A14
A15A15
A16A16
A17A17
A18A18
A19A19
A20A20
A21A21
A22A22
A23A23
A24A24
A25A25
A26A26
A27A27
A28A28
A29A29
A30A30
A31A31
A32A32
A33A33
A34A34
A35A35
A36A36
A37A37
MH1MH1
MH2MH2
B1B1
B2B2
B3B3
B4B4
B5B5
B6B6
B7B7
B8B8
B9B9
B10B10
B11B11
B12B12
B13B13
B14B14
B15B15
B16B16
B17B17
B18B18
B19B19
B20B20
B21B21
B22B22
B23B23
B24B24
B25B25
B26B26
B27B27
B28B28
B29B29
B30B30
B31B31
B32B32
B33B33
B34B34
B35B35
B36B36
B37B37
MH3MH3
MH4MH4
R97 0
R6140
100K
R95 DNI
R106 DNI
R6292 DNI
R101 DNI
R6124
4.70K
R6559 DNI
R92 0
R105 DNI
R6561
4.70K
ON
SW19
CVS-01TB
1 2
R6566 DNI
R107 DNI
R99 0
R104 DNI
R96 DNI
R100 0
R108 DNI
R6564 DNI
R6123
4.70K
R6152 10.0K0402 1%
R6560
4.70K
R93 0
R6565
4.70K
R98 0
R6293 DNI
U10-G274-250T
J55
A1A1
A2A2
A3A3
A4A4
A5A5
A6A6
A7A7
A8A8
A9A9
A10A10
A11A11
A12A12
A13A13
A14A14
A15A15
A16A16
A17A17
A18A18
A19A19
A20A20
A21A21
A22A22
A23A23
A24A24
A25A25
A26A26
A27A27
A28A28
A29A29
A30A30
A31A31
A32A32
A33A33
A34A34
A35A35
A36A36
A37A37
MH1MH1
MH2MH2
B1B1
B2B2
B3B3
B4B4
B5B5
B6B6
B7B7
B8B8
B9B9
B10B10
B11B11
B12B12
B13B13
B14B14
B15B15
B16B16
B17B17
B18B18
B19B19
B20B20
B21B21
B22B22
B23B23
B24B24
B25B25
B26B26
B27B27
B28B28
B29B29
B30B30
B31B31
B32B32
B33B33
B34B34
B35B35
B36B36
B37B37
MH3MH3
MH4MH4
R6563
4.70K
R94 DNI
R111 DNI
R6562 DNI
R103 DNI
R102 DNI
UPI0_LSIO_TX1
UPI0_LSIO_RX6_CON
UPI0_LSIO_RX5_CON
UPI0_LSIO_RX2_CON
UPI0_LSIO_RX1_CON
UPI0_SDA_3V3
UPI0_FPGA_CPU_DN19UPI0_FPGA_CPU_DP19
UPI0_FPGA_CPU_DN17UPI0_FPGA_CPU_DP17
UPI0_FPGA_CPU_DN15UPI0_FPGA_CPU_DP15
UPI0_FPGA_CPU_DP13UPI0_FPGA_CPU_DN13
UPI0_FPGA_CPU_DN11UPI0_FPGA_CPU_DP11
UPI0_FPGA_CPU_DN9UPI0_FPGA_CPU_DP9
UPI0_FPGA_CPU_DN7
UPI0_FPGA_CPU_DP5UPI0_FPGA_CPU_DN5
UPI0_FPGA_CPU_DP7
UPI0_FPGA_CPU_DN3UPI0_FPGA_CPU_DP3
UPI0_FPGA_CPU_DP1
UPI0_LSIO_TX6_CON
UPI0_FPGA_CPU_DN1
UPI0_LSIO_TX5_CON
UPI0_LSIO_TX3_CONUPI0_LSIO_TX4_CON
UPI0_LSIO_RX6
UPI0_FPGA_CPU_DN18UPI0_FPGA_CPU_DP18
UPI0_LSIO_RX5
UPI0_FPGA_CPU_DN14
UPI0_FPGA_CPU_DP16UPI0_FPGA_CPU_DN16
UPI0_FPGA_CPU_DP10UPI0_FPGA_CPU_DN10
UPI0_FPGA_CPU_DN12UPI0_FPGA_CPU_DP12
UPI0_FPGA_CPU_DP14
UPI0_FPGA_CPU_DN6
UPI0_FPGA_CPU_DP8UPI0_FPGA_CPU_DN8
UPI0_FPGA_CPU_DP6
UPI0_FPGA_CPU_DN4UPI0_FPGA_CPU_DP4
UPI0_FPGA_CPU_DN0
UPI0_LSIO_TX2_CON
UPI0_FPGA_CPU_DP0
UPI0_FPGA_CPU_DP2UPI0_FPGA_CPU_DN2
UPI0_LSIO_TX1_CON
UPI0_CPU_FPGA_DN19UPI0_CPU_FPGA_DP19
UPI0_CPU_FPGA_DP17UPI0_CPU_FPGA_DN17
UPI0_CPU_FPGA_DN15UPI0_CPU_FPGA_DP15
UPI0_CPU_FPGA_DN13UPI0_CPU_FPGA_DP13
UPI0_CPU_FPGA_DP11UPI0_CPU_FPGA_DN11
UPI0_CPU_FPGA_DP9UPI0_CPU_FPGA_DN9
UPI0_CPU_FPGA_DN7
UPI0_CPU_FPGA_DP5UPI0_CPU_FPGA_DN5
UPI0_CPU_FPGA_DP7
UPI0_CPU_FPGA_DN3UPI0_CPU_FPGA_DP3
UPI0_LSIO_RX4
UPI0_LSIO_RX2
UPI0_LSIO_RX1
UPI0_LSIO_RX6_CON
UPI0_CPU_FPGA_DN1UPI0_CPU_FPGA_DP1
UPI0_LSIO_RX5_CON
UPI0_LSIO_RX4_CONUPI0_LSIO_RX3_CON
UPI0_CPU_FPGA_DN18UPI0_CPU_FPGA_DP18
UPI0_CPU_FPGA_DN14
UPI0_CPU_FPGA_DN16UPI0_CPU_FPGA_DP16
UPI0_CPU_FPGA_DP12UPI0_CPU_FPGA_DN12
UPI0_CPU_FPGA_DP14
UPI0_CPU_FPGA_DN10UPI0_CPU_FPGA_DP10
UPI0_CPU_FPGA_DP6
UPI0_CPU_FPGA_DN4UPI0_CPU_FPGA_DP4
UPI0_CPU_FPGA_DN6
UPI0_CPU_FPGA_DN8UPI0_CPU_FPGA_DP8
UPI0_CPU_FPGA_DP2UPI0_CPU_FPGA_DN2
UPI0_CPU_FPGA_DP0UPI0_CPU_FPGA_DN0
UPI0_LSIO_RX2_CONUPI0_LSIO_RX1_CON
UPI0_LSIO_RX3
UPI0_LSIO_TX1_CON UPI0_PRNSTn_3V3
UPI0_PERSTnUPI0_LSIO_TX2_CON
UPI0_LSIO_TX2
UPI0_LSIO_TX3UPI0_LSIO_TX3_CONUPI0_LSIO_TX4UPI0_LSIO_TX4_CON
UPI0_LSIO_TX5_CON
UPI0_LSIO_TX5
UPI0_LSIO_TX6_CON
UPI0_LSIO_TX6
UPI0_SCL_3V3
UPI0_LSIO_RX3_CON
UPI0_NID0_3V3
UPI0_NID1_3V3
UPI0_LSIO_RX4_CON
CLK_100M_UPI0_REFCLK_RP_NCLK_100M_UPI0_REFCLK_RP_P
CLK_100M_UPI0_REFCLK_EP_PCLK_100M_UPI0_REFCLK_EP_N
UPI0_LSIO_RX1_PCIE
UPI0_LSIO_RX2_PCIE
UPI0_LSIO_RX5_PCIE
UPI0_LSIO_RX6_PCIE
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
UPI1 LINK
TDV UPI1
Note:LSIO signals carry 3.3V in PCIe mode or 1.8V in UPI mode.Default mode is PCIe
UPI1 ONLY SUPPOR SLAVE EP PCIE OR UPI SLAVE MODE ON FPGA INTERFACE
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
UPI1_CPU_FPGA_DP[19:0] 16UPI1_CPU_FPGA_DN[19:0] 16
UPI1_FPGA_CPU_DP[19:0] 16UPI1_FPGA_CPU_DN[19:0] 16
UPI1_LSIO_TX[6:1] 9
UPI1_LSIO_RX[6:1] 9
UPI1_PRNSTn_3V3 68UPI1_PERSTn 68UPI1_SDA_3V3 68UPI1_SCL_3V3 68UPI1_NID0_3V3 68UPI1_NID1_3V3 68
CLK_100M_UPI1_REFCLK_EP_P 22CLK_100M_UPI1_REFCLK_EP_N 22
UPI1_LSIO_RX1_PCIE 69UPI1_LSIO_RX2_PCIE 69UPI1_LSIO_RX5_PCIE 69UPI1_LSIO_RX6_PCIE 69
CLK_100M_UPI1_REFCLK_RP_P 22CLK_100M_UPI1_REFCLK_RP_N 22
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
26 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
26 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
26 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R74 DNI
R6567 DNI
R6180 10.0K0402 1%
R6294 DNI
U10-G274-250T
J38
A1A1
A2A2
A3A3
A4A4
A5A5
A6A6
A7A7
A8A8
A9A9
A10A10
A11A11
A12A12
A13A13
A14A14
A15A15
A16A16
A17A17
A18A18
A19A19
A20A20
A21A21
A22A22
A23A23
A24A24
A25A25
A26A26
A27A27
A28A28
A29A29
A30A30
A31A31
A32A32
A33A33
A34A34
A35A35
A36A36
A37A37
MH1MH1
MH2MH2
B1B1
B2B2
B3B3
B4B4
B5B5
B6B6
B7B7
B8B8
B9B9
B10B10
B11B11
B12B12
B13B13
B14B14
B15B15
B16B16
B17B17
B18B18
B19B19
B20B20
B21B21
B22B22
B23B23
B24B24
B25B25
B26B26
B27B27
B28B28
B29B29
B30B30
B31B31
B32B32
B33B33
B34B34
B35B35
B36B36
B37B37
MH3MH3
MH4MH4
R6569
4.70K
R6187 10.0K0402 1%
U10-G274-250T
J40
A1A1
A2A2
A3A3
A4A4
A5A5
A6A6
A7A7
A8A8
A9A9
A10A10
A11A11
A12A12
A13A13
A14A14
A15A15
A16A16
A17A17
A18A18
A19A19
A20A20
A21A21
A22A22
A23A23
A24A24
A25A25
A26A26
A27A27
A28A28
A29A29
A30A30
A31A31
A32A32
A33A33
A34A34
A35A35
A36A36
A37A37
MH1MH1
MH2MH2
B1B1
B2B2
B3B3
B4B4
B5B5
B6B6
B7B7
B8B8
B9B9
B10B10
B11B11
B12B12
B13B13
B14B14
B15B15
B16B16
B17B17
B18B18
B19B19
B20B20
B21B21
B22B22
B23B23
B24B24
B25B25
B26B26
B27B27
B28B28
B29B29
B30B30
B31B31
B32B32
B33B33
B34B34
B35B35
B36B36
B37B37
MH3MH3
MH4MH4
R60 DNI
R6295 DNI
R56 DNI
R6574 DNI
R76 DNI
R113 0
R73 DNI
R6125
4.70K
R130 0
R6573
4.70K
R6568
4.70K
R53 DNI
R57 DNI
R138 0
R70 DNI
R6572 DNI
R75 0
R109 0
R6570 DNI
R131 0
R6165
100K
R6126
4.70K
ON
SW20
CVS-01TB
1 2
R58 DNI
R6571
4.70K
R54 DNI
R139 0
R77 DNI
UPI1_FPGA_CPU_DN19UPI1_FPGA_CPU_DP19
UPI1_FPGA_CPU_DN17UPI1_FPGA_CPU_DP17
UPI1_FPGA_CPU_DN15UPI1_FPGA_CPU_DP15
UPI1_FPGA_CPU_DP13UPI1_FPGA_CPU_DN13
UPI1_FPGA_CPU_DN11UPI1_FPGA_CPU_DP11
UPI1_FPGA_CPU_DN9UPI1_FPGA_CPU_DP9
UPI1_FPGA_CPU_DN7
UPI1_FPGA_CPU_DP5UPI1_FPGA_CPU_DN5
UPI1_FPGA_CPU_DP7
UPI1_FPGA_CPU_DN3UPI1_FPGA_CPU_DP3
UPI1_FPGA_CPU_DP1
UPI1_LSIO_TX6_CON
UPI1_FPGA_CPU_DN1
UPI1_LSIO_TX5_CON
UPI1_LSIO_TX3_CONUPI1_LSIO_TX4_CON
UPI1_FPGA_CPU_DN18UPI1_FPGA_CPU_DP18
UPI1_FPGA_CPU_DN14
UPI1_FPGA_CPU_DP16UPI1_FPGA_CPU_DN16
UPI1_FPGA_CPU_DP10UPI1_FPGA_CPU_DN10
UPI1_FPGA_CPU_DN12UPI1_FPGA_CPU_DP12
UPI1_FPGA_CPU_DP14
UPI1_FPGA_CPU_DN6
UPI1_FPGA_CPU_DP8UPI1_FPGA_CPU_DN8
UPI1_FPGA_CPU_DP6
UPI1_FPGA_CPU_DN4UPI1_FPGA_CPU_DP4
UPI1_FPGA_CPU_DN0
UPI1_LSIO_TX2_CON
UPI1_FPGA_CPU_DP0
UPI1_FPGA_CPU_DP2UPI1_FPGA_CPU_DN2
UPI1_LSIO_TX1_CON
UPI1_CPU_FPGA_DN19UPI1_CPU_FPGA_DP19
UPI1_CPU_FPGA_DP17UPI1_CPU_FPGA_DN17
UPI1_CPU_FPGA_DN15UPI1_CPU_FPGA_DP15
UPI1_CPU_FPGA_DN13UPI1_CPU_FPGA_DP13
UPI1_CPU_FPGA_DP11UPI1_CPU_FPGA_DN11
UPI1_CPU_FPGA_DP9UPI1_CPU_FPGA_DN9
UPI1_CPU_FPGA_DN7
UPI1_CPU_FPGA_DP5UPI1_CPU_FPGA_DN5
UPI1_CPU_FPGA_DP7
UPI1_CPU_FPGA_DN3UPI1_CPU_FPGA_DP3
UPI1_LSIO_RX6_CON
UPI1_CPU_FPGA_DN1UPI1_CPU_FPGA_DP1
UPI1_LSIO_RX5_CON
UPI1_LSIO_RX4_CONUPI1_LSIO_RX3_CON
UPI1_CPU_FPGA_DN18UPI1_CPU_FPGA_DP18
UPI1_CPU_FPGA_DN14
UPI1_CPU_FPGA_DN16UPI1_CPU_FPGA_DP16
UPI1_CPU_FPGA_DP12UPI1_CPU_FPGA_DN12
UPI1_CPU_FPGA_DP14
UPI1_CPU_FPGA_DN10UPI1_CPU_FPGA_DP10
UPI1_CPU_FPGA_DP6
UPI1_CPU_FPGA_DN4UPI1_CPU_FPGA_DP4
UPI1_CPU_FPGA_DN6
UPI1_CPU_FPGA_DN8UPI1_CPU_FPGA_DP8
UPI1_CPU_FPGA_DP2UPI1_CPU_FPGA_DN2
UPI1_CPU_FPGA_DP0UPI1_CPU_FPGA_DN0
UPI1_LSIO_RX2_CONUPI1_LSIO_RX1_CON
UPI1_LSIO_TX1
UPI1_LSIO_RX2_CON
UPI1_LSIO_RX5_CON
UPI1_LSIO_RX6_CON
UPI1_LSIO_RX1_CON
UPI1_SDA_3V3
UPI1_LSIO_RX6
UPI1_LSIO_RX5
UPI1_LSIO_RX1
UPI1_LSIO_RX4
UPI1_LSIO_RX3
UPI1_PRNSTn_3V3UPI1_LSIO_TX1_CON
UPI1_PERSTnUPI1_LSIO_TX2_CON
UPI1_LSIO_TX2
UPI1_LSIO_TX3UPI1_LSIO_TX3_CONUPI1_LSIO_TX4_CON UPI1_LSIO_TX4
UPI1_LSIO_TX5
UPI1_LSIO_TX5_CONUPI1_LSIO_TX6_CON
UPI1_LSIO_TX6
UPI1_SCL_3V3
UPI1_LSIO_RX3_CON
UPI1_NID0_3V3
UPI1_NID1_3V3
UPI1_LSIO_RX4_CON
CLK_100M_UPI1_REFCLK_EP_NCLK_100M_UPI1_REFCLK_EP_P
UPI1_LSIO_RX6_PCIE
UPI1_LSIO_RX2
UPI1_LSIO_RX1_PCIE
UPI1_LSIO_RX2_PCIE
UPI1_LSIO_RX5_PCIE
CLK_100M_UPI1_REFCLK_RP_NCLK_100M_UPI1_REFCLK_RP_P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
UPI2 LINK
TDV UPI2
Note:LSIO signals carry 3.3V in PCIe mode or 1.8V in UPI mode.Default mode is PCIe
UPI1 ONLY SUPPOR SLAVE EP PCIE OR UPI SLAVE MODE ON FPGA INTERFACE
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG 3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
UPI2_CPU_FPGA_DN[19:0] 16UPI2_CPU_FPGA_DP[19:0] 16
UPI2_FPGA_CPU_DN[19:0] 16UPI2_FPGA_CPU_DP[19:0] 16
UPI2_LSIO_TX[6:1] 9
UPI2_LSIO_RX[6:1] 9
UPI2_PRNSTn_3V3 68UPI2_PERSTn 68UPI2_SDA_3V3 68UPI2_SCL_3V3 68UPI2_NID0_3V3 68UPI2_NID1_3V3 68
CLK_100M_UPI2_REFCLK_EP_N 22CLK_100M_UPI2_REFCLK_EP_P 22
UPI2_LSIO_RX1_PCIE 69UPI2_LSIO_RX2_PCIE 69UPI2_LSIO_RX5_PCIE 69UPI2_LSIO_RX6_PCIE 69
CLK_100M_UPI2_REFCLK_RP_P 22CLK_100M_UPI2_REFCLK_RP_N 22
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
27 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
27 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
27 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R6576 DNI
R81 0
R63 DNI
R6128
4.70K
R6297 DNI
R173 0
R6577
4.70K
R6240 10.0K0402 1%
R6118 0
ON
SW21
CVS-01TB
1 2
R80 DNI
U10-G274-250T
J39
A1A1
A2A2
A3A3
A4A4
A5A5
A6A6
A7A7
A8A8
A9A9
A10A10
A11A11
A12A12
A13A13
A14A14
A15A15
A16A16
A17A17
A18A18
A19A19
A20A20
A21A21
A22A22
A23A23
A24A24
A25A25
A26A26
A27A27
A28A28
A29A29
A30A30
A31A31
A32A32
A33A33
A34A34
A35A35
A36A36
A37A37
MH1MH1
MH2MH2
B1B1
B2B2
B3B3
B4B4
B5B5
B6B6
B7B7
B8B8
B9B9
B10B10
B11B11
B12B12
B13B13
B14B14
B15B15
B16B16
B17B17
B18B18
B19B19
B20B20
B21B21
B22B22
B23B23
B24B24
B25B25
B26B26
B27B27
B28B28
B29B29
B30B30
B31B31
B32B32
B33B33
B34B34
B35B35
B36B36
B37B37
MH3MH3
MH4MH4
R68 DNI
R79 DNI
R6127
4.70K
R6582 DNI
U10-G274-250T
J41
A1A1
A2A2
A3A3
A4A4
A5A5
A6A6
A7A7
A8A8
A9A9
A10A10
A11A11
A12A12
A13A13
A14A14
A15A15
A16A16
A17A17
A18A18
A19A19
A20A20
A21A21
A22A22
A23A23
A24A24
A25A25
A26A26
A27A27
A28A28
A29A29
A30A30
A31A31
A32A32
A33A33
A34A34
A35A35
A36A36
A37A37
MH1MH1
MH2MH2
B1B1
B2B2
B3B3
B4B4
B5B5
B6B6
B7B7
B8B8
B9B9
B10B10
B11B11
B12B12
B13B13
B14B14
B15B15
B16B16
B17B17
B18B18
B19B19
B20B20
B21B21
B22B22
B23B23
B24B24
B25B25
B26B26
B27B27
B28B28
B29B29
B30B30
B31B31
B32B32
B33B33
B34B34
B35B35
B36B36
B37B37
MH3MH3
MH4MH4
R6296 DNI
R6580 DNI
R78 DNI
R61 DNI
R6575
4.70K
R66 DNI
R6206
100K
R174 0
R6116 0
R83 DNI
R6581
4.70K
R6119 0
R6241 10.0K0402 1%
R82 DNI
R69 DNI
R6121 0
R6578 DNI
R67 DNI
UPI2_FPGA_CPU_DN18UPI2_FPGA_CPU_DP18
UPI2_FPGA_CPU_DN14
UPI2_FPGA_CPU_DN16UPI2_FPGA_CPU_DP16
UPI2_FPGA_CPU_DP12UPI2_FPGA_CPU_DN12
UPI2_FPGA_CPU_DP14
UPI2_FPGA_CPU_DN10UPI2_FPGA_CPU_DP10
UPI2_FPGA_CPU_DP6
UPI2_FPGA_CPU_DN4UPI2_FPGA_CPU_DP4
UPI2_FPGA_CPU_DN6
UPI2_FPGA_CPU_DN8UPI2_FPGA_CPU_DP8
UPI2_FPGA_CPU_DP2UPI2_FPGA_CPU_DN2
UPI2_FPGA_CPU_DP0UPI2_FPGA_CPU_DN0
UPI2_LSIO_TX2_CONUPI2_LSIO_TX1_CON
UPI2_FPGA_CPU_DP17UPI2_FPGA_CPU_DN17
UPI2_FPGA_CPU_DN15
UPI2_FPGA_CPU_DP19UPI2_FPGA_CPU_DN19
UPI2_FPGA_CPU_DP11UPI2_FPGA_CPU_DN11
UPI2_FPGA_CPU_DP15
UPI2_FPGA_CPU_DN13UPI2_FPGA_CPU_DP13
UPI2_FPGA_CPU_DP9UPI2_FPGA_CPU_DN9
UPI2_FPGA_CPU_DN7
UPI2_FPGA_CPU_DP5UPI2_FPGA_CPU_DN5
UPI2_FPGA_CPU_DP7
UPI2_LSIO_TX6_CON
UPI2_FPGA_CPU_DN1UPI2_FPGA_CPU_DP1
UPI2_FPGA_CPU_DN3UPI2_FPGA_CPU_DP3
UPI2_LSIO_TX5_CON
UPI2_LSIO_TX4_CONUPI2_LSIO_TX3_CON
UPI2_CPU_FPGA_DN19UPI2_CPU_FPGA_DP19
UPI2_CPU_FPGA_DN15
UPI2_CPU_FPGA_DN17UPI2_CPU_FPGA_DP17
UPI2_CPU_FPGA_DP13UPI2_CPU_FPGA_DN13
UPI2_CPU_FPGA_DP15
UPI2_CPU_FPGA_DN11UPI2_CPU_FPGA_DP11
UPI2_CPU_FPGA_DP7
UPI2_CPU_FPGA_DN5UPI2_CPU_FPGA_DP5
UPI2_CPU_FPGA_DN7
UPI2_CPU_FPGA_DN9UPI2_CPU_FPGA_DP9
UPI2_CPU_FPGA_DP3UPI2_CPU_FPGA_DN3
UPI2_CPU_FPGA_DP1UPI2_CPU_FPGA_DN1
UPI2_LSIO_RX6_CON
UPI2_LSIO_RX3_CONUPI2_LSIO_RX4_CON
UPI2_LSIO_RX5_CON
UPI2_CPU_FPGA_DP16UPI2_CPU_FPGA_DN16
UPI2_CPU_FPGA_DN14
UPI2_CPU_FPGA_DP18UPI2_CPU_FPGA_DN18
UPI2_CPU_FPGA_DP10UPI2_CPU_FPGA_DN10
UPI2_CPU_FPGA_DP14
UPI2_CPU_FPGA_DN12UPI2_CPU_FPGA_DP12
UPI2_CPU_FPGA_DP8UPI2_CPU_FPGA_DN8
UPI2_CPU_FPGA_DN6
UPI2_CPU_FPGA_DP4UPI2_CPU_FPGA_DN4
UPI2_CPU_FPGA_DP6
UPI2_LSIO_RX2_CON
UPI2_CPU_FPGA_DN0UPI2_CPU_FPGA_DP0
UPI2_CPU_FPGA_DN2UPI2_CPU_FPGA_DP2
UPI2_LSIO_RX1_CON
UPI2_LSIO_TX1
UPI2_LSIO_RX2_CON
UPI2_LSIO_RX5_CON
UPI2_LSIO_RX6_CON
UPI2_LSIO_RX1_CON
UPI2_SDA_3V3
UPI2_LSIO_RX6
UPI2_LSIO_RX5
UPI2_LSIO_RX1
UPI2_LSIO_RX2
UPI2_LSIO_RX4
UPI2_LSIO_RX3
UPI2_PRNSTn_3V3UPI2_LSIO_TX1_CON
UPI2_PERSTnUPI2_LSIO_TX2_CON
UPI2_LSIO_TX2
UPI2_LSIO_TX3UPI2_LSIO_TX3_CONUPI2_LSIO_TX4_CON UPI2_LSIO_TX4
UPI2_LSIO_TX5
UPI2_LSIO_TX5_CON UPI2_LSIO_TX6_CON
UPI2_LSIO_TX6
UPI2_SCL_3V3
UPI2_LSIO_RX3_CON
UPI2_NID0_3V3
UPI2_NID1_3V3
UPI2_LSIO_RX4_CON
CLK_100M_UPI2_REFCLK_EP_PCLK_100M_UPI2_REFCLK_EP_N
UPI2_LSIO_RX5_PCIE
UPI2_LSIO_RX1_PCIE
UPI2_LSIO_RX2_PCIE
UPI2_LSIO_RX6_PCIE
CLK_100M_UPI2_REFCLK_RP_NCLK_100M_UPI2_REFCLK_RP_P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Place a 1uF and 0.1uF per VDD1 pinPlace a 1uF and 0.1uF per VDD2 pin
I2C 8-bit Addr = 0x1E
GREEN LED for 25GON = LINKBLINK = ACTIVITY
YELLOW LED for 10GON = LINKBLINK = ACTIVITY
GREEN LED for 25GON = LINKBLINK = ACTIVITY
YELLOW LED for 10GON = LINKBLINK = ACTIVITY
Ios Limit = 1.489A / 1.742A / 1.965A
zQSFP Controller
Addr = 0x02,0x1E
3.3V_ZQSFP1
3.3V_ZQSFP2
1.8V3.3V_REG
3.3V_ZQSFP1
3.3V_ZQSFP2
3.3V_REG1.8V
1.8V
ZQSFP1_3V3_SDA 29
ZQSFP1_3V3_SCL 29
ZQSFP1_3V3_INT_L 29
ZQSFP1_3V3_RESET_L 29
ZQSFP1_3V3_MODPRS_L 29
ZQSFP1_3V3_LPMODE 29
ZQSFP2_3V3_RESET_L 30ZQSFP2_3V3_LPMODE 30
ZQSFP2_3V3_INT_L 30ZQSFP2_3V3_MODPRS_L 30
ZQSFP2_3V3_SDA 30
ZQSFP2_3V3_SCL 30
ZQSFP1_PWR_EN29ZQSFP1_FAULT_N29
I2C2_1V8_SDA7I2C2_1V8_SCL7
ZQSFP_1V8_PORT_INT_N7
ZQSFP_1V8_PORT_EN7
ZQSFP2_PWR_EN30ZQSFP2_FAULT_N30
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
28 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
28 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
28 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R3314.70K
1%0402
C8560.1uF040225VX7R
R33710.0K,DNI04021%
R328 0
C8271uF040225VX5R
R3824004021%
R3324004021%
C8280.1uF040225VX7R
R35110.0K04021%
D18GREEN_LEDLED_0603
C5190.1uF040225VX7R D20 YELLOW_LED
LED_0603
R3484.70K
1%0402
C5201uF040225VX5R
U50
FPC202RHUR
P1_S0_IN_B1
P1_S0_OUT_B2
P1_S0_OUT_C6
P1_S0_OUT_D7
GPIO[2]8
VDD1_19
VDD1_243
VDD1_354
P1_S1_OUT_A11
P0_S1_OUT_A44
P0_S1_OUT_B45
P1_S1_OUT_B13CAPL
32
CTRL123
CTRL224
CTRL328
CTRL421
EN22
GPIO[0]42
GPIO[1]53
GPIO[3]19
GND27
HOST_INT_N25
P0_S0_IN_A41
P1_S0_IN_A55
P0_S0_IN_B39
P0_S0_IN_C37
P1_S0_IN_C3
P0_S1_IN_A50
P1_S1_IN_A10
P0_S1_IN_B47
P1_S1_IN_B12
P0_S1_IN_C46
P1_S1_IN_C14
P0_MOD_SCL36
P1_MOD_SCL4
P0_MOD_SDA35
P1_MOD_SDA5
P0_AUX_SCL49P0_AUX_SDA48
P1_AUX_SCL15P1_AUX_SDA16
P0_S0_OUT_B38
P0_S0_OUT_C34
P0_S0_OUT_A40
P1_S0_OUT_A56
P0_S0_OUT_D33
P0_S1_OUT_D52
P1_S1_OUT_C17
P0_S1_OUT_C51
P1_S1_OUT_D18
PROTOCOL_SEL31
SPI_LED_SY_NC30
TEST_N29
VDD2_120
VDD2_226
DAP (GND)57
R31910.0K04021%
R15324004021%
C8291uF040225VX5R
R3494.70K
1%0402
R11824004021%
C8480.1uF040225VX7R
C5182.2uF060310VX5R
R31823.2K04021%
D21 YELLOW_LEDLED_0603
R3164.70K
1%0402
C8231uF040225VX5R
C8491uF040225VX5R
D22GREEN_LEDLED_0603
C8260.1uF040225VX7R
R35023.2K04021%
R33610.0K04021%
R3174.70K
1%0402
R327 0 ZQSFP1_25G_LINK_ACT_LEDnZQSFP1_10G_LINK_ACT_LEDn
ZQSFP2_25G_LINK_ACT_LEDnZQSFP2_10G_LINK_ACT_LEDn
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Quad Small Form-factor Pluggable (QSFP) Interface
NOTE 1: Bypass Capacitors should be placed as close to the associated 20-pinconnector as possible.
NOTE 2: Assuming that the SFP RD 100-ohm termination on the Host Board FPGAdevice will be implemented via the on-chip termination circuit.
NOTE 3: DC blocking capacitors are in the module for RX and TX.
NOTE 4: 1uH inductors should have a DC Resistance of less than 0.1-ohm.
QSFP1
I2C Address = A0h
QSFP1 INTERFACE
Vil=0.66VVih=1.1V
Rds(on) max = 35mOhmdropout max = 1.965A x .035 = .069V
Route traceshort aspossible
60uA
ABSMAX = 7V
Ios Limit = 1.489A / 1.742A / 1.965A
ABSMAX = 7V
Support both CAUI2 and 4x25G ethernet
GND_QSFP_CAGE
QSFP1_VCC
QSFP1_VCCRQSFP1_VCCT
3.3V_REG
3.3V_ZQSFP1
QSFP1_VCCT
QSFP1_VCCR
QSFP1_VCC
3.3V_ZQSFP1
QSFP1_VCC
GND_QSFP_CAGE
QSFP1_RX_P[3:0]14QSFP1_RX_N[3:0]14
QSFP1_TX_P[3:0]14QSFP1_TX_N[3:0]14
ZQSFP1_PWR_EN28
ZQSFP1_FAULT_N28
ZQSFP1_3V3_RESET_L 28
ZQSFP1_3V3_LPMODE 28ZQSFP1_3V3_MODPRS_L 28
ZQSFP1_3V3_INT_L 28
ZQSFP1_3V3_SCL 28ZQSFP1_3V3_SDA 28
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
29 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
29 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
29 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C3420.1uF040225VX7R
C34310uF06036.3VX6S
R375
0
C3170.1uF040225VX7R
C30710uF06036.3VX6S
C31922uF06036.3VX6S
R358 0
J15
Molex_zQSFP_Connector
GND1
TX2n2 TX2p3
GND4
TX4n5 TX4p6
GND7
ModselL8
ResetL9
VCCRX10
SCL11
SDA12
GND13
RX3p14
RX3n15
GND16
RX1p17
RX1n18
GND19 GND20
RX2n21RX2p22
GND23
RX4n24RX4p25
GND26
ModPrsL27
Intl28
VCCTX29 VCC130
LPMode31
GND32
TX3p33
TX3n34
GND35
TX1p36
TX1n37
GND38
MTH139
MTH240
C8601uF040225VX5R
C37022uF06036.3VX6S
R359 0
C36922uF06036.3VX6S
C1904.7nF
0402
C34422uF06036.3VX6SR14610.0K
R5564DNI
04
02
R32354.9K04021%
FB15
80ohm @ 100Mhz5A, 10mOhm
C34522uF06036.3VX6S
C30622uF06036.3VX6S
HW1
2170806-1
CAGE_GND0MH1
CAGE_GND1MH2
CAGE_GND2MH3
CAGE_GND3MH4
CAGE_GND4MH5
CAGE_GND5MH6
CAGE_GND6MH7
CAGE_GND7MH8
CAGE_GND8MH9
CAGE_GND9MH10CAGE_GND10MH11CAGE_GND11MH12CAGE_GND12MH13CAGE_GND13MH14CAGE_GND14MH15CAGE_GND15MH16CAGE_GND16MH17
FB16
80ohm @ 100Mhz5A, 10mOhm
R32463.4K04021%
C8570.1uF040225VX7R
C3460.1uF040225VX7R
C30522uF06036.3VX6S
FB14
80ohm @ 100Mhz5A, 10mOhm
C52122uF06036.3VX6S
C3180.1uF040225VX7R
C36810uF06036.3VX6S
U51
TPS2557DRBR
IN23 IN12
EN4
FAULT8
GND1
MPAD9
ILIM5
OUT16
OUT27
QSFP1_TX_N3
QSFP1_TX_N0QSFP1_TX_P0
QSFP1_TX_P3QSFP1_RX_N3QSFP1_RX_P3
QSFP1_RX_P0QSFP1_RX_N0
ZQSFP1_MODSELL
QSFP1_TX_P1QSFP1_TX_N1
QSFP1_TX_P2QSFP1_TX_N2
QSFP1_RX_P2QSFP1_RX_N2
QSFP1_RX_P1QSFP1_RX_N1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
I2C Address = A0h
QSFP2
Vil=0.66VVih=1.1V
Rds(on) max = 35mOhmdropout max = 1.965A x .035 = .069V
Route traceshort aspossible
ABSMAX = 7V
ABSMAX = 7V
Ios Limit = 1.489A / 1.742A / 1.965A
Support both CAUI2 and 4x25G ethernet
QSFP2_VCC
QSFP2_VCCRQSFP2_VCCT
3.3V_REG3.3V_ZQSFP2
QSFP2_VCCT
QSFP2_VCCR
QSFP2_VCC
3.3V_ZQSFP2
QSFP2_VCC
QSFP2_RX_P[3:0]14QSFP2_RX_N[3:0]14
QSFP2_TX_P[3:0]14QSFP2_TX_N[3:0]14
ZQSFP2_3V3_RESET_L 28
ZQSFP2_3V3_LPMODE 28ZQSFP2_3V3_MODPRS_L 28
ZQSFP2_3V3_INT_L 28
ZQSFP2_3V3_SCL 28ZQSFP2_3V3_SDA 28
ZQSFP2_PWR_EN28
ZQSFP2_FAULT_N28
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
30 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
30 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
30 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C3470.1uF040225VX7R
C30822uF06036.3VX6S
R376
0
FB17
80ohm @ 100Mhz5A, 10mOhm
C3480.1uF040225VX7R
C37210uF06036.3VX6S
R32554.9K04021%
C3230.1uF040225VX7R
C31310uF06036.3VX6S
C3240.1uF040225VX7R
C35010uF06036.3VX6S
R32663.4K04021%
C8610.1uF040225VX7R
C32522uF06036.3VX6S
C37322uF06036.3VX6S
U52
TPS2557DRBR
IN23 IN12
EN4
FAULT8
GND1
MPAD9
ILIM5
OUT16
OUT27
C52222uF06036.3VX6S
C37122uF06036.3VX6S
R360 0
C35122uF06036.3VX6S
FB18
80ohm @ 100Mhz5A, 10mOhm
R361 0
C34922uF06036.3VX6S
FB19
80ohm @ 100Mhz5A, 10mOhm
J18
Molex_zQSFP_Connector
GND1
TX2n2 TX2p3
GND4
TX4n5 TX4p6
GND7
ModselL8
ResetL9
VCCRX10
SCL11
SDA12
GND13
RX3p14
RX3n15
GND16
RX1p17
RX1n18
GND19 GND20
RX2n21RX2p22
GND23
RX4n24RX4p25
GND26
ModPrsL27
Intl28
VCCTX29 VCC130
LPMode31
GND32
TX3p33
TX3n34
GND35
TX1p36
TX1n37
GND38
MTH139
MTH240
C31422uF06036.3VX6S
R5566DNI
04
02
C8621uF040225VX5R
QSFP2_TX_P0QSFP2_TX_N0
QSFP2_TX_N3QSFP2_TX_P3
QSFP2_RX_P0
QSFP2_RX_P3QSFP2_RX_N3
QSFP2_RX_N0
ZQSFP2_MODSELL
QSFP2_TX_P2QSFP2_TX_N2
QSFP2_TX_P1QSFP2_TX_N1
QSFP2_RX_P2QSFP2_RX_N2
QSFP2_RX_P1QSFP2_RX_N1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
User PB, SW, I/Os
CONF_DONE
PWR Good
VGS(th) = 0.6V / 1V /1.5V
Status LEDs
1.8V
3.3V_REG
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
CPU_RESETn 9,23
MAX_RESETn 23
USER_LED_G[3:0]8
MAX_CONF_DONE 23
USER_PB0 9
PWRGD_OUT23
FPGA_CONF_DONE_LED23
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
31 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
31 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
31 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
D13GREEN_LED
R624004021%
R59
100
D57GREEN_LED
LED_0603
R659424004021%
R15910.0K
S4
PB Switch1 2
1
2
3Q7SI2302CDS-T1-GE3
SOT23
R16010.0K
S3
PB Switch1 2
D9
GREEN_LED
D56YELLOW_LED
LED_0603
R6596 2400402 1%
Q43
DMN26D0UT-7
R16110.0K
D10
GREEN_LED
R15110.0K
Q44
DMN26D0UT-7
Q45
DMN26D0UT-7
1
2
3Q8SI2302CDS-T1-GE3
SOT23
D15
GREEN_LED
R14710.0K
R262130
Q46
DMN26D0UT-7
R42
100
R14810.0K
R43
100
R192 2400402 1%
D14
GREEN_LED
S2
PB Switch1 2
R62
100
R15810.0K
MAX_RESETn
USER_PB0
CPU_RESETn
MAX_CONF_DONELED_MAX_CONF_DONE_ANODE
USER_LED_G0
USER_LED_G1
USER_LED_G2
USER_LED_G3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Route as matched pair on Top layer
PLACE CLOSE CY7C68013
USB Blaster II
VGS(th) = 0.6V / 1V /1.5V
When EXT UBII is plugged into J8, USB PHYis held in RESET to avoid contention onPD[3:0] signal with Header JTAG signals.
3.3V_REG_INST
3.3V_REG_INST3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
FX2_PA[7:0] 23
USB_T_CLK 23FX2_FLAGA 23
FX2_SCL 23FX2_SDA 23
FX2_SLRDn 23FX2_SLWRn 23FX2_RESETn 23
FX2_PB[7:0] 23
FX2_PD[7:0] 23
FX2_FLAGB 23FX2_FLAGC 23
USB_PHY_RESETn 23
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
32 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
32 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
32 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C232
12pF0402
R4831K0402
1%
C240
0.1uF0402
R224 2.00K
R484 05%0402
C237
0.1uF0402
U26
CY7C68013A_QFN
RDY01
RDY12
XTALIN5
AVCC3
DMINUS9
AGND6
VCC11
GND12
PD752
CLKOUT54
XTALOUT4
AVCC7
DPLUS8
AGND10
IFCLK13
RESERVED14
PD550PD449
PD651
SCL15
SDA16
PB018
GND26
GND28
GND41
PB119
PB321PB220
VCC17
VCC27
PB624PB523PB422
PD348PD247
PA740
PA437
PA134
PB725
PD146
WAKEUP44
PA639
GND53
VCC43
PA336
CTL130CTL029
PD045
RESET42
PA538
GND56
VCC55
PA235
PA033
CTL231
VCC32
EXPOSED_PAD57
C241
0.1uF0402
Y4
24.00MHz
1 32
4
R220100K
C236
0.1uF0402
U25
TPD2EUSB30
D-2D+1
GND3
R219
10.0K
C231
12pF0402
C239
0.1uF0402
R221
20.0K
C229
0.1uF0402
VBUS
D-
D+
ID
CN1MICRO_USB_CONN
12345
67891
01
1
R223 2.00KR222 0
U24
MAX811
GND1
RESET2
VCC4
MR3
C235
0.1uF0402
1
2
3 Q28SI2302CDS-T1-GE3
SOT23
R66574.70K
C230 4.7nF0402
R4851001% 0402
C228 0.1uF0402
C238
0.1uF0402
C234
0.1uF0402
R597 0, DNI
FX2_D_NFX2_D_P
VBUS_5V
24M_XTALIN24M_XTALOUT
FX2_WAKEUPVBUS_5V
USB_T_CLK
FX2_PA0FX2_PA1FX2_PA2FX2_PA3FX2_PA4FX2_PA5FX2_PA6FX2_PA7
FX2_PB0FX2_PB1FX2_PB2FX2_PB3FX2_PB4FX2_PB5FX2_PB6FX2_PB7
FX2_PD0FX2_PD1FX2_PD2FX2_PD3FX2_PD4FX2_PD5FX2_PD6FX2_PD7
FX2_SLWRnFX2_SLRDn
FX2_FLAGCFX2_FLAGBFX2_FLAGA
FX2_WAKEUP
FX2_SDAFX2_SCL
FX2_RESETn
FX2_RESETn
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Temp Sense, fan connector
Core A
I2C ADDR = 9A
Board Temp Sensor
I2C ADDR = 7b
4-Channel Power Monitor
12V_AUX2_IN
3.3V_REG_INST
3.3V_REG_INST3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
FAN_PWM 23FAN_TACH 23
S10_TEMPDIODE0_P20 OVERTEMPn 23S10_TEMPDIODE0_N20
I2C3_SCL7,23I2C3_SDA7,23
TSENSE_ALERTn 23,68S10_TEMPDIODE1_P20S10_TEMPDIODE1_N20S10_TEMPDIODE2_P20S10_TEMPDIODE2_N20S10_TEMPDIODE4_P20S10_TEMPDIODE4_N20S10_TEMPDIODE5_P20S10_TEMPDIODE5_N20
DIODEH17DIODEL17
S10_TEMPDIODE6_P20S10_TEMPDIODE6_N20
VCCRT_GXP_SENSE_P62VCCRT_GXP_SENSE_N62
VCCRT_GXE_SENSE_P62VCCRT_GXE_SENSE_N62
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
33 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
33 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
33 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C711 100pf
C3219 100pf
R1818 DNI
J24
FAN_Conn
GND112V2DNR_TACH3FAN_PWM4
R321 69.8
C710 100pf
C32220.1uF R338
2.2K
R1817 0
C3217 100pf
R3352.2K,DNI
C3218 100pf
R1816 0
D40 RED_LED
C709 100pf
U32
MAX6581
DXP21
DXP33
DXP45
DXN47
DXN59
DXN712
DXN22
DXN34
NC16
DXP58
DXN610 DXP611
DXP713 STBY
14
I.C.15VCC17
OVERT16
ALERT18
SMBDATA19 SMBCLK20
GND21
NC222
DXP123
DXN124
EP25
R1819 0
C395 100pf
U233
PAC1932_UQFN
SLOW/ALERTn1V
DD
2
GN
D3
SM_CLK4
SM_DATA5
ADDRSEL6
SENSE3-7 SENSE3+8
SENSE1+11
SENSE1-12
SENSE2+13
SENSE2-14
SENSE4+10
SENSE4-9
VD
DIO
15
PWRDNn16
GN
D_
EP
17
R729 10.0K
R6
67
21
0.0
KR
66
73
10
.0K
C3960.1uF
C32210.1uF
OVERTEMPn RESn_LED_FAN
OVERTEMPnTSENSE_ALERTn
I2C3_SCLI2C3_SDA
I2C3_SCLI2C3_SDA
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Byte 0
Byte 1 Byte 3
Byte 2
When using singledie DDR4, set UZQresistor to 0-ohm
When using singledie DDR4, set UZQresistor to 0-ohm
Place near pin E9of each device
Place near pin E9of each device
DDR4 CH0 Part1
0V6_DDR4_VREF_CH000V6_DDR4_VREF_CH00
2V5_DDR4_CH00 2V5_DDR4_CH00
S10_1V2OUT_CH00S10_1V2OUT_CH00
DDR4_CH0_BA011,34,35,36,37
DDR4_CH0_A1611,34,35,36,37DDR4_CH0_A1511,34,35,36,37DDR4_CH0_A1411,34,35,36,37
DDR4_CH0_A1311,34,35,36,37DDR4_CH0_A1211,34,35,36,37DDR4_CH0_A1111,34,35,36,37DDR4_CH0_A1011,34,35,36,37
DDR4_CH0_A911,34,35,36,37DDR4_CH0_A811,34,35,36,37DDR4_CH0_A711,34,35,36,37DDR4_CH0_A611,34,35,36,37DDR4_CH0_A511,34,35,36,37DDR4_CH0_A411,34,35,36,37DDR4_CH0_A311,34,35,36,37DDR4_CH0_A211,34,35,36,37DDR4_CH0_A111,34,35,36,37DDR4_CH0_A011,34,35,36,37
DDR4_CH0_BA111,34,35,36,37
DDR4_CH0_BG111,34,35,36,37
DDR4_CH0_DQ0 11DDR4_CH0_DQ1 11DDR4_CH0_DQ2 11DDR4_CH0_DQ3 11DDR4_CH0_DQ4 11DDR4_CH0_DQ5 11DDR4_CH0_DQ6 11DDR4_CH0_DQ7 11DDR4_CH0_DQ8 11DDR4_CH0_DQ9 11DDR4_CH0_DQ10 11DDR4_CH0_DQ11 11DDR4_CH0_DQ12 11DDR4_CH0_DQ13 11DDR4_CH0_DQ14 11DDR4_CH0_DQ15 11
DDR4_CH0_A011,34,35,36,37 DDR4_CH0_DQ16 11DDR4_CH0_A111,34,35,36,37 DDR4_CH0_DQ17 11DDR4_CH0_A211,34,35,36,37 DDR4_CH0_DQ18 11DDR4_CH0_A311,34,35,36,37 DDR4_CH0_DQ19 11DDR4_CH0_A411,34,35,36,37 DDR4_CH0_DQ20 11DDR4_CH0_A511,34,35,36,37 DDR4_CH0_DQ21 11DDR4_CH0_A611,34,35,36,37 DDR4_CH0_DQ22 11DDR4_CH0_A711,34,35,36,37 DDR4_CH0_DQ23 11DDR4_CH0_A811,34,35,36,37 DDR4_CH0_DQ24 11DDR4_CH0_A911,34,35,36,37 DDR4_CH0_DQ25 11
DDR4_CH0_A1011,34,35,36,37 DDR4_CH0_DQ26 11DDR4_CH0_A1111,34,35,36,37 DDR4_CH0_DQ27 11DDR4_CH0_A1211,34,35,36,37 DDR4_CH0_DQ28 11DDR4_CH0_A1311,34,35,36,37 DDR4_CH0_DQ29 11
DDR4_CH0_DQ30 11DDR4_CH0_A1411,34,35,36,37 DDR4_CH0_DQ31 11DDR4_CH0_A1511,34,35,36,37DDR4_CH0_A1611,34,35,36,37
DDR4_CH0_BA011,34,35,36,37DDR4_CH0_BA111,34,35,36,37
DDR4_CH0_BG111,34,35,36,37
DDR4_CH0_PAR11,34,35,36,37
DDR4_CH0_ALERTn 11,34,35,36
DDR4_CH0_CKE11,34,35,36,37
DDR4_CH0_CKp11,34,35,36,37DDR4_CH0_CKn11,34,35,36,37
DDR4_CH0_CSn11,34,35,36,37
DDR4_CH0_ODT11,34,35,36,37
DDR4_CH0_ACTn11,34,35,36,37
DDR4_CH0_RESETn11,34,35,36,37
DDR4_CH0_CKp11,34,35,36,37DDR4_CH0_CKn11,34,35,36,37
DDR4_CH0_CKE11,34,35,36,37
DDR4_CH0_CSn11,34,35,36,37
DDR4_CH0_ODT11,34,35,36,37DDR4_CH0_PAR11,34,35,36,37
DDR4_CH0_RESETn11,34,35,36,37
DDR4_CH0_ACTn11,34,35,36,37DDR4_CH0_DQS0n 11DDR4_CH0_DQS0p 11
DDR4_CH0_DQS1n 11DDR4_CH0_DQS1p 11
DDR4_CH0_DQS2p 11DDR4_CH0_DQS2n 11
DDR4_CH0_DQS3p 11DDR4_CH0_DQS3n 11
DDR4_CH0_ALERTn 11,34,35,36
DDR4_CH0_TEN34,35,36 DDR4_CH0_TEN34,35,36
DDR4_CH0_DM011DDR4_CH0_DM111
DDR4_CH0_DM211DDR4_CH0_DM311
DDR4_CH0_BG011,34,35,36,37 DDR4_CH0_BG011,34,35,36,37
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
34 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
34 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
34 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R57930, DNI
04025%
R579624004021%
R5795240
04021%
R579824004021%
DDR4 x 16
U142
MT40A1G16KNR-075:E
A0P3
A1P7
A2R3
A3N7
A4N3
A5P8
A6P2
A7R8
A8R2
A9R7
A10/APM3
A11T2
A12/BCnM7
A13T8
A14/WEnL2
A15/CASnM8
A16/RASnL8
ACTnL3
BA0N2
BA1N8
BG1M9
CK_TK7
CK_CK8
CKEK2
CSnL7
NF/LDMn/LDBInE7
NF/UDMn/UDBInE2
ODTK3
PART3
RESETnP1
TENN9
DQ0G2
DQ1F7
DQ2H3
DQ3H7
DQ4H2
DQ5H8
DQ6J3
DQ7J7
DQ8A3
DQ9B8
DQ10C3
DQ11C7
DQ12C2
DQ13C8
DQ14D3
DQ15D7
DQSL_TG3
DQSL_CF3
DQSU_TB7
DQSU_CA7
ALERTnP9
VDD1D1
VDD2J1
VDD3L1
VDD4R1
VDD5B3
VDD6G7
VDD7B9
VDD8J9
VDD9L9
VDD10T9
VDDQ1A1
VDDQ2C1
VDDQ3G1
VDDQ4F2
VDDQ5J2
VDDQ6F8
VDDQ7J8
VDDQ8A9
VDDQ9D9
VDDQ10G9
VSS1E1
VSS2K1
VSS3N1
VSS4T1
VSS5B2
VSS6G8
UZQE9
VSS8K9
VSSQ1F1
VSSQ2H1
VSSQ3A2
VSSQ4D2
VSSQ5E3
VSSQ6A8
VSSQ7D8
VSSQ8E8
VSSQ9C9
VSSQ10H9
VSS7T7
VREFCAM1
VPP1B1
VPP2R9
LZQF9
BG0M2
R5797240
04021%
DDR4 x 16
U143
MT40A1G16KNR-075:E
A0P3
A1P7
A2R3
A3N7
A4N3
A5P8
A6P2
A7R8
A8R2
A9R7
A10/APM3
A11T2
A12/BCnM7
A13T8
A14/WEnL2
A15/CASnM8
A16/RASnL8
ACTnL3
BA0N2
BA1N8
BG1M9
CK_TK7
CK_CK8
CKEK2
CSnL7
NF/LDMn/LDBInE7
NF/UDMn/UDBInE2
ODTK3
PART3
RESETnP1
TENN9
DQ0G2
DQ1F7
DQ2H3
DQ3H7
DQ4H2
DQ5H8
DQ6J3
DQ7J7
DQ8A3
DQ9B8
DQ10C3
DQ11C7
DQ12C2
DQ13C8
DQ14D3
DQ15D7
DQSL_TG3
DQSL_CF3
DQSU_TB7
DQSU_CA7
ALERTnP9
VDD1D1
VDD2J1
VDD3L1
VDD4R1
VDD5B3
VDD6G7
VDD7B9
VDD8J9
VDD9L9
VDD10T9
VDDQ1A1
VDDQ2C1
VDDQ3G1
VDDQ4F2
VDDQ5J2
VDDQ6F8
VDDQ7J8
VDDQ8A9
VDDQ9D9
VDDQ10G9
VSS1E1
VSS2K1
VSS3N1
VSS4T1
VSS5B2
VSS6G8
UZQE9
VSS8K9
VSSQ1F1
VSSQ2H1
VSSQ3A2
VSSQ4D2
VSSQ5E3
VSSQ6A8
VSSQ7D8
VSSQ8E8
VSSQ9C9
VSSQ10H9
VSS7T7
VREFCAM1
VPP1B1
VPP2R9
LZQF9
BG0M2
R57940, DNI
04025%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Byte 5
Byte 4
Byte 7
Byte 6
When using singledie DDR4, set UZQresistor to 0-ohm
When using singledie DDR4, set UZQresistor to 0-ohm
Place near pin E9of each device
Place near pin E9of each device
DDR4 CH0 Part2
0V6_DDR4_VREF_CH000V6_DDR4_VREF_CH00
2V5_DDR4_CH00 2V5_DDR4_CH00
S10_1V2OUT_CH00S10_1V2OUT_CH00
DDR4_CH0_BA011,34,35,36,37
DDR4_CH0_A1611,34,35,36,37DDR4_CH0_A1511,34,35,36,37DDR4_CH0_A1411,34,35,36,37
DDR4_CH0_A1311,34,35,36,37DDR4_CH0_A1211,34,35,36,37DDR4_CH0_A1111,34,35,36,37DDR4_CH0_A1011,34,35,36,37
DDR4_CH0_A911,34,35,36,37DDR4_CH0_A811,34,35,36,37DDR4_CH0_A711,34,35,36,37DDR4_CH0_A611,34,35,36,37DDR4_CH0_A511,34,35,36,37DDR4_CH0_A411,34,35,36,37DDR4_CH0_A311,34,35,36,37DDR4_CH0_A211,34,35,36,37DDR4_CH0_A111,34,35,36,37DDR4_CH0_A011,34,35,36,37
DDR4_CH0_BA111,34,35,36,37
DDR4_CH0_BG111,34,35,36,37
DDR4_CH0_DQ32 11DDR4_CH0_DQ33 11DDR4_CH0_DQ34 11DDR4_CH0_DQ35 11DDR4_CH0_DQ36 11DDR4_CH0_DQ37 11DDR4_CH0_DQ38 11DDR4_CH0_DQ39 11DDR4_CH0_DQ40 11DDR4_CH0_DQ41 11DDR4_CH0_DQ42 11DDR4_CH0_DQ43 11DDR4_CH0_DQ44 11DDR4_CH0_DQ45 11DDR4_CH0_DQ46 11DDR4_CH0_DQ47 11
DDR4_CH0_A011,34,35,36,37 DDR4_CH0_DQ48 11DDR4_CH0_A111,34,35,36,37 DDR4_CH0_DQ49 11DDR4_CH0_A211,34,35,36,37 DDR4_CH0_DQ50 11DDR4_CH0_A311,34,35,36,37 DDR4_CH0_DQ51 11DDR4_CH0_A411,34,35,36,37 DDR4_CH0_DQ52 11DDR4_CH0_A511,34,35,36,37 DDR4_CH0_DQ53 11DDR4_CH0_A611,34,35,36,37 DDR4_CH0_DQ54 11DDR4_CH0_A711,34,35,36,37 DDR4_CH0_DQ55 11DDR4_CH0_A811,34,35,36,37 DDR4_CH0_DQ56 11DDR4_CH0_A911,34,35,36,37 DDR4_CH0_DQ57 11
DDR4_CH0_A1011,34,35,36,37 DDR4_CH0_DQ58 11DDR4_CH0_A1111,34,35,36,37 DDR4_CH0_DQ59 11DDR4_CH0_A1211,34,35,36,37 DDR4_CH0_DQ60 11DDR4_CH0_A1311,34,35,36,37 DDR4_CH0_DQ61 11
DDR4_CH0_DQ62 11DDR4_CH0_A1411,34,35,36,37 DDR4_CH0_DQ63 11DDR4_CH0_A1511,34,35,36,37DDR4_CH0_A1611,34,35,36,37
DDR4_CH0_BA011,34,35,36,37DDR4_CH0_BA111,34,35,36,37
DDR4_CH0_BG111,34,35,36,37
DDR4_CH0_PAR11,34,35,36,37
DDR4_CH0_ALERTn 11,34,35,36
DDR4_CH0_CKE11,34,35,36,37
DDR4_CH0_CKp11,34,35,36,37DDR4_CH0_CKn11,34,35,36,37
DDR4_CH0_CSn11,34,35,36,37
DDR4_CH0_ODT11,34,35,36,37
DDR4_CH0_ACTn11,34,35,36,37
DDR4_CH0_RESETn11,34,35,36,37
DDR4_CH0_CKp11,34,35,36,37DDR4_CH0_CKn11,34,35,36,37
DDR4_CH0_CKE11,34,35,36,37
DDR4_CH0_CSn11,34,35,36,37
DDR4_CH0_ODT11,34,35,36,37DDR4_CH0_PAR11,34,35,36,37
DDR4_CH0_RESETn11,34,35,36,37
DDR4_CH0_ACTn11,34,35,36,37DDR4_CH0_DQS4n 11DDR4_CH0_DQS4p 11
DDR4_CH0_DQS5n 11DDR4_CH0_DQS5p 11
DDR4_CH0_DQS6p 11DDR4_CH0_DQS6n 11
DDR4_CH0_DQS7p 11DDR4_CH0_DQS7n 11
DDR4_CH0_ALERTn 11,34,35,36
DDR4_CH0_TEN34,35,36 DDR4_CH0_TEN34,35,36
DDR4_CH0_DM411DDR4_CH0_DM511
DDR4_CH0_DM611DDR4_CH0_DM711
DDR4_CH0_BG011,34,35,36,37 DDR4_CH0_BG011,34,35,36,37
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
35 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
35 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
35 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R5803240
04021%
R58000, DNI
04025%
DDR4 x 16
U145
MT40A1G16KNR-075:E
A0P3
A1P7
A2R3
A3N7
A4N3
A5P8
A6P2
A7R8
A8R2
A9R7
A10/APM3
A11T2
A12/BCnM7
A13T8
A14/WEnL2
A15/CASnM8
A16/RASnL8
ACTnL3
BA0N2
BA1N8
BG1M9
CK_TK7
CK_CK8
CKEK2
CSnL7
NF/LDMn/LDBInE7
NF/UDMn/UDBInE2
ODTK3
PART3
RESETnP1
TENN9
DQ0G2
DQ1F7
DQ2H3
DQ3H7
DQ4H2
DQ5H8
DQ6J3
DQ7J7
DQ8A3
DQ9B8
DQ10C3
DQ11C7
DQ12C2
DQ13C8
DQ14D3
DQ15D7
DQSL_TG3
DQSL_CF3
DQSU_TB7
DQSU_CA7
ALERTnP9
VDD1D1
VDD2J1
VDD3L1
VDD4R1
VDD5B3
VDD6G7
VDD7B9
VDD8J9
VDD9L9
VDD10T9
VDDQ1A1
VDDQ2C1
VDDQ3G1
VDDQ4F2
VDDQ5J2
VDDQ6F8
VDDQ7J8
VDDQ8A9
VDDQ9D9
VDDQ10G9
VSS1E1
VSS2K1
VSS3N1
VSS4T1
VSS5B2
VSS6G8
UZQE9
VSS8K9
VSSQ1F1
VSSQ2H1
VSSQ3A2
VSSQ4D2
VSSQ5E3
VSSQ6A8
VSSQ7D8
VSSQ8E8
VSSQ9C9
VSSQ10H9
VSS7T7
VREFCAM1
VPP1B1
VPP2R9
LZQF9
BG0M2
R5801240
04021%
DDR4 x 16
U144
MT40A1G16KNR-075:E
A0P3
A1P7
A2R3
A3N7
A4N3
A5P8
A6P2
A7R8
A8R2
A9R7
A10/APM3
A11T2
A12/BCnM7
A13T8
A14/WEnL2
A15/CASnM8
A16/RASnL8
ACTnL3
BA0N2
BA1N8
BG1M9
CK_TK7
CK_CK8
CKEK2
CSnL7
NF/LDMn/LDBInE7
NF/UDMn/UDBInE2
ODTK3
PART3
RESETnP1
TENN9
DQ0G2
DQ1F7
DQ2H3
DQ3H7
DQ4H2
DQ5H8
DQ6J3
DQ7J7
DQ8A3
DQ9B8
DQ10C3
DQ11C7
DQ12C2
DQ13C8
DQ14D3
DQ15D7
DQSL_TG3
DQSL_CF3
DQSU_TB7
DQSU_CA7
ALERTnP9
VDD1D1
VDD2J1
VDD3L1
VDD4R1
VDD5B3
VDD6G7
VDD7B9
VDD8J9
VDD9L9
VDD10T9
VDDQ1A1
VDDQ2C1
VDDQ3G1
VDDQ4F2
VDDQ5J2
VDDQ6F8
VDDQ7J8
VDDQ8A9
VDDQ9D9
VDDQ10G9
VSS1E1
VSS2K1
VSS3N1
VSS4T1
VSS5B2
VSS6G8
UZQE9
VSS8K9
VSSQ1F1
VSSQ2H1
VSSQ3A2
VSSQ4D2
VSSQ5E3
VSSQ6A8
VSSQ7D8
VSSQ8E8
VSSQ9C9
VSSQ10H9
VSS7T7
VREFCAM1
VPP1B1
VPP2R9
LZQF9
BG0M2
R57990, DNI
04025%
R580224004021%
R580424004021%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Byte 8
When using singledie DDR4, set UZQresistor to 0-ohm
TEN is active high (TEN should be low for normal operation)When FPGA drive TEN to 1.8V, DDR4 input is 1.12VHigh = 0.8*VDD = 960mVLow = 0.2*VDD = 240mV
Place near pin E9of each device
DDR4 CH0 Part3
0V6_DDR4_VREF_CH00
2V5_DDR4_CH00
S10_1V2OUT_CH00
S10_1V2OUT_CH00
S10_1V2OUT_CH00
S10_1V2OUT_CH00
DDR4_CH0_BA011,34,35,37
DDR4_CH0_A1611,34,35,37DDR4_CH0_A1511,34,35,37DDR4_CH0_A1411,34,35,37
DDR4_CH0_A1311,34,35,37DDR4_CH0_A1211,34,35,37DDR4_CH0_A1111,34,35,37DDR4_CH0_A1011,34,35,37
DDR4_CH0_A911,34,35,37DDR4_CH0_A811,34,35,37DDR4_CH0_A711,34,35,37DDR4_CH0_A611,34,35,37DDR4_CH0_A511,34,35,37DDR4_CH0_A411,34,35,37DDR4_CH0_A311,34,35,37DDR4_CH0_A211,34,35,37DDR4_CH0_A111,34,35,37DDR4_CH0_A011,34,35,37
DDR4_CH0_BA111,34,35,37
DDR4_CH0_BG111,34,35,37
DDR4_CH0_DQ64 11DDR4_CH0_DQ65 11DDR4_CH0_DQ66 11DDR4_CH0_DQ67 11DDR4_CH0_DQ68 11DDR4_CH0_DQ69 11DDR4_CH0_DQ70 11DDR4_CH0_DQ71 11
DDR4_CH0_PAR11,34,35,37
DDR4_CH0_ALERTn 11,34,35DDR4_CH0_CKE11,34,35,37
DDR4_CH0_CKp11,34,35,37DDR4_CH0_CKn11,34,35,37
DDR4_CH0_CSn11,34,35,37
DDR4_CH0_ODT11,34,35,37
DDR4_CH0_ACTn11,34,35,37
DDR4_CH0_RESETn11,34,35,37
DDR4_CH0_DQS8n 11DDR4_CH0_DQS8p 11
DDR4_CH0_TEN34,35
DDR4_CH0_DM811
DDR4_CH0_BG011,34,35,37
DDR4_CH0_TEN_1V88
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
36 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
36 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
36 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R58194.70K
0.1%0402
R5818 2.87k0402 0.1%
R5816 221 Ohm0402 1%
R5814 221 Ohm0402 1%
R58200, DNI
04025%
R582224004021%
R5821240
04021%
DDR4 x 16
U146
MT40A1G16KNR-075:E
A0P3
A1P7
A2R3
A3N7
A4N3
A5P8
A6P2
A7R8
A8R2
A9R7
A10/APM3
A11T2
A12/BCnM7
A13T8
A14/WEnL2
A15/CASnM8
A16/RASnL8
ACTnL3
BA0N2
BA1N8
BG1M9
CK_TK7
CK_CK8
CKEK2
CSnL7
NF/LDMn/LDBInE7
NF/UDMn/UDBInE2
ODTK3
PART3
RESETnP1
TENN9
DQ0G2
DQ1F7
DQ2H3
DQ3H7
DQ4H2
DQ5H8
DQ6J3
DQ7J7
DQ8A3
DQ9B8
DQ10C3
DQ11C7
DQ12C2
DQ13C8
DQ14D3
DQ15D7
DQSL_TG3
DQSL_CF3
DQSU_TB7
DQSU_CA7
ALERTnP9
VDD1D1
VDD2J1
VDD3L1
VDD4R1
VDD5B3
VDD6G7
VDD7B9
VDD8J9
VDD9L9
VDD10T9
VDDQ1A1
VDDQ2C1
VDDQ3G1
VDDQ4F2
VDDQ5J2
VDDQ6F8
VDDQ7J8
VDDQ8A9
VDDQ9D9
VDDQ10G9
VSS1E1
VSS2K1
VSS3N1
VSS4T1
VSS5B2
VSS6G8
UZQE9
VSS8K9
VSSQ1F1
VSSQ2H1
VSSQ3A2
VSSQ4D2
VSSQ5E3
VSSQ6A8
VSSQ7D8
VSSQ8E8
VSSQ9C9
VSSQ10H9
VSS7T7
VREFCAM1
VPP1B1
VPP2R9
LZQF9
BG0M2
R5817 1.00K, DNI0402 1%
R5815
10.0K
0402
1%
R5805 221 Ohm0402 1%DDR4_CH0_DQS9n
DDR4_CH0_DQS9p
DDR4_CH0_DM9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR4 CH0 Part40V6_DDR4_VTT_CH00
0V6_DDR4_VTT_CH00 S10_1V2OUT_CH00
2V5_DDR4_CH00
S10_1V2OUT_CH00 S10_1V2OUT_CH00 S10_1V2OUT_CH00
0V6_DDR4_VTT_CH00 S10_1V2OUT_CH00
S10_1V2OUT_CH00
S10_1V2OUT_CH000V6_DDR4_VREF_CH00
2V5_DDR4_CH00
DDR4_CH0_A011,34,35,36
DDR4_CH0_A111,34,35,36
DDR4_CH0_A211,34,35,36
DDR4_CH0_A311,34,35,36
DDR4_CH0_A411,34,35,36
DDR4_CH0_A511,34,35,36
DDR4_CH0_A611,34,35,36
DDR4_CH0_A711,34,35,36
DDR4_CH0_A811,34,35,36
DDR4_CH0_A911,34,35,36
DDR4_CH0_A1011,34,35,36
DDR4_CH0_A1111,34,35,36
DDR4_CH0_A1211,34,35,36
DDR4_CH0_A1311,34,35,36
DDR4_CH0_A1411,34,35,36
DDR4_CH0_A1511,34,35,36
DDR4_CH0_A1611,34,35,36
DDR4_CH0_ACTn11,34,35,36
DDR4_CH0_BA011,34,35,36
DDR4_CH0_BA111,34,35,36
DDR4_CH0_BG011,34,35,36
DDR4_CH0_CKp11,34,35,36
DDR4_CH0_CKn11,34,35,36
DDR4_CH0_CKE11,34,35,36
DDR4_CH0_CSn11,34,35,36
DDR4_CH0_ODT11,34,35,36
DDR4_CH0_PAR11,34,35,36
DDR4_CH0_RESETn11,34,35,36
DDR4_CH0_BG111,34,35,36
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
37 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
37 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
37 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C2161 0.1uF0402 25V X7R
R5849 1K0402 1%
C2122 0.1uF0402 25V X7R
C2125 0.1uF0402 25V X7R
C2131 0.1uF0402 25V X7R
C2129 0.1uF0402 25V X7R
C2121 0.1uF0402 25V X7R
C2091 0.1uF0402 25V X7R
C2100 0.1uF0402 25V X7R
C2108 0.1uF0402 25V X7R
C2152 0.1uF0402 25V X7R
C2111 0.1uF0402 25V X7R
C2138 0.1uF0402 25V X7R
C2112 0.1uF0402 25V X7R
R5841 390402 1%
C2155 0.1uF0402 25V X7R
C2092 0.1uF0402 25V X7R
R5832 390402 1%
C2139 0.1uF0402 25V X7R
C2160 0.1uF0402 25V X7R
C2090 0.1uF0402 25V X7R
C2133 0.1uF0402 25V X7R
C2144 0.1uF0402 25V X7R
R5838 390402 1%
R5828 390402 1%
R5823 390402 1%
C2153 0.1uF0402 25V X7R
C2099 0.1uF0402 25V X7R
C2151 0.1uF0402 25V X7R
R5844 390402 1%
C2124 0.1uF0402 25V X7R
C2116 0.1uF0402 25V X7R
C2146 0.1uF0402 25V X7R
R5843 390402 1%
R5848 390402 1%
R5830 390402 1%
R5845 390402 1%
C2142 0.1uF0402 25V X7R
C2143 0.1uF0402 25V X7R
R5835 390402 1%
C2150 0.1uF0402 25V X7R
C2093 4.7uF0402 6.3V X5R
R5840 390402 1%
C2130 0.1uF0402 25V X7R
C2105 0.1uF0402 25V X7R
R5851 36.5 Ohm0402 1%
C2101 0.1uF0402 25V X7R
C2148 0.1uF0402 25V X7R
C2147 0.1uF0402 25V X7R
C2123 0.1uF0402 25V X7R
C2113 0.1uF0402 25V X7R C2115 0.1uF
0402 25V X7R
C3225
4.7uF
C2110 0.1uF0402 25V X7R
R5842 390402 1%
R5839 390402 1%
R5824 390402 1%
C2127 0.1uF0402 25V X7R
R5833 390402 1%
C2095 0.1uF0402 25V X7R
R5846 390402 1%
C2140 0.1uF0402 25V X7R
R5834 390402 1%
C215910nF040250VX7R
C2098 0.1uF0402 25V X7R
C2145 0.1uF0402 25V X7R
C2114 0.1uF0402 25V X7R
C2157 0.1uF0402 25V X7R
R5836 390402 1%
C2128 0.1uF0402 25V X7R
C2094 0.1uF0402 25V X7R
R5837 390402 1%
R5827 390402 1% C2102 0.1uF
0402 25V X7R
C2149 0.1uF0402 25V X7R
R5847 390402 1%
C2106 0.1uF0402 25V X7R
C2096 0.1uF0402 25V X7R
C2134 0.1uF0402 25V X7R
C2109 0.1uF0402 25V X7R
C2097 4.7uF0402 6.3V X5R
R5826 390402 1%
C2136 0.1uF0402 25V X7R
C2120 0.1uF0402 25V X7R
R5829 390402 1%
C2137 0.1uF0402 25V X7R
C2107 0.1uF0402 25V X7R
C2154 0.1uF0402 25V X7R
C2117 0.1uF0402 25V X7R
R5831 390402 1%
C2135 0.1uF0402 25V X7R
C2141 0.1uF0402 25V X7R
C2126 0.1uF0402 25V X7R
C2158 0.1uF0402 25V X7R
C2119 0.1uF0402 25V X7R
C2103 0.1uF0402 25V X7R
C2104 0.1uF0402 25V X7R
R5850 1.00K, DNI0402 1%
C2132 0.1uF0402 25V X7R
R5825 390402 1%
R5852 36.5 Ohm0402 1%
C2118 0.1uF0402 25V X7R
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Byte 0
Byte 1 Byte 3
Byte 2
When using singledie DDR4, set UZQresistor to 0-ohm
When using singledie DDR4, set UZQresistor to 0-ohm
Place near pin E9of each device
Place near pin E9of each device
DDR4 CH1 Part1
0V6_DDR4_VREF_CH110V6_DDR4_VREF_CH11
2V5_DDR4_CH11 2V5_DDR4_CH11
S10_1V2OUT_CH11S10_1V2OUT_CH11
DDR4_CH1_BA09,38,39,40,41
DDR4_CH1_A169,38,39,40,41DDR4_CH1_A159,38,39,40,41DDR4_CH1_A149,38,39,40,41
DDR4_CH1_A139,38,39,40,41DDR4_CH1_A129,38,39,40,41DDR4_CH1_A119,38,39,40,41DDR4_CH1_A109,38,39,40,41
DDR4_CH1_A99,38,39,40,41DDR4_CH1_A89,38,39,40,41DDR4_CH1_A79,38,39,40,41DDR4_CH1_A69,38,39,40,41DDR4_CH1_A59,38,39,40,41DDR4_CH1_A49,38,39,40,41DDR4_CH1_A39,38,39,40,41DDR4_CH1_A29,38,39,40,41DDR4_CH1_A19,38,39,40,41DDR4_CH1_A09,38,39,40,41
DDR4_CH1_BA19,38,39,40,41
DDR4_CH1_BG19,38,39,40,41
DDR4_CH1_DQ0 9DDR4_CH1_DQ1 9DDR4_CH1_DQ2 9DDR4_CH1_DQ3 9DDR4_CH1_DQ4 9DDR4_CH1_DQ5 9DDR4_CH1_DQ6 9DDR4_CH1_DQ7 9DDR4_CH1_DQ8 9DDR4_CH1_DQ9 9DDR4_CH1_DQ10 9DDR4_CH1_DQ11 9DDR4_CH1_DQ12 9DDR4_CH1_DQ13 9DDR4_CH1_DQ14 9DDR4_CH1_DQ15 9
DDR4_CH1_A09,38,39,40,41 DDR4_CH1_DQ16 9DDR4_CH1_A19,38,39,40,41 DDR4_CH1_DQ17 9DDR4_CH1_A29,38,39,40,41 DDR4_CH1_DQ18 9DDR4_CH1_A39,38,39,40,41 DDR4_CH1_DQ19 9DDR4_CH1_A49,38,39,40,41 DDR4_CH1_DQ20 9DDR4_CH1_A59,38,39,40,41 DDR4_CH1_DQ21 9DDR4_CH1_A69,38,39,40,41 DDR4_CH1_DQ22 9DDR4_CH1_A79,38,39,40,41 DDR4_CH1_DQ23 9DDR4_CH1_A89,38,39,40,41 DDR4_CH1_DQ24 9DDR4_CH1_A99,38,39,40,41 DDR4_CH1_DQ25 9
DDR4_CH1_A109,38,39,40,41 DDR4_CH1_DQ26 9DDR4_CH1_A119,38,39,40,41 DDR4_CH1_DQ27 9DDR4_CH1_A129,38,39,40,41 DDR4_CH1_DQ28 9DDR4_CH1_A139,38,39,40,41 DDR4_CH1_DQ29 9
DDR4_CH1_DQ30 9DDR4_CH1_A149,38,39,40,41 DDR4_CH1_DQ31 9DDR4_CH1_A159,38,39,40,41DDR4_CH1_A169,38,39,40,41
DDR4_CH1_BA09,38,39,40,41DDR4_CH1_BA19,38,39,40,41
DDR4_CH1_BG19,38,39,40,41
DDR4_CH1_PAR9,38,39,40,41
DDR4_CH1_ALERTn 9,38,39,40
DDR4_CH1_CKE9,38,39,40,41
DDR4_CH1_CKp9,38,39,40,41DDR4_CH1_CKn9,38,39,40,41
DDR4_CH1_CSn9,38,39,40,41
DDR4_CH1_ODT9,38,39,40,41
DDR4_CH1_ACTn9,38,39,40,41
DDR4_CH1_RESETn9,38,39,40,41
DDR4_CH1_CKp9,38,39,40,41DDR4_CH1_CKn9,38,39,40,41
DDR4_CH1_CKE9,38,39,40,41
DDR4_CH1_CSn9,38,39,40,41
DDR4_CH1_ODT9,38,39,40,41DDR4_CH1_PAR9,38,39,40,41
DDR4_CH1_RESETn9,38,39,40,41
DDR4_CH1_ACTn9,38,39,40,41DDR4_CH1_DQS0n 9DDR4_CH1_DQS0p 9
DDR4_CH1_DQS1n 9DDR4_CH1_DQS1p 9
DDR4_CH1_DQS2p 9DDR4_CH1_DQS2n 9
DDR4_CH1_DQS3p 9DDR4_CH1_DQS3n 9
DDR4_CH1_ALERTn 9,38,39,40
DDR4_CH1_TEN38,39,40 DDR4_CH1_TEN38,39,40
DDR4_CH1_DM09DDR4_CH1_DM19
DDR4_CH1_DM29DDR4_CH1_DM39
DDR4_CH1_BG09,38,39,40,41 DDR4_CH1_BG09,38,39,40,41
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
38 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
38 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
38 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R591824004021%
DDR4 x 16
U153
MT40A1G16KNR-075:E
A0P3
A1P7
A2R3
A3N7
A4N3
A5P8
A6P2
A7R8
A8R2
A9R7
A10/APM3
A11T2
A12/BCnM7
A13T8
A14/WEnL2
A15/CASnM8
A16/RASnL8
ACTnL3
BA0N2
BA1N8
BG1M9
CK_TK7
CK_CK8
CKEK2
CSnL7
NF/LDMn/LDBInE7
NF/UDMn/UDBInE2
ODTK3
PART3
RESETnP1
TENN9
DQ0G2
DQ1F7
DQ2H3
DQ3H7
DQ4H2
DQ5H8
DQ6J3
DQ7J7
DQ8A3
DQ9B8
DQ10C3
DQ11C7
DQ12C2
DQ13C8
DQ14D3
DQ15D7
DQSL_TG3
DQSL_CF3
DQSU_TB7
DQSU_CA7
ALERTnP9
VDD1D1
VDD2J1
VDD3L1
VDD4R1
VDD5B3
VDD6G7
VDD7B9
VDD8J9
VDD9L9
VDD10T9
VDDQ1A1
VDDQ2C1
VDDQ3G1
VDDQ4F2
VDDQ5J2
VDDQ6F8
VDDQ7J8
VDDQ8A9
VDDQ9D9
VDDQ10G9
VSS1E1
VSS2K1
VSS3N1
VSS4T1
VSS5B2
VSS6G8
UZQE9
VSS8K9
VSSQ1F1
VSSQ2H1
VSSQ3A2
VSSQ4D2
VSSQ5E3
VSSQ6A8
VSSQ7D8
VSSQ8E8
VSSQ9C9
VSSQ10H9
VSS7T7
VREFCAM1
VPP1B1
VPP2R9
LZQF9
BG0M2
R5915240
04021%
DDR4 x 16
U152
MT40A1G16KNR-075:E
A0P3
A1P7
A2R3
A3N7
A4N3
A5P8
A6P2
A7R8
A8R2
A9R7
A10/APM3
A11T2
A12/BCnM7
A13T8
A14/WEnL2
A15/CASnM8
A16/RASnL8
ACTnL3
BA0N2
BA1N8
BG1M9
CK_TK7
CK_CK8
CKEK2
CSnL7
NF/LDMn/LDBInE7
NF/UDMn/UDBInE2
ODTK3
PART3
RESETnP1
TENN9
DQ0G2
DQ1F7
DQ2H3
DQ3H7
DQ4H2
DQ5H8
DQ6J3
DQ7J7
DQ8A3
DQ9B8
DQ10C3
DQ11C7
DQ12C2
DQ13C8
DQ14D3
DQ15D7
DQSL_TG3
DQSL_CF3
DQSU_TB7
DQSU_CA7
ALERTnP9
VDD1D1
VDD2J1
VDD3L1
VDD4R1
VDD5B3
VDD6G7
VDD7B9
VDD8J9
VDD9L9
VDD10T9
VDDQ1A1
VDDQ2C1
VDDQ3G1
VDDQ4F2
VDDQ5J2
VDDQ6F8
VDDQ7J8
VDDQ8A9
VDDQ9D9
VDDQ10G9
VSS1E1
VSS2K1
VSS3N1
VSS4T1
VSS5B2
VSS6G8
UZQE9
VSS8K9
VSSQ1F1
VSSQ2H1
VSSQ3A2
VSSQ4D2
VSSQ5E3
VSSQ6A8
VSSQ7D8
VSSQ8E8
VSSQ9C9
VSSQ10H9
VSS7T7
VREFCAM1
VPP1B1
VPP2R9
LZQF9
BG0M2
R591624004021%
R59140, DNI
04025%
R5917240
04021%
R59130, DNI
04025%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Byte 5
Byte 4
Byte 7
Byte 6
When using singledie DDR4, set UZQresistor to 0-ohm
Place near pin E9of each devicePlace near pin E9
of each device
When using singledie DDR4, set UZQresistor to 0-ohm
DDR4 CH1 Part2
0V6_DDR4_VREF_CH110V6_DDR4_VREF_CH11
2V5_DDR4_CH11 2V5_DDR4_CH11
S10_1V2OUT_CH11S10_1V2OUT_CH11
DDR4_CH1_BA09,38,39,40,41
DDR4_CH1_A169,38,39,40,41DDR4_CH1_A159,38,39,40,41DDR4_CH1_A149,38,39,40,41
DDR4_CH1_A139,38,39,40,41DDR4_CH1_A129,38,39,40,41DDR4_CH1_A119,38,39,40,41DDR4_CH1_A109,38,39,40,41
DDR4_CH1_A99,38,39,40,41DDR4_CH1_A89,38,39,40,41DDR4_CH1_A79,38,39,40,41DDR4_CH1_A69,38,39,40,41DDR4_CH1_A59,38,39,40,41DDR4_CH1_A49,38,39,40,41DDR4_CH1_A39,38,39,40,41DDR4_CH1_A29,38,39,40,41DDR4_CH1_A19,38,39,40,41DDR4_CH1_A09,38,39,40,41
DDR4_CH1_BA19,38,39,40,41
DDR4_CH1_BG19,38,39,40,41
DDR4_CH1_DQ32 9DDR4_CH1_DQ33 9DDR4_CH1_DQ34 9DDR4_CH1_DQ35 9DDR4_CH1_DQ36 9DDR4_CH1_DQ37 9DDR4_CH1_DQ38 9DDR4_CH1_DQ39 9DDR4_CH1_DQ40 9DDR4_CH1_DQ41 9DDR4_CH1_DQ42 9DDR4_CH1_DQ43 9DDR4_CH1_DQ44 9DDR4_CH1_DQ45 9DDR4_CH1_DQ46 9DDR4_CH1_DQ47 9
DDR4_CH1_A09,38,39,40,41 DDR4_CH1_DQ48 9DDR4_CH1_A19,38,39,40,41 DDR4_CH1_DQ49 9DDR4_CH1_A29,38,39,40,41 DDR4_CH1_DQ50 9DDR4_CH1_A39,38,39,40,41 DDR4_CH1_DQ51 9DDR4_CH1_A49,38,39,40,41 DDR4_CH1_DQ52 9DDR4_CH1_A59,38,39,40,41 DDR4_CH1_DQ53 9DDR4_CH1_A69,38,39,40,41 DDR4_CH1_DQ54 9DDR4_CH1_A79,38,39,40,41 DDR4_CH1_DQ55 9DDR4_CH1_A89,38,39,40,41 DDR4_CH1_DQ56 9DDR4_CH1_A99,38,39,40,41 DDR4_CH1_DQ57 9
DDR4_CH1_A109,38,39,40,41 DDR4_CH1_DQ58 9DDR4_CH1_A119,38,39,40,41 DDR4_CH1_DQ59 9DDR4_CH1_A129,38,39,40,41 DDR4_CH1_DQ60 9DDR4_CH1_A139,38,39,40,41 DDR4_CH1_DQ61 9
DDR4_CH1_DQ62 9DDR4_CH1_A149,38,39,40,41 DDR4_CH1_DQ63 9DDR4_CH1_A159,38,39,40,41DDR4_CH1_A169,38,39,40,41
DDR4_CH1_BA09,38,39,40,41DDR4_CH1_BA19,38,39,40,41
DDR4_CH1_BG19,38,39,40,41
DDR4_CH1_PAR9,38,39,40,41
DDR4_CH1_ALERTn 9,38,39,40
DDR4_CH1_CKE9,38,39,40,41
DDR4_CH1_CKp9,38,39,40,41DDR4_CH1_CKn9,38,39,40,41
DDR4_CH1_CSn9,38,39,40,41
DDR4_CH1_ODT9,38,39,40,41
DDR4_CH1_ACTn9,38,39,40,41
DDR4_CH1_RESETn9,38,39,40,41
DDR4_CH1_CKp9,38,39,40,41DDR4_CH1_CKn9,38,39,40,41
DDR4_CH1_CKE9,38,39,40,41
DDR4_CH1_CSn9,38,39,40,41
DDR4_CH1_ODT9,38,39,40,41DDR4_CH1_PAR9,38,39,40,41
DDR4_CH1_RESETn9,38,39,40,41
DDR4_CH1_ACTn9,38,39,40,41DDR4_CH1_DQS4n 9DDR4_CH1_DQS4p 9
DDR4_CH1_DQS5n 9DDR4_CH1_DQS5p 9
DDR4_CH1_DQS6p 9DDR4_CH1_DQS6n 9
DDR4_CH1_DQS7p 9DDR4_CH1_DQS7n 9
DDR4_CH1_ALERTn 9,38,39,40
DDR4_CH1_TEN38,39,40 DDR4_CH1_TEN38,39,40
DDR4_CH1_DM49DDR4_CH1_DM59
DDR4_CH1_DM69DDR4_CH1_DM79
DDR4_CH1_BG09,38,39,40,41 DDR4_CH1_BG09,38,39,40,41
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
39 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
39 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
39 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R5923240
04021%
DDR4 x 16
U155
MT40A1G16KNR-075:E
A0P3
A1P7
A2R3
A3N7
A4N3
A5P8
A6P2
A7R8
A8R2
A9R7
A10/APM3
A11T2
A12/BCnM7
A13T8
A14/WEnL2
A15/CASnM8
A16/RASnL8
ACTnL3
BA0N2
BA1N8
BG1M9
CK_TK7
CK_CK8
CKEK2
CSnL7
NF/LDMn/LDBInE7
NF/UDMn/UDBInE2
ODTK3
PART3
RESETnP1
TENN9
DQ0G2
DQ1F7
DQ2H3
DQ3H7
DQ4H2
DQ5H8
DQ6J3
DQ7J7
DQ8A3
DQ9B8
DQ10C3
DQ11C7
DQ12C2
DQ13C8
DQ14D3
DQ15D7
DQSL_TG3
DQSL_CF3
DQSU_TB7
DQSU_CA7
ALERTnP9
VDD1D1
VDD2J1
VDD3L1
VDD4R1
VDD5B3
VDD6G7
VDD7B9
VDD8J9
VDD9L9
VDD10T9
VDDQ1A1
VDDQ2C1
VDDQ3G1
VDDQ4F2
VDDQ5J2
VDDQ6F8
VDDQ7J8
VDDQ8A9
VDDQ9D9
VDDQ10G9
VSS1E1
VSS2K1
VSS3N1
VSS4T1
VSS5B2
VSS6G8
UZQE9
VSS8K9
VSSQ1F1
VSSQ2H1
VSSQ3A2
VSSQ4D2
VSSQ5E3
VSSQ6A8
VSSQ7D8
VSSQ8E8
VSSQ9C9
VSSQ10H9
VSS7T7
VREFCAM1
VPP1B1
VPP2R9
LZQF9
BG0M2
R59200, DNI
04025%
DDR4 x 16
U154
MT40A1G16KNR-075:E
A0P3
A1P7
A2R3
A3N7
A4N3
A5P8
A6P2
A7R8
A8R2
A9R7
A10/APM3
A11T2
A12/BCnM7
A13T8
A14/WEnL2
A15/CASnM8
A16/RASnL8
ACTnL3
BA0N2
BA1N8
BG1M9
CK_TK7
CK_CK8
CKEK2
CSnL7
NF/LDMn/LDBInE7
NF/UDMn/UDBInE2
ODTK3
PART3
RESETnP1
TENN9
DQ0G2
DQ1F7
DQ2H3
DQ3H7
DQ4H2
DQ5H8
DQ6J3
DQ7J7
DQ8A3
DQ9B8
DQ10C3
DQ11C7
DQ12C2
DQ13C8
DQ14D3
DQ15D7
DQSL_TG3
DQSL_CF3
DQSU_TB7
DQSU_CA7
ALERTnP9
VDD1D1
VDD2J1
VDD3L1
VDD4R1
VDD5B3
VDD6G7
VDD7B9
VDD8J9
VDD9L9
VDD10T9
VDDQ1A1
VDDQ2C1
VDDQ3G1
VDDQ4F2
VDDQ5J2
VDDQ6F8
VDDQ7J8
VDDQ8A9
VDDQ9D9
VDDQ10G9
VSS1E1
VSS2K1
VSS3N1
VSS4T1
VSS5B2
VSS6G8
UZQE9
VSS8K9
VSSQ1F1
VSSQ2H1
VSSQ3A2
VSSQ4D2
VSSQ5E3
VSSQ6A8
VSSQ7D8
VSSQ8E8
VSSQ9C9
VSSQ10H9
VSS7T7
VREFCAM1
VPP1B1
VPP2R9
LZQF9
BG0M2
R5921240
04021%
R592224004021%
R59190, DNI
04025%
R592424004021%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Byte 8
When using singledie DDR4, set UZQresistor to 0-ohm
TEN is active high (TEN should be low for normal operation)When FPGA drive TEN to 1.8V, DDR4 input is 1.12VHigh = 0.8*VDD = 960mVLow = 0.2*VDD = 240mV
Place near pin E9of each device
DDR4 CH1 Part3
0V6_DDR4_VREF_CH11
2V5_DDR4_CH11
S10_1V2OUT_CH11
S10_1V2OUT_CH11
S10_1V2OUT_CH11
S10_1V2OUT_CH11
DDR4_CH1_BA09,38,39,41
DDR4_CH1_A169,38,39,41DDR4_CH1_A159,38,39,41DDR4_CH1_A149,38,39,41
DDR4_CH1_A139,38,39,41DDR4_CH1_A129,38,39,41DDR4_CH1_A119,38,39,41DDR4_CH1_A109,38,39,41
DDR4_CH1_A99,38,39,41DDR4_CH1_A89,38,39,41DDR4_CH1_A79,38,39,41DDR4_CH1_A69,38,39,41DDR4_CH1_A59,38,39,41DDR4_CH1_A49,38,39,41DDR4_CH1_A39,38,39,41DDR4_CH1_A29,38,39,41DDR4_CH1_A19,38,39,41DDR4_CH1_A09,38,39,41
DDR4_CH1_BA19,38,39,41
DDR4_CH1_BG19,38,39,41
DDR4_CH1_DQ64 9DDR4_CH1_DQ65 9DDR4_CH1_DQ66 9DDR4_CH1_DQ67 9DDR4_CH1_DQ68 9DDR4_CH1_DQ69 9DDR4_CH1_DQ70 9DDR4_CH1_DQ71 9
DDR4_CH1_PAR9,38,39,41
DDR4_CH1_ALERTn 9,38,39DDR4_CH1_CKE9,38,39,41
DDR4_CH1_CKp9,38,39,41DDR4_CH1_CKn9,38,39,41
DDR4_CH1_CSn9,38,39,41
DDR4_CH1_ODT9,38,39,41
DDR4_CH1_ACTn9,38,39,41
DDR4_CH1_RESETn9,38,39,41
DDR4_CH1_DQS8n 9DDR4_CH1_DQS8p 9
DDR4_CH1_TEN38,39
DDR4_CH1_DM89
DDR4_CH1_BG09,38,39,41
DDR4_CH1_TEN_1V88
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
40 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
40 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
40 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R59400, DNI
04025%
R594224004021%
DDR4 x 16
U156
MT40A1G16KNR-075:E
A0P3
A1P7
A2R3
A3N7
A4N3
A5P8
A6P2
A7R8
A8R2
A9R7
A10/APM3
A11T2
A12/BCnM7
A13T8
A14/WEnL2
A15/CASnM8
A16/RASnL8
ACTnL3
BA0N2
BA1N8
BG1M9
CK_TK7
CK_CK8
CKEK2
CSnL7
NF/LDMn/LDBInE7
NF/UDMn/UDBInE2
ODTK3
PART3
RESETnP1
TENN9
DQ0G2
DQ1F7
DQ2H3
DQ3H7
DQ4H2
DQ5H8
DQ6J3
DQ7J7
DQ8A3
DQ9B8
DQ10C3
DQ11C7
DQ12C2
DQ13C8
DQ14D3
DQ15D7
DQSL_TG3
DQSL_CF3
DQSU_TB7
DQSU_CA7
ALERTnP9
VDD1D1
VDD2J1
VDD3L1
VDD4R1
VDD5B3
VDD6G7
VDD7B9
VDD8J9
VDD9L9
VDD10T9
VDDQ1A1
VDDQ2C1
VDDQ3G1
VDDQ4F2
VDDQ5J2
VDDQ6F8
VDDQ7J8
VDDQ8A9
VDDQ9D9
VDDQ10G9
VSS1E1
VSS2K1
VSS3N1
VSS4T1
VSS5B2
VSS6G8
UZQE9
VSS8K9
VSSQ1F1
VSSQ2H1
VSSQ3A2
VSSQ4D2
VSSQ5E3
VSSQ6A8
VSSQ7D8
VSSQ8E8
VSSQ9C9
VSSQ10H9
VSS7T7
VREFCAM1
VPP1B1
VPP2R9
LZQF9
BG0M2
R5936 221 Ohm0402 1%
R5935
10.0K
0402
1%
R5941240
04021%
R5938 2.87k0402 0.1%
R5925 221 Ohm0402 1%R5934 221 Ohm0402 1%
R59394.70K
0.1%0402
R5937 1.00K, DNI0402 1%
DDR4_CH1_DQS9nDDR4_CH1_DQS9p
DDR4_CH1_DM9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR4 CH1 Part40V6_DDR4_VTT_CH11
0V6_DDR4_VTT_CH11 S10_1V2OUT_CH11
2V5_DDR4_CH11
S10_1V2OUT_CH11 S10_1V2OUT_CH11 S10_1V2OUT_CH11
0V6_DDR4_VTT_CH11 S10_1V2OUT_CH11
S10_1V2OUT_CH11
S10_1V2OUT_CH110V6_DDR4_VREF_CH11
2V5_DDR4_CH11
DDR4_CH1_A09,38,39,40
DDR4_CH1_A19,38,39,40
DDR4_CH1_A29,38,39,40
DDR4_CH1_A39,38,39,40
DDR4_CH1_A49,38,39,40
DDR4_CH1_A59,38,39,40
DDR4_CH1_A69,38,39,40
DDR4_CH1_A79,38,39,40
DDR4_CH1_A89,38,39,40
DDR4_CH1_A99,38,39,40
DDR4_CH1_A109,38,39,40
DDR4_CH1_A119,38,39,40
DDR4_CH1_A129,38,39,40
DDR4_CH1_A139,38,39,40
DDR4_CH1_A149,38,39,40
DDR4_CH1_A159,38,39,40
DDR4_CH1_A169,38,39,40
DDR4_CH1_ACTn9,38,39,40
DDR4_CH1_BA09,38,39,40
DDR4_CH1_BA19,38,39,40
DDR4_CH1_BG09,38,39,40
DDR4_CH1_CKp9,38,39,40
DDR4_CH1_CKn9,38,39,40
DDR4_CH1_CKE9,38,39,40
DDR4_CH1_CSn9,38,39,40
DDR4_CH1_ODT9,38,39,40
DDR4_CH1_PAR9,38,39,40
DDR4_CH1_RESETn9,38,39,40
DDR4_CH1_BG19,38,39,40
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
41 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
41 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
41 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R5957 390402 1%
R5963 390402 1%
C2293 0.1uF0402 25V X7R
C2263 0.1uF0402 25V X7R
C2271 0.1uF0402 25V X7R
C2236 0.1uF0402 25V X7R
C2282 0.1uF0402 25V X7R
C2247 0.1uF0402 25V X7R
C2253 0.1uF0402 25V X7R
C2288 0.1uF0402 25V X7R
C2252 0.1uF0402 25V X7R
C1647
4.7uF
C2234 0.1uF0402 25V X7R
C2262 0.1uF0402 25V X7R
R5946 390402 1%
C2256 0.1uF0402 25V X7R
R5952 390402 1%
C2284 0.1uF0402 25V X7R
R5958 390402 1%
C2280 0.1uF0402 25V X7R
C2302 0.1uF0402 25V X7R
C2265 0.1uF0402 25V X7R
C2249 0.1uF0402 25V X7R
R5964 390402 1%
C2297 0.1uF0402 25V X7R
R5972 36.5 Ohm0402 1%
C2235 0.1uF0402 25V X7R
C2250 0.1uF0402 25V X7R
C2290 0.1uF0402 25V X7R
C2260 0.1uF0402 25V X7R
C2266 0.1uF0402 25V X7R
C2298 0.1uF0402 25V X7R
R5947 390402 1%
R5953 390402 1%
R5959 390402 1%
R5965 390402 1%
R5971 36.5 Ohm0402 1%
C2303 0.1uF0402 25V X7R
C2287 0.1uF0402 25V X7R
C2237 4.7uF0402 6.3V X5R
C2255 0.1uF0402 25V X7R
C2268 0.1uF0402 25V X7R
C2296 0.1uF0402 25V X7R
C2241 4.7uF0402 6.3V X5R
C2301 0.1uF0402 25V X7R
C2277 0.1uF0402 25V X7R
C2289 0.1uF0402 25V X7R
C2258 0.1uF0402 25V X7R
C230410nF040250VX7R
R5943 390402 1%
R5948 390402 1%
C2295 0.1uF0402 25V X7R
R5954 390402 1%
C2275 0.1uF0402 25V X7R
R5960 390402 1%
C2285 0.1uF0402 25V X7R
R5966 390402 1%
C2244 0.1uF0402 25V X7R
C2267 0.1uF0402 25V X7R
C2248 0.1uF0402 25V X7R
C2292 0.1uF0402 25V X7R
C2246 0.1uF0402 25V X7R
C2299 0.1uF0402 25V X7R
C2240 0.1uF0402 25V X7R
C2276 0.1uF0402 25V X7R
C2278 0.1uF0402 25V X7R
C2259 0.1uF0402 25V X7R
C2254 0.1uF0402 25V X7R
R5949 390402 1%
R5955 390402 1%
C2305 0.1uF0402 25V X7R
R5961 390402 1%
C2257 0.1uF0402 25V X7R
C2272 0.1uF0402 25V X7R
C2269 0.1uF0402 25V X7R
R5967 390402 1%
C2251 0.1uF0402 25V X7R
C2245 0.1uF0402 25V X7R
C2264 0.1uF0402 25V X7R
C2283 0.1uF0402 25V X7R
C2243 0.1uF0402 25V X7R
C2242 0.1uF0402 25V X7R
C2294 0.1uF0402 25V X7R
C2238 0.1uF0402 25V X7R
C2281 0.1uF0402 25V X7R
R5944 390402 1%
C2261 0.1uF0402 25V X7R
R5950 390402 1%
C2286 0.1uF0402 25V X7R
R5956 390402 1%
R5962 390402 1%
R5968 390402 1%
C2274 0.1uF0402 25V X7R
C2291 0.1uF0402 25V X7R
C2270 0.1uF0402 25V X7R
C2239 0.1uF0402 25V X7R
R5969 1K0402 1%R5970 1.00K, DNI0402 1%
C2279 0.1uF0402 25V X7R
R5945 390402 1%
R5951 390402 1%
C2273 0.1uF0402 25V X7R
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR4 DIMM CH0 IF
DDR4/DDRT DIMM CH0
Put caps on VDD pins which are close to DIMM A/C pins
S10_1V2OUT_CH00
S10_1V2OUT_CH00
2V5_DDR4_CH00
S10_1V2OUT_CH00
S10_1V2OUT_CH00
0V6_DDR4_VTT_CH00
2V5_DDR4_CH00
2V5_DDR4_CH00
12V_AUX2_IN
0V6_DDR4_VREF_CH00
2V5_DDR4_CH00
2V5_DDR4_CH000V6_DDR4_VTT_CH000V6_DDR4_VREF_CH00
0V6_DDR4_VTT_CH00S10_1V2OUT_CH00
1.8V
S10_1V2OUT_CH00 S10_1V2OUT_CH00
0V6_DDR4_VTT_CH00
1.8V
2V5_DDR4_CH00
2V5_DDR4_CH00
2V5_DDR4_CH00 M10_3.3V
DDR4_DIMM_CH0_C210
DDR4_DIMM_CH0_EVENT_N8
DDR4_DIMM_CH0_DQ[71:0]10
DDR4_DIMM_CH0_A[17:0]10
DDR4_DIMM_CH0_DQS_P[17:0]10
DDR4_DIMM_CH0_CKE[1:0]10
DDR4_DIMM_CH0_CK_P[1:0]10
DDR4_DIMM_CH0_DQS_N[17:0]10
DDR4_DIMM_CH0_ODT[1:0]10
DDR4_DIMM_CH0_RESET_N10
DDR4_DIMM_CH0_CK_N[1:0]10
DDR4_DIMM_CH0_CS_N[3:0]10
DDR4_DIMM_CH0_BG[1:0]10DDR4_DIMM_CH0_BA[1:0]10
DDR4_DIMM_CH0_ACT_N10
DDR4_DIMM_CH0_PAR10DDR4_DIMM_CH0_ALERT_N10
DDR4_DIMM_CH0_SAVE_N8
I2C_DDR4T_0_2V5_SDA43I2C_DDR4T_0_2V5_SCL43
I2C1_SDA23,49,55,63,68I2C1_SCL23,49,55,63,68
I2C_DDR4T_0_S10_SDA8I2C_DDR4T_0_S10_SCL8
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
42 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
42 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
42 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.C123 10nF
C16
0.1uF
C112100uF120610VX5R
C111100uF120610VX5R
C85 0.1uF
C116
10uF
R6392 0
C17
1uF
J73A
DDR4x72x288
Vss2
DQ43
Vss4
DQ05
Vss6
DQS9_t/DM0_n/DBI0_n7
DQS9_c8
Vss9
DQ610
Vss11
Vss13
Vss15
Vss17
Vss20
Vss22
Vss24
Vss26
Vss28
Vss31
Vss33
Vss35
Vss37
DQ212
DQ1214
DQ816
DQ1421
DQ1023
DQ2025
DQ1627
DQ2232
DQ1834
DQ2836
DQS10_t/DM1_n/DBI1_n18
DQS10_c19
DQS11_t/DM2_n/DBI2_n29
DQS11_c30
DQ2438
DQ3043
DQ2645
Vss39
Vss42
DQS12_t/DM3_n/DBI3_n40
DQS12_c41
Vss44
Vss46
Vss48
Vss50
Vss53
Vss55
Vss57
Vdd59
Vdd61
CB4/NC47
CB0/NC49
DQS17_t/DM8_n/DBI8_n51
DQS17_c52
CB6/NC54
CB2/NC56
RESET_n58
Vdd64
Vdd67
Vdd70
Vdd73
CKE060
ACT_n62
BG063
A1265
A966
A868
A669
A371
A172
CK0_t74
CK0_c75
Vdd76
Vtt77
Vrefca146
Vss147
Vss149
Vss151
Vss154
Vss156
Vss158
Vss160
Vss162
Vss165
DQ5148
DQ1150
DQ7155
DQ3157
DQ13159
DQ9161
DQ15166
DQS0_c152
DQS0_t153
DQS1_c163
DQS1_t164
Vss167
Vss169
Vss171
Vss173
Vss176
Vss178
Vss180
DQ11168
DQ21170
DQ17172
DQS2_c174
DQS2_t175
DQ23177
DQ19179
DQ29181
Vss182
Vss184
Vss187
Vss189
Vss191
Vss193
Vss195
DQ25183
DQ31188
DQ27190
CB5/NC192
CB1/NC194
Vss198
Vss200
Vss202
Vdd204
Vdd206
Vdd209
Vdd212
Vdd215
Vdd217
CB7/NC199
CB3/NC201
CKE1203
RFU2205
BG1207
ALERT_n208
A11210
A7211
A5213
A4214
A2216
Vdd220
CK1_t218
CK1_c219
Vtt221
DQS3_c185
DQS3_t186
DQS8_c196
DQS8_t197
12V/NC1
12V/NC145
C101
0.1uF
C3
0.1uF
C86
0.1uF
C2
1uF
C18
0.1uF
R19 10.0KR21 DNI
C114
0.1uF
U2
MAX3378EETD+T
VL10
IO VL11
IO VL22
IO VL35
IO VL46
GND7
VCC14
IO VCC113
IO VCC212
IO VCC39
IO VCC48
TS3
NC14
NC211
EP15
C115
0.1uF
R27 0
C118
10uF
J73B
DDR4x72x288
EVENT_n78
A079
Vdd80
BA081
RAS_n/A1682
Vdd83
S0_n84
Vdd85
Vdd88
Vdd90
Vdd92
Vss94
Vss98
Vss101
Vss103
Vss105
Vss107
Vss109
CAS_n/A1586
ODT087
S1_n89
ODT191
S2_n/C093
DQ3695
DQ3297 Vss96
DQS13_t/DM4_n/DBI4_n99
DQS13_c100
DQ38102
DQ34104
DQ44106
DQ40108
DQS14_t/DM5_n/DBI5_n110
DQS14_c111
Vss112
Vss114
Vss116
Vss118
Vss120
Vss123
Vss125
Vss127
Vss129
Vss131
Vss134
Vss136
Vss138
Vpp142
Vpp143
RFU1144
DQ46113
DQ42115
DQ52117
DQ48119
DQS15_t/DM6_n/DBI6_n121
DQS15_c122
DQ54124
DQ50126
DQ60128
DQ56130
DQS16_t/DM7_n/DBI7_n132
DQS16_c133
DQ62135
DQ58137
SA0139
SA1140
SCL141
PARITY222
Vdd223
BA1224
A10/AP225
Vdd226
Vdd229
Vdd231
Vdd233
Vdd236
Vss239
Vss241
Vss243
Vss246
Vss248
Vss250
Vss252
Vss254
RFU3227
WE_n/A14228
SAVE_n/NC230
A13232
A17/NC234
C2/NC235
S3_n/C1237
SA2/RFU238
DQ37240
DQ33242
DQS4_c244
DQS4_t245
DQ39247
DQ35249
DQ45251
DQ41253
Vss257
Vss259
Vss261
Vss263
Vss265
DQS6_t267
Vss270
Vss272
Vss274
Vss276
Vss279
Vss281
Vss283
Vpp286
Vpp287
Vpp288
DQS5_c255
DQS5_t256
DQ47258
DQ43260
DQ53262
DQ49264
DQS6_c266
Vss268
DQ55269
DQ51271
DQ61273
DQ57275
DQS7_c277
DQS7_t278
DQ63280
DQ59282
Vddspd284
SDA285
U3
MAX3378EETD+T
VL10
IO VL11
IO VL22
IO VL35
IO VL46
GND7
VCC14
IO VCC113
IO VCC212
IO VCC39
IO VCC48
TS3
NC14
NC211
EP15
R36 0
C97 0.1uF
C119
10nF
R6381 0
C4
10nF
C125 0.1uF
C120
10nF
R29 10.0K
C7
0.1uF
C96 0.1uF
C127
10nF
R63960
C99
100uF
R10 0
C121
10uF
C124
10nF
C70100uF120610VX5R
R6380 0
C149 0.1uF
R18 0
R63990
C126
10nF
C69
0.1uF
C148
10nF
R46 0
R24 10.0K
R45 10.0K,DNI
C5
0.1uF
R6393 0
C84 0.1uFC100
1uF
C113
0.1uF
C6
0.1uF
R31 0
R63980
C117
10nF
R39 10.0K
C122
10nF
R63970
C98
0.1uF
DDR4_DIMM_CH0_C2
DDR4_CH0_EVENT_N DDR4_DIMM_CH0_EVENT_NDDR4_DIMM_CH0_SAVE_NDDR4_CH0_SAVE_N
DDR4_DIMM_CH0_DQ63
DDR4_DIMM_CH0_A11
DDR4_DIMM_CH0_A10
DDR4_DIMM_CH0_DQS_N9
DDR4_DIMM_CH0_DQS_N12
DDR4_DIMM_CH0_DQS_N13
DDR4_DIMM_CH0_DQS_N14
DDR4_DIMM_CH0_DQS_N10
DDR4_DIMM_CH0_DQS_N11
DDR4_DIMM_CH0_DQS_N15
DDR4_DIMM_CH0_DQS_N16
DDR4_DIMM_CH0_DQS_N17
DDR4_CH0_SAVE_N
DDR4_DIMM_CH0_SA1DDR4_DIMM_CH0_SA0
DDR4_DIMM_CH0_DQS_P9
DDR4_DIMM_CH0_DQS_P8DDR4_DIMM_CH0_DQS_N8
DDR4_DIMM_CH0_CK_P1DDR4_DIMM_CH0_CK_N1
DDR4_DIMM_CH0_DQS_P6
DDR4_DIMM_CH0_DQ55
DDR4_DIMM_CH0_DQ51
DDR4_DIMM_CH0_CKE1
DDR4_DIMM_CH0_CS_N0
DDR4_CH0_EVENT_N
DDR4_CH0_SAVE_N
DDR4_DIMM_CH0_PAR
DDR4_DIMM_CH0_ALERT_N
DDR4_DIMM_CH0_ACT_N
DDR4_DIMM_CH0_CKE0
DDR4_DIMM_CH0_CK_P0DDR4_DIMM_CH0_CK_N0
DDR4_DIMM_CH0_A1 DDR4_DIMM_CH0_A2DDR4_DIMM_CH0_A3
DDR4_DIMM_CH0_BG1
DDR4_DIMM_CH0_RESET_N
DDR4_DIMM_CH0_A8
DDR4_DIMM_CH0_A9DDR4_DIMM_CH0_A12
DDR4_DIMM_CH0_A0
DDR4_DIMM_CH0_BG0
DDR4_DIMM_CH0_DQ1
DDR4_DIMM_CH0_DQ2DDR4_DIMM_CH0_DQ3
DDR4_DIMM_CH0_A4DDR4_DIMM_CH0_A5
DDR4_DIMM_CH0_DQ6DDR4_DIMM_CH0_DQ7
DDR4_DIMM_CH0_DQ8DDR4_DIMM_CH0_DQ9
DDR4_DIMM_CH0_DQ0
DDR4_DIMM_CH0_DQ12DDR4_DIMM_CH0_DQ13
DDR4_DIMM_CH0_DQ14
DDR4_DIMM_CH0_DQ4DDR4_DIMM_CH0_DQ5
DDR4_DIMM_CH0_DQ17
DDR4_DIMM_CH0_DQ18DDR4_DIMM_CH0_DQ19
DDR4_DIMM_CH0_DQ10DDR4_DIMM_CH0_DQ11
DDR4_DIMM_CH0_DQ22DDR4_DIMM_CH0_DQ23
DDR4_DIMM_CH0_DQ24
DDR4_DIMM_CH0_DQ15
DDR4_DIMM_CH0_DQ16
DDR4_DIMM_CH0_DQ27
DDR4_DIMM_CH0_DQ28DDR4_DIMM_CH0_DQ29
DDR4_DIMM_CH0_DQ20DDR4_DIMM_CH0_DQ21
DDR4_DIMM_CH0_DQ32DDR4_DIMM_CH0_DQ33
DDR4_DIMM_CH0_DQ34DDR4_DIMM_CH0_DQ35
DDR4_DIMM_CH0_DQ25
DDR4_DIMM_CH0_DQ26
DDR4_DIMM_CH0_DQ38DDR4_DIMM_CH0_DQ39
DDR4_DIMM_CH0_DQ40
DDR4_DIMM_CH0_DQ30DDR4_DIMM_CH0_DQ31
DDR4_DIMM_CH0_DQ44DDR4_DIMM_CH0_DQ45
DDR4_DIMM_CH0_DQ36DDR4_DIMM_CH0_DQ37
DDR4_DIMM_CH0_DQ50
DDR4_DIMM_CH0_DQ61
DDR4_DIMM_CH0_DQ41
DDR4_DIMM_CH0_DQ42DDR4_DIMM_CH0_DQ43
DDR4_DIMM_CH0_DQ56
DDR4_DIMM_CH0_DQ49
DDR4_DIMM_CH0_DQ46DDR4_DIMM_CH0_DQ47
DDR4_DIMM_CH0_DQ48
DDR4_DIMM_CH0_DQS_N6
DDR4_DIMM_CH0_DQ57
DDR4_DIMM_CH0_DQ62
DDR4_DIMM_CH0_DQ52DDR4_DIMM_CH0_DQ53
DDR4_DIMM_CH0_DQ54
DDR4_DIMM_CH0_SA2
DDR4_DIMM_CH0_SA0
DDR4_DIMM_CH0_DQ58DDR4_DIMM_CH0_DQ59
DDR4_DIMM_CH0_DQ60
DDR4_DIMM_CH0_DQS_N2DDR4_DIMM_CH0_DQS_P2
DDR4_DIMM_CH0_DQS_N0DDR4_DIMM_CH0_DQS_P0
DDR4_DIMM_CH0_DQS_N5DDR4_DIMM_CH0_DQS_P5
DDR4_DIMM_CH0_DQS_N1DDR4_DIMM_CH0_DQS_P1
DDR4_DIMM_CH0_DQS_N3DDR4_DIMM_CH0_DQS_P3
DDR4_DIMM_CH0_DQS_P4DDR4_DIMM_CH0_DQS_N4
DDR4_DIMM_CH0_DQS_N7DDR4_DIMM_CH0_DQS_P7
DDR4_DIMM_CH0_DQS_P10
DDR4_DIMM_CH0_DQS_P11
DDR4_DIMM_CH0_SA1
DDR4_DIMM_CH0_DQS_P13
DDR4_DIMM_CH0_DQS_P14
DDR4_DIMM_CH0_DQS_P15
DDR4_DIMM_CH0_DQS_P16
DDR4_DIMM_CH0_DQS_P12
I2C_DDR4T_0_2V5_SCL
I2C_DDR4T_0_2V5_SDA
DDR4_DIMM_CH0_DQS_P17
DDR4_DIMM_CH0_DQ64DDR4_DIMM_CH0_DQ65
DDR4_DIMM_CH0_DQ66DDR4_DIMM_CH0_DQ67
DDR4_DIMM_CH0_DQ68DDR4_CH0_EVENT_NI2C_DDR4T_0_2V5_SCL
DDR4_DIMM_CH0_A6
DDR4_DIMM_CH0_A7
DDR4_DIMM_CH0_DQ69
DDR4_DIMM_CH0_DQ70DDR4_DIMM_CH0_DQ71
DDR4_DIMM_CH0_CS_N1
DDR4_DIMM_CH0_BA0
DDR4_DIMM_CH0_ODT0
DDR4_DIMM_CH0_ODT1
DDR4_DIMM_CH0_A13
DDR4_DIMM_CH0_A15
DDR4_DIMM_CH0_A16
DDR4_DIMM_CH0_BA1
DDR4_DIMM_CH0_CS_N2 DDR4_DIMM_CH0_CS_N3
DDR4_DIMM_CH0_A14
DDR4_DIMM_CH0_A17
I2C_DDR4T_0_2V5_SDA
DDR4_DIMM_CH0_SA2
I2C1_SDAI2C1_SCL
I2C_DDR4T_0_2V5_SDAI2C_DDR4T_0_2V5_SCL
I2C_DDR4T_0_S10_SDAI2C_DDR4T_0_S10_SCL
I2C_DDR4T_0_2V5_SDAI2C_DDR4T_0_2V5_SCL
DDR4_DIMM_CH0_RESET_N
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR4 DIMM CH1 IF
DDR4/DDRT DIMM CH1
Put caps on VDD pins which are close to DIMM A/C pins
S10_1V2OUT_CH11
S10_1V2OUT_CH11
2V5_DDR4_CH11
S10_1V2OUT_CH11
S10_1V2OUT_CH11
0V6_DDR4_VTT_CH11
2V5_DDR4_CH11
2V5_DDR4_CH11
12V_PCIE_IN
0V6_DDR4_VREF_CH11
2V5_DDR4_CH11
2V5_DDR4_CH110V6_DDR4_VTT_CH11
0V6_DDR4_VREF_CH11
0V6_DDR4_VTT_CH11
S10_1V2OUT_CH11
1.8V
S10_1V2OUT_CH11 S10_1V2OUT_CH11
0V6_DDR4_VTT_CH11
1.8V
2V5_DDR4_CH11
DDR4_DIMM_CH1_C27
DDR4_DIMM_CH1_EVENT_N8I2C_DDR4T_0_2V5_SDA42
DDR4_DIMM_CH1_DQ[71:0]7
DDR4_DIMM_CH1_A[17:0]7
DDR4_DIMM_CH1_DQS_P[17:0]7
DDR4_DIMM_CH1_CKE[1:0]7
DDR4_DIMM_CH1_CK_P[1:0]7
DDR4_DIMM_CH1_DQS_N[17:0]7
DDR4_DIMM_CH1_ODT[1:0]7
DDR4_DIMM_CH1_RESET_N7
DDR4_DIMM_CH1_CK_N[1:0]7
DDR4_DIMM_CH1_CS_N[3:0]7
DDR4_DIMM_CH1_BG[1:0]7
DDR4_DIMM_CH1_BA[1:0]7
DDR4_DIMM_CH1_ACT_N7
I2C_DDR4T_0_2V5_SCL42
DDR4_DIMM_CH1_PAR7DDR4_DIMM_CH1_ALERT_N7
DDR4_DIMM_CH1_SAVE_N8
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
43 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
43 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
43 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R6226 0
C2923 0.1uF
R6233 DNI
R6236 0
C2918
10nF
R6230 0
R6232 10.0K
C2916
10nF
C2939
10nF
C2936100uF120610VX5R
C2938
0.1uF
C2922 0.1uF
C2913
0.1uF
C2926
10uF
R6231 0
C2933 10nF
C2921
1uF
R6228 10.0K
J74B
DDR4x72x288
EVENT_n78
A079
Vdd80
BA081
RAS_n/A1682
Vdd83
S0_n84
Vdd85
Vdd88
Vdd90
Vdd92
Vss94
Vss98
Vss101
Vss103
Vss105
Vss107
Vss109
CAS_n/A1586
ODT087
S1_n89
ODT191
S2_n/C093
DQ3695
DQ3297 Vss96
DQS13_t/DM4_n/DBI4_n99
DQS13_c100
DQ38102
DQ34104
DQ44106
DQ40108
DQS14_t/DM5_n/DBI5_n110
DQS14_c111
Vss112
Vss114
Vss116
Vss118
Vss120
Vss123
Vss125
Vss127
Vss129
Vss131
Vss134
Vss136
Vss138
Vpp142
Vpp143
RFU1144
DQ46113
DQ42115
DQ52117
DQ48119
DQS15_t/DM6_n/DBI6_n121
DQS15_c122
DQ54124
DQ50126
DQ60128
DQ56130
DQS16_t/DM7_n/DBI7_n132
DQS16_c133
DQ62135
DQ58137
SA0139
SA1140
SCL141
PARITY222
Vdd223
BA1224
A10/AP225
Vdd226
Vdd229
Vdd231
Vdd233
Vdd236
Vss239
Vss241
Vss243
Vss246
Vss248
Vss250
Vss252
Vss254
RFU3227
WE_n/A14228
SAVE_n/NC230
A13232
A17/NC234
C2/NC235
S3_n/C1237
SA2/RFU238
DQ37240
DQ33242
DQS4_c244
DQS4_t245
DQ39247
DQ35249
DQ45251
DQ41253
Vss257
Vss259
Vss261
Vss263
Vss265
DQS6_t267
Vss270
Vss272
Vss274
Vss276
Vss279
Vss281
Vss283
Vpp286
Vpp287
Vpp288
DQS5_c255
DQS5_t256
DQ47258
DQ43260
DQ53262
DQ49264
DQS6_c266
Vss268
DQ55269
DQ51271
DQ61273
DQ57275
DQS7_c277
DQS7_t278
DQ63280
DQ59282
Vddspd284
SDA285
C2935 0.1uF
C2917
0.1uF
C2915
0.1uF
C2907
0.1uF
C2924100uF120610VX5R
U10
MAX3378EETD+T
VL10
IO VL11
IO VL22
IO VL35
IO VL46
GND7
VCC14
IO VCC113
IO VCC212
IO VCC39
IO VCC48
TS3
NC14
NC211
EP15
C2927
10uF
C2930
10nF
C2929
0.1uF
C2932 0.1uF
C2909
0.1uF
R6227 10.0K,DNI
C2906
0.1uF
C2940 0.1uF
R6229 0
C2928
0.1uF
C2905
1uF
C2925100uF120610VX5R
C2912
10nF
C2919
0.1uF
C2908
10nF
C2937
10uF
C2931
10nF
R6225 0
C2911
0.1uF
C2910
10nF
C2934 0.1uF
J74A
DDR4x72x288
Vss2
DQ43
Vss4
DQ05
Vss6
DQS9_t/DM0_n/DBI0_n7
DQS9_c8
Vss9
DQ610
Vss11
Vss13
Vss15
Vss17
Vss20
Vss22
Vss24
Vss26
Vss28
Vss31
Vss33
Vss35
Vss37
DQ212
DQ1214
DQ816
DQ1421
DQ1023
DQ2025
DQ1627
DQ2232
DQ1834
DQ2836
DQS10_t/DM1_n/DBI1_n18
DQS10_c19
DQS11_t/DM2_n/DBI2_n29
DQS11_c30
DQ2438
DQ3043
DQ2645
Vss39
Vss42
DQS12_t/DM3_n/DBI3_n40
DQS12_c41
Vss44
Vss46
Vss48
Vss50
Vss53
Vss55
Vss57
Vdd59
Vdd61
CB4/NC47
CB0/NC49
DQS17_t/DM8_n/DBI8_n51
DQS17_c52
CB6/NC54
CB2/NC56
RESET_n58
Vdd64
Vdd67
Vdd70
Vdd73
CKE060
ACT_n62
BG063
A1265
A966
A868
A669
A371
A172
CK0_t74
CK0_c75
Vdd76
Vtt77
Vrefca146
Vss147
Vss149
Vss151
Vss154
Vss156
Vss158
Vss160
Vss162
Vss165
DQ5148
DQ1150
DQ7155
DQ3157
DQ13159
DQ9161
DQ15166
DQS0_c152
DQS0_t153
DQS1_c163
DQS1_t164
Vss167
Vss169
Vss171
Vss173
Vss176
Vss178
Vss180
DQ11168
DQ21170
DQ17172
DQS2_c174
DQS2_t175
DQ23177
DQ19179
DQ29181
Vss182
Vss184
Vss187
Vss189
Vss191
Vss193
Vss195
DQ25183
DQ31188
DQ27190
CB5/NC192
CB1/NC194
Vss198
Vss200
Vss202
Vdd204
Vdd206
Vdd209
Vdd212
Vdd215
Vdd217
CB7/NC199
CB3/NC201
CKE1203
RFU2205
BG1207
ALERT_n208
A11210
A7211
A5213
A4214
A2216
Vdd220
CK1_t218
CK1_c219
Vtt221
DQS3_c185
DQS3_t186
DQS8_c196
DQS8_t197
12V/NC1
12V/NC145
C2914
10nF
C2920
100uF
DDR4_DIMM_CH1_C2
DDR4_CH1_EVENT_N DDR4_DIMM_CH1_EVENT_NDDR4_DIMM_CH1_SAVE_NDDR4_CH1_SAVE_N
DDR4_DIMM_CH1_DQ63
DDR4_DIMM_CH1_A11
DDR4_DIMM_CH1_A10
DDR4_DIMM_CH1_DQS_N9
DDR4_DIMM_CH1_DQS_N12
DDR4_DIMM_CH1_DQS_N13
DDR4_DIMM_CH1_DQS_N14
DDR4_DIMM_CH1_DQS_N10
DDR4_DIMM_CH1_DQS_N11
DDR4_DIMM_CH1_DQS_N15
DDR4_DIMM_CH1_DQS_N16
DDR4_DIMM_CH1_DQS_N17
DDR4_CH1_SAVE_N
DDR4_DIMM_CH1_SA1DDR4_DIMM_CH1_SA0
DDR4_DIMM_CH1_DQS_P9
DDR4_DIMM_CH1_DQS_P8DDR4_DIMM_CH1_DQS_N8
DDR4_DIMM_CH1_CK_P1DDR4_DIMM_CH1_CK_N1
DDR4_DIMM_CH1_DQS_P6
DDR4_DIMM_CH1_DQ55
DDR4_DIMM_CH1_DQ51
DDR4_DIMM_CH1_CKE1
DDR4_DIMM_CH1_CS_N0
DDR4_CH1_EVENT_N
DDR4_CH1_SAVE_N
DDR4_DIMM_CH1_PAR
DDR4_DIMM_CH1_ALERT_N
DDR4_DIMM_CH1_ACT_N
DDR4_DIMM_CH1_CKE0
DDR4_DIMM_CH1_CK_P0DDR4_DIMM_CH1_CK_N0
DDR4_DIMM_CH1_A1 DDR4_DIMM_CH1_A2DDR4_DIMM_CH1_A3
DDR4_DIMM_CH1_BG1
DDR4_DIMM_CH1_RESET_N
DDR4_DIMM_CH1_A8
DDR4_DIMM_CH1_A9DDR4_DIMM_CH1_A12
DDR4_DIMM_CH1_A0
DDR4_DIMM_CH1_BG0
DDR4_DIMM_CH1_DQ1
DDR4_DIMM_CH1_DQ2DDR4_DIMM_CH1_DQ3
DDR4_DIMM_CH1_A4DDR4_DIMM_CH1_A5
DDR4_DIMM_CH1_DQ6DDR4_DIMM_CH1_DQ7
DDR4_DIMM_CH1_DQ8DDR4_DIMM_CH1_DQ9
DDR4_DIMM_CH1_DQ0
DDR4_DIMM_CH1_DQ12DDR4_DIMM_CH1_DQ13
DDR4_DIMM_CH1_DQ14
DDR4_DIMM_CH1_DQ4DDR4_DIMM_CH1_DQ5
DDR4_DIMM_CH1_DQ17
DDR4_DIMM_CH1_DQ18DDR4_DIMM_CH1_DQ19
DDR4_DIMM_CH1_DQ10DDR4_DIMM_CH1_DQ11
DDR4_DIMM_CH1_DQ22DDR4_DIMM_CH1_DQ23
DDR4_DIMM_CH1_DQ24
DDR4_DIMM_CH1_DQ15
DDR4_DIMM_CH1_DQ16
DDR4_DIMM_CH1_DQ27
DDR4_DIMM_CH1_DQ28DDR4_DIMM_CH1_DQ29
DDR4_DIMM_CH1_DQ20DDR4_DIMM_CH1_DQ21
DDR4_DIMM_CH1_DQ32DDR4_DIMM_CH1_DQ33
DDR4_DIMM_CH1_DQ34DDR4_DIMM_CH1_DQ35
DDR4_DIMM_CH1_DQ25
DDR4_DIMM_CH1_DQ26
DDR4_DIMM_CH1_DQ38DDR4_DIMM_CH1_DQ39
DDR4_DIMM_CH1_DQ40
DDR4_DIMM_CH1_DQ30DDR4_DIMM_CH1_DQ31
DDR4_DIMM_CH1_DQ44DDR4_DIMM_CH1_DQ45
DDR4_DIMM_CH1_DQ36DDR4_DIMM_CH1_DQ37
DDR4_DIMM_CH1_DQ50
DDR4_DIMM_CH1_DQ61
DDR4_DIMM_CH1_DQ41
DDR4_DIMM_CH1_DQ42DDR4_DIMM_CH1_DQ43
DDR4_DIMM_CH1_DQ56
DDR4_DIMM_CH1_DQ49
DDR4_DIMM_CH1_DQ46DDR4_DIMM_CH1_DQ47
DDR4_DIMM_CH1_DQ48
DDR4_DIMM_CH1_DQS_N6
DDR4_DIMM_CH1_DQ57
DDR4_DIMM_CH1_DQ62
DDR4_DIMM_CH1_DQ52DDR4_DIMM_CH1_DQ53
DDR4_DIMM_CH1_DQ54
DDR4_DIMM_CH1_SA2
DDR4_DIMM_CH1_SA0
DDR4_DIMM_CH1_DQ58DDR4_DIMM_CH1_DQ59
DDR4_DIMM_CH1_DQ60
DDR4_DIMM_CH1_DQS_N2DDR4_DIMM_CH1_DQS_P2
DDR4_DIMM_CH1_DQS_N0DDR4_DIMM_CH1_DQS_P0
DDR4_DIMM_CH1_DQS_N5DDR4_DIMM_CH1_DQS_P5
DDR4_DIMM_CH1_DQS_N1DDR4_DIMM_CH1_DQS_P1
DDR4_DIMM_CH1_DQS_N3DDR4_DIMM_CH1_DQS_P3
DDR4_DIMM_CH1_DQS_P4DDR4_DIMM_CH1_DQS_N4
DDR4_DIMM_CH1_DQS_N7DDR4_DIMM_CH1_DQS_P7
DDR4_DIMM_CH1_DQS_P10
DDR4_DIMM_CH1_DQS_P11
DDR4_DIMM_CH1_SA1
DDR4_DIMM_CH1_DQS_P13
DDR4_DIMM_CH1_DQS_P14
DDR4_DIMM_CH1_DQS_P15
DDR4_DIMM_CH1_DQS_P16
DDR4_DIMM_CH1_DQS_P12
I2C_DDR4T_0_2V5_SCL
DDR4_DIMM_CH1_DQS_P17
DDR4_DIMM_CH1_DQ64DDR4_DIMM_CH1_DQ65
DDR4_DIMM_CH1_DQ66DDR4_DIMM_CH1_DQ67
DDR4_DIMM_CH1_DQ68
DDR4_CH1_EVENT_N
DDR4_DIMM_CH1_A6
DDR4_DIMM_CH1_A7
DDR4_DIMM_CH1_DQ69
DDR4_DIMM_CH1_DQ70DDR4_DIMM_CH1_DQ71
DDR4_DIMM_CH1_CS_N1
DDR4_DIMM_CH1_BA0
DDR4_DIMM_CH1_ODT0
DDR4_DIMM_CH1_ODT1
DDR4_DIMM_CH1_A13
DDR4_DIMM_CH1_A15
DDR4_DIMM_CH1_A16
DDR4_DIMM_CH1_BA1
DDR4_DIMM_CH1_CS_N2 DDR4_DIMM_CH1_CS_N3
DDR4_DIMM_CH1_A14
DDR4_DIMM_CH1_A17
I2C_DDR4T_0_2V5_SDA
DDR4_DIMM_CH1_SA2
DDR4_DIMM_CH1_RESET_N
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.1V @3.1A
Power S10_VCCH_GXE
S10_VCCH_GXE_LOW S10_VCCH_GXE3.3V_REG_INST
3.3V_REG_INST
U184_AGND
U184_AGNDU184_AGND
U184_AGND
U184_AGND
VCCH_GXE_PG23
VCCH_GXE_EN23,53
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
44 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
44 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
44 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C6115nF
0402
C29447uF,DNI120616VX5R
R66840
0402
R6280 10.0K,DNIRCA15k
04
02
R76.81K
0402
R6281 2.2K0402
R6197
10
RA294k
04
02
C3121
22uF
0805
25V
X5R
C3120
22uF
0805
25V
X5R
C3119
22uF,DNI
0805
25V
X5R
CA10pF
04
02
C29247uF120616VX5R
R6198 0.002C29347uF120616VX5R
C55DNI
04
02
U184EN6382QI
EN6382-QFN56A
NC181NC172NC163NC154NC145NC136NC127NC118NC109
VO
UT
15
VO
UT
16
VO
UT
17
VO
UT
18
NC
41
9N
C3
20
NC
22
1N
C1
22
NC
(SW
)12
3P
GN
D2
4
PG
ND
27
PVIN36 PVIN35 PVIN34 PVIN33 PVIN32 PVIN31 PVIN30 PVIN29
NC
22
54
NC
23
53
NC
(SW
)25
2N
C(S
W)3
51
NC
(SW
)45
0N
C(S
W)5
49
PG
OO
D4
8V
SE
NS
E4
7S
S4
6F
RQ
45
AG
ND
44
AV
IN4
3
VFB42 ENABLE41 BGND40 VDDB39 NC2538 NC2437
PG
ND
28
NC910NC811NC712NC613NC514
NC
21
55
NC
20
56
PG
ND
25
PG
ND
(pa
d)
57
NC
19
60
PG
ND
26
RB348K
04
02
VCCH_GXE_PG
VCCH_GXE_EN
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Ra
Rvs
R1 Ca
Css
Cb
Rb
Power S10_VCCH_GXP, VCCCLK_GXP
Optional path for sourcing from VCCPT
Uninstall R6722 (0 ohm)Install R6723 (0-ohm)
S10_VCCH_GXP_LOW
3.3V_REG_INST
U186_AGND
U186_AGND
U186_AGND
U186_AGND
U186_AGND3.3V_REG_INST
S10_VCCH_GXP
S10_VCCCLK_GXP
S10_G2_1.8V
VCCH_GXP_EN23,53VCCH_GXP_PG23
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
45 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
45 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
45 69Thursday, May 30, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R6283 2.2K0402
R621778.7K
L58
0.1uH,0.32mohm,17A
C2892 27pF0402
R6211
0,DNI
L59
120 Ohm, 1A
R6210
4.42K
C2884
47UF
R6723 DNI
C2886
47UF
R57070
0402
C320547UF1206
U186EN63A0QI
EN63A0QI-11x10MM-76QFN
NC
11
NC
22
NC
33
NC
44
NC
55
NC
66
NC
77
NC
88
NC
99
NC
10
10
NC
11
11
NC
12
12
NC
13
13
NC
14
14
NC
15
15
NC
16
16
NC
17
17
NC
18
18
NC1919VOUT20VOUT21VOUT22VOUT23VOUT24VOUT25VOUT26VOUT27VOUT28NC2929NC(SW)3030NC(SW)3131PGND32PGND33PGND34PGND35PGND36PGND37PGND38
S_
IN5
6
BG
ND
55
VD
DB
54
NC
63
53
NC
62
52
PV
IN5
1
PV
IN5
0
PV
IN4
9
PV
IN4
8
PV
IN4
7
PV
IN4
6
PV
IN4
5
PV
IN4
4
PV
IN4
3
PV
IN4
2
PV
IN4
1
PV
IN4
0
PV
IN3
9
NC7676 NC7575 NC7474 NC7373 NC7272 NC(SW)7171 NC(SW)7070 EN_PB69 FQADJ68 NC6767 VSENSE66 SS65 EAOUT64 VFB63 M/S62 AGND61 AVIN60 ENABLE59 POK58 S_OUT57 PGND(PAD)
77
C288715nF0402
R6212 0
C3201
22uF
0805
R6722 0
R620710.0K
R6214 12K
R620415K,DNI04021%
C28830.22uF0402
C320247uF120616VX5R
C3203100uF120610VX5R
C2885
47UF
C3204
100UF1206
C2889
47UF
R6213 158K
C2890
47UF
R6208
0,DNI
R6282 10.0K,DNI
C2888
47UF
R6205
10.0K,DNI
VCCH_GXP_PGVCCH_GXP_EN
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Ra
Rb Rb=142.2/(VOUT-0.6)
2.5V
Power - S10_VCCCLK_GXE
S10_VCCCLK_GXES10_VCCCLK_GXE_LOW3.3V_REG_INST
U78_AGND
U78_AGND
U78_AGND
U78_AGND
U78_AGNDU78_AGND
VCCCLK_GXE_EN23,53
VCCCLK_GXE_PG23
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
46 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
46 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
46 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R624875k
U78EP53F8QI
NC(SW1)1
PG
ND
2P
GN
D3
AVIN24
VFB5
NC16
VOUT7
VOUT8
AG
ND
9
AVIN110
POK11
ENABLE12
PVIN13
PVIN14
NC(SW2)15
NC(SW3)16
R6246237K
R6278 2.2K0402
C2944
5pF
0402
R6243
10
C2945
22uF
0805
R57270
0402
C2942
10uF
0805C2946
22uF,DNI
0805
C51
1uF,DNI
C2941
10uF
0805
L60
120 Ohm, 1A
R6247
0,DNI
C2943
680pF
0603
C320647UF1206
C29471uF0402
VCCCLK_GXE_PG
VCCCLK_GXE_EN
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BLANK
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
47 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
47 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
47 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BLANK
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
48 69Friday, May 24, 2019
K53732-100-A
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
48 69Friday, May 24, 2019
K53732-100-A
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
48 69Friday, May 24, 2019
K53732-100-A
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Cboost
150W 2x4 ATX AUX INPUT POWER CONNECTOR
12V_AUX2 Hot Swap
Typ: 30A, 360W
VIN absmax = 16V
R_Iload
VIN = 10.8V / 12V / 13.2V
Absmax = 6VVih = 1.2VVil = 0.8V
ADDR = 41h
Tr = 18.8mS
ILoad = 5uA / A
FAULT to BMC
SMBA to BMC
Place close toMAX16550 VIN pin
When 16V, EN = 1.96VWhen 15V, EN = 1.84VWhen 14V, EN = 1.72VWhen 13V, EN = 1.59VWhen 12V, EN = 1.47VWhen 11V, EN = 1.35VWhen 10V, EN = 1.23V
Rocp
20.6A = 1.34745V
EN ABSMAX = 2.5V
VDD = 1.76V / 1.85V / 1.94V
12V_AUX_IN C_load ~ 1472uF
Viload = 1.35VAbsmax = 2.5V
Rdson = 1.9mOhm for MAX16550Rdson = 0.95mOhm for MAX16545BInternal FET Ploss Max = 668mW
12V_PCIE = 150W = 12V @ 12.5A
ENth = 0.95V / 1V / 1.05V
Power On Switch(For external power supply)
OFF
ON
12V_AUX2
AUX_VDD_1V85
12V_AUX2
12V_AUX2_IN
AUX_VDD_1V85
3.3V_REG_INST
12V_AUX2_IN
12V_AUX2
M10_3.3V
AUX2_HSC_MAX10_PG 23
AUX2_HSC_FAULT_N23
I2C1_SCL23,42,55,63,68
I2C1_SDA23,42,55,63,68
AUX2_HSC_ALERT_N23
MAX10_PS_ON23
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
49 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
49 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
49 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R6536 0, DNI
R653141.2K04021%
R653310.0K04021%
D54
5p0SMDJ12A
R6534 10.0K0402 1%
R6539 2.37K0402 1%
C31460.22uF040216VX5R
R664210.0K
C31470.1uF040225VX7R
R65438.2K04020.1%
C313722uF080525VX5R
U217
MAX16550AGPN+ QFN-18
SMB_CLK1
ILOAD2
SS3
VBST4
VOUT15
VOUT26VIN1
7
VIN28
GND9
EN/UVLO10
SMB_ALERTB11
FAULTB12
PWRGD13
ROCP14
SMB_DATA15
SMB_ID16
NC17
VDD18
R65325.76K04021%
R654110.0K04021%
SW31SW_SLIDE_DPDT
1
236
5
4
C313822uF080525VX5R
R6537 0
C313922uF080525VX5R
J42
PCIe 2x4 ATX
12V1
12V2
12V3
GND8
SENSE14
SENSE06 GND5
GND7
C314910nF040250VX7R
C31440.01uF040225VX7R
R654297.6K04021%
C31411uF040225VX5R
C314022uF080525VX5R
C315047nF040225VX7R
D55STPS30L30DJF-TR
C31420.1uF040225VX7R
R664310.0K
R6538 0
C31451.5uF120650VX6S
C31430.1uF040225VX7R
C3151 0.1uF0402 25V
X7R
AUX2_HSC_MAX10_PG
AUX2_HSC_EN
AUX2_HSC_BST
AUX2_HSC_ALERT_NAUX2_HSC_ROCP
AUX2_HSC_SMB_ID_R
AUX2_HSC_ILOAD
AUX2_HSC_SS
ATX_PS_ONMAX10_PS_ON
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power - S10 VCCPT & 1.8V
PMBus Address = 0X47
DefaultVout =1.8v
H = 6.6mmPlace on Top side
RemoteSense NearFPGA Powerballs
connect AGND toPGND through asingle via
Rtune = 1x Base
Cout = Base = 1000uF 1.8V@18A
5V0
S10_G2_1.8V
12V_PCIE_IN
GND_SIGNAL2
GND_SIGNAL2
GND_SIGNAL2
GND_SIGNAL2
GND_SIGNAL2
GND_SIGNAL2
GND_SIGNAL2GND_SIGNAL2
GND_SIGNAL2
S10_G2_1.8V_FLT
S10_G2_1.8V
VDD33_250
VDD33_250
VDD33_250
1.8V_EN23,53
EM_I2C_SDA62,63
EM_I2C_SCL62,63
1.8V_PG23
VDD33_250
VDD33_250
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
50 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
50 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
50 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C1897
100uF
C2689
1uF0201
R57210,DNI
C320047UF1206
R56276.81K
0402
C1915
22uF0805X5R
R56412.00K0402
U113
EM2130H
AGND70
NC6868
VSENP71VSENN72
VOUT79
VOUT3
VTRACK77
ADDR17
VOUT80
ADDR08
RTUNE5
VOUT2
VCCSEN78
RVSET4
SCL15 SDA14
PG
ND
32
VDD3316
VCC66
NC7676
DGND69
PWM9
VOUT81
VINSEN6
VOUT1
SMBALERT13 CONTROL12 PGOOD11 SYNC10
PG
ND
33
PG
ND
34
PG
ND
35
PG
ND
36
PG
ND
37
PG
ND
38
PG
ND
39
PG
ND
40
PG
ND
42
PG
ND
43
PG
ND
44
PG
ND
45
PG
ND
46
PG
ND
47
PG
ND
48
PG
ND
49
PG
ND
50
PG
ND
41
PGND22
PGND23
PGND24
PGND25
PGND26
PGND27
PGND28
PGND29
PGND30
PGND31
PGND60
PGND59
PGND58
PGND57
PGND56
PGND55
PGND54
PGND53
PGND52
PGND51
PVIN61PVIN62PVIN63PVIN64
PVCC65
NC6767
NC7575
NC7474
NC7373
PVIN17
PVIN18
PVIN19
PVIN20
PVIN21
VO
UT
10
0
VO
UT
99
VO
UT
98
VO
UT
97
VO
UT
96
VO
UT
95
VO
UT
94
VO
UT
93
VO
UT
92
VO
UT
91
VO
UT
90
VO
UT
89
VO
UT
88
VO
UT
87
VO
UT
86
VO
UT
85
VO
UT
84
VO
UT
83
VO
UT
82
PVIN_PAD103
PGND_PAD104
AGND_PAD102
VO
UT
_P
AD
10
1
C1913
22uF0805X5R
1.8V_PWRGD1
C1912
22uF0805X5R
C1903
100uF
C1914
22uF0805X5R
R564211k
0402
R56261.5K
0402
C1896
100uF
V70
RS
NS
1S
NS
2
R571
10,DNI
R5644
0
R56332.2K0402
R562010.0K,DNI
C1901
100uF
R56431K
R563610.0K
0402
C1902
100uF
C1918DNI
04
02
R5634DNI 0402
C1916
22uF0805X5R
C1907
100UF1206R5629
DNI
04
02
C1895
100uF
C1908DNI
04
02
C1900
100uF
R56402.00K0402
R56315.6K
0402
1%
U113_PWM1
C1899
100uF
R563010.0K
R56352.7K
0402
1%
C1909
2.2uF0603
V69
RS
NS
1S
NS
2
C191710uF
1206
C1910
100uF
73
43
-V_
low
-pro
file
FB206A, RDC 7mOhm
C1911
100uF
73
43
-V_
low
-pro
file
R56323.3k
0402
FB11742792780
0402
C774
1uF0201
C1904
100uF
R5639DNI 0402
C1898
100uF
ALERTB_1.8V
1.8V_SENSE_N
1.8V_SENSE_P
1.8V_PG
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.8V @3.0A
RACA
RB
RC
RB=(0.6V*RA)/(VOUT - 0.6V)
tRISE~1.3ms
Power S10_VCCIO_1V8
1.8V3.3V_REG_INST
3.3V_REG_INST
U188_AGND
U188_AGND
U188_AGND
U188_AGND
VCCIO_1V8_EN23,53VCCIO_1V8_PG23
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
51 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
51 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
51 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C290015pF040250VC0G/NPO
C29011uF0402
R6219 10
R6284 10.0K,DNIC290210nF
R6221
10.0K
R6285 2.2K0402
U188
EN6363QI
NC(SW0)1
NC(SW1)2
NC13
NC24
VOUT5
VOUT6
VOUT7
VOUT8
VOUT9
VOUT10
VOUT11
NC(SW2)12
PGND13
PGND14
PVIN15
PVIN16
PVIN17
NC318
NC419ENABLE
20
NC521
NC622
NC723
VFB24
SS25
AVIN26
AGND27
POK28
AGND29
NC(SW3)30
NC(SW4)31
NC(SW5)32
NC(SW6)33
NC(SW7)34
PGND35
C2899100uF,DNI120610VX5R
R57260
0402
C2896100uF120610VX5R
R6222124K04021%
C2897100uF120610VX5R
R6220249K04021%
C2898100uF,DNI120610VX5R
C2894
47UF
C2895
47UF
VCCIO_1V8_PGVCCIO_1V8_EN
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 Decoupling
Place near S10 VCCPT
S10_VCC S10_VCC
S10_VCC
S10_VCC
0p9V
S10_VCCRT_GXE
1V2_DDR4_CH00
1V2_DDR4_CH11
0p9V
S10_G2_1.8V
S10_G2_1.8V S10_G2_1.8V
S10_G2_1.8V
S10_VCCH_GXP
S10_VCCH_GXEVCCRTPLL_GXE S10_VCCCLK_GXE
S10_VCCCLK_GXP
1.8V
0V6_DDR4_VREF_CH000V6_DDR4_VREF_CH11
S10_VCCH_GXP
S10_VCCH_GXPS10_VCCH_GXP
S10_VCCRT_GXP S10_VCCRT_GXP
S10_VCCRT_GXPS10_VCCRT_GXP
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
52 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
52 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
52 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C2549
1uF0201
C2618
1uF0201
C81622uF0603
C542
330uF7343-V_LOW-PROFILE
C2663
1uF0201
C3056
1uF0201
C2718
1uF0201
C3075
1uF0201
C2555
1uF0201
C746
1uF0201
C2677
1uF0201
C2666
1uF0201
C3085
1uF0201
C1459
1uF
0201
C30461uF0201
C2794
1uF0201
C1666
4.7uFC0201
C573
220uF1206
C592
100uF
C2
01
2
C3066
1uF0201
C2623
1uF0201
C2683
1uF0201
C33110uF0603
C603
100uF
C2
01
2
C33610uF0603
C844
100uF
C2
01
2
C835
1uF0201
C2742
1uF0201
C833
1uF0201
C551
220uF1206
C30371uF0201
C566
220uF1206
C3061
1uF0201
C600
100uF
C2
01
2
C2621
1uF0201
C2698
1uF0201
C2511
1uF0201
C715
1uF0201
C755
22uF0603
C2810
1uF0201
C2807
1uF0201
C2638
1uF0201
C589
100uF
C2
01
2
C2478
1uF0201
C728
1uF0201
C2760
1uF0201
C30471uF0201
C2517
1uF0201
C2610
1uF0201
C30321uF0201
C556
220uF1206
C776
1uF0201
C30291uF0201
C2624
1uF0201
C3055
1uF0201
C2625
1uF0201
C2667
1uF0201
C2597
1uF0201
C2729
1uF0201
C675
100uF
C2
01
2
C2587
1uF0201
C797
22uF0603
C2581
1uF0201
C3065
1uF0201
C2600
1uF0201
C588
100uF
C2
01
2
C2631
1uF0201
C2409
4.7uF
0603
C2547
1uF0201
C594
100uF
C2
01
2
C843
100uF
C2
01
2
C30341uF0201
C2746
1uF0201
C817
1uF0201
C2598
1uF0201
C1555
4.7uFC0201
C553
220uF1206
C3070
1uF0201
C2635
1uF0201
C561
220uF1206
C2696
1uF0201
C32610uF06036.3VX6S
C2501
1uF0201
C730
100uF
C2
01
2
C2533
1uF0201
C2848
1uF0201
C543
330uF7343-V_LOW-PROFILE
C674
100uF
C2
01
2
C2747
1uF0201
C753
100uF
C2
01
2
C2607
1uF0201
C670
100uF
C2
01
2
C836
1uF0201
C766
1uF0201
C2494
1uF0201
C2717
1uF0201
C563
220uF1206
C791
1uF0201
C687
1uF0201
C30491uF0201
C2510
1uF0201
C2715
1uF0201
C32910uF06036.3VX6S
C2673
1uF0201
C2575
1uF0201
C2753
1uF0201
C30391uF0201
C2573
1uF0201
C750
1uF0201
C2840
1uF0201
C2754
1uF0201
C3093
1uF0201
C2589
1uF0201
C2486
1uF0201
C2614
1uF0201
C714
1uF0201
C1403
4.7uFC0201
C2778
1uF0201
C559
220uF1206
C2787
1uF0201
C30381uF0201
C1665
4.7uFC0201
C3097
1uF0201
C2672
1uF0201
C586
100uF
C2
01
2
C2482
1uF0201
C2556
1uF0201
C719
1uF0201
C30521uF0201
C3077
1uF0201
C2504
1uF0201
C2564
1uF0201
C796
22uF0603
C23981uF
0201
C550
220uF1206
C30411uF0201
C837
1uF0201
C2627
1uF0201
C2758
1uF0201
C62010uF0603
C2762
1uF0201
C2602
1uF0201
C2826
1uF0201
C2582
1uF0201
C2842
1uF0201
C717
1uF0201
C2686
1uF0201
C35210uF0603
C795
22uF0603
C1655
4.7uFC0201
C2521
1uF0201
C3080
1uF0201
C2613
1uF0201
C2594
1uF0201
C784
1uF0201
C721
1uF0201
C2512
1uF0201
C2790
1uF0201
C2728
1uF0201
C2727
1uF0201
C2813
1uF0201
C3108
1uF0201
C3106
1uF0201
C2792
1uF0201
C688
1uF0201
C834
1uF0201
C2745
1uF0201
C2538
1uF0201
C596
100uF
C2
01
2
C2764
1uF0201
C554
220uF1206
C546
220uF1206
C31110uF06036.3VX6S
C598
100uF
C2
01
2
C574
220uF1206
C3064
1uF0201
C2838
1uF0201
C2584
1uF0201
C732
100uF
C2
01
2
C597
100uF
C2
01
2
C2408
4.7uF
0603
C30481uF0201
C2750
1uF0201
C2604
1uF0201
C3089
1uF0201
C2391220uFC3528
C744
22uF0603
C30331uF0201
C2832
1uF0201
C1659
4.7uFC0201
C2723
1uF0201
C2518
1uF0201
C2644
1uF0201
C557
220uF1206
C2675
1uF0201
C3086
1uF0201
C30501uF0201
C1645
4.7uFC0201
C2523
1uF0201
C2519
1uF0201
C2572
1uF0201
C2531
1uF0201
C745
1uF0201
C2574
1uF0201
C2730
1uF0201
C2490
1uF0201
C2528
1uF0201
C2834
1uF0201
C727
1uF0201
C2847
1uF0201
C2407
4.7uF
0603
C686
1uF0201
C3058
1uF0201
C2829
1uF0201
C2726
1uF0201
C1463
1uF0201
C2734
1uF0201
C558
220uF1206
C764
1uF0201
C33310uF0603
C2648
1uF0201
C3082
1uF0201
C81022uF0603
C2496
1uF0201
C2595
1uF0201
C80822uF0603
C2859
1uF0201
C731
100uF
C2
01
2
C2390220uFC3528
C2558
1uF0201
C62810uF0603
C2536
1uF0201
C560
220uF1206
C82122uF0603
C1661
4.7uFC0201
C2682
1uF0201
C2640
1uF0201
C765
1uF0201
C32710uF06036.3VX6S
C2526
1uF0201
C2491
1uF0201
C3084
1uF0201
C32010uF06036.3VX6S
C2546
1uF0201
C2498
1uF0201
C819
1uF0201
C623
4.7uFC0201
C2553
1uF0201
C2570
1uF0201
C2664
1uF0201
C2513
1uF0201
C3072
1uF0201
C2783
1uF0201
C3068
1uF0201
C2649
1uF0201
C590
100uF
C2
01
2
C2692
1uF0201
C2846
1uF0201
C2522
1uF0201
C30441uF0201
C3074
1uF0201
C30271uF0201
C2827
1uF0201
C2716
1uF0201
C2577
1uF0201
C585
100uF
C2
01
2
C30311uF0201
C2668
1uF0201
C562
220uF1206
C33410uF0603
C81322uF0603
C2647
1uF0201
C3087
1uF0201
C2669
1uF0201
C3059
1uF0201
C35410uF0603
C2853
1uF0201
C2404
4.7uF
0603
C2483
1uF0201
C2550
1uF0201
C3069
1uF0201
C621
4.7uFC0201
C2858
1uF0201
C82222uF0603
C2741
1uF0201
C2497
1uF0201
C2641
1uF0201
C555
220uF1206
C30401uF0201
C1657
4.7uFC0201
C2795
1uF0201
C2583
1uF0201
C3095
1uF0201
C2603
1uF0201
C2565
1uF0201
C624
1uF0201
C2821
1uF0201
C726
1uF0201
C2552
1uF0201
C2476
1uF0201
C838
1uF0201
C752
100uF
C2
01
2
C2481
1uF0201
C2803
1uF0201
C2507
1uF0201
C30361uF0201
C3073
1uF0201
C552
220uF1206
C2694
1uF0201
C569
220uF1206
C2628
1uF0201
C545
220uF1206
C1660
4.7uFC0201
C767
1uF0201
C2588
1uF0201
C62510uF0603
C2485
1uF0201
C3081
1uF0201
C2620
1uF0201
C576
100uF
C2
01
2
C2782
1uF0201
C2733
1uF0201
C2606
1uF0201
C2786
1uF0201
C2862
1uF0201
C3078
1uF0201
C2502
1uF0201
C33010uF06036.3VX6S
C2854
1uF0201
C565
220uF1206
C30281uF0201
C1465
1uF0201
C2484
1uF0201
C2545
1uF0201
C2808
1uF0201
C2719
1uF0201
C757
1uF0201
C842
100uF
C2
01
2
C2495
1uF0201
C2811
1uF0201
C2580
1uF0201
C2779
1uF0201
C2720
1uF0201
C30301uF0201
C1658
4.7uFC0201
C2500
1uF0201
C2568
1uF0201
C540
330uF7343-V_LOW-PROFILE
C2541
1uF0201
C3071
1uF0201
C2520
1uF0201
C30261uF0201
C32110uF06036.3VX6S
C676
100uF
C2
01
2
C2586
1uF0201
C2752
1uF0201
C2802
1uF0201
C587
100uF
C2
01
2
C2560
1uF0201
C2693
1uF0201
C830
1uF0201
C3092
1uF0201
C748
22uF0603
C2527
1uF0201
C2406
4.7uF
0603
C1462
1uF0201
C30431uF0201
C2615
1uF0201
C3063
1uF0201
C1417
4.7uFC0201
C2643
1uF0201
C30421uF0201
C3088
1uF0201
C82022uF0603
C81522uF0603
C672
100uF
C2
01
2
C2636
1uF0201
C2860
1uF0201
C2633
1uF0201
C3062
1uF0201
C2508
1uF0201
C2855
1uF0201
C23951uF
0201
C2845
1uF0201
C2797
1uF0201
C3079
1uF0201
C2744
1uF0201
C2632
1uF0201
C30531uF0201
C2781
1uF0201
C33710uF0603
C740
1uF0201
C2516
1uF0201
C812
100uFC2012
C2515
1uF0201
C2612
1uF0201
C541
330uF7343-V_LOW-PROFILE
C722
1uF0201
C2557
1uF0201
C2530
1uF0201
C716
1uF0201
C2822
1uF0201
C30511uF0201
C2492
1uF0201
C578
100uF
C2
01
2
C773
1uF0201
C2535
1uF0201
C2601
1uF0201
C2634
1uF0201
C2691
1uF0201
C684
1uF0201
C571
220uF1206
C3096
1uF0201
C749
22uF0603
C2793
1uF0201
C751
100uF
C2
01
2
C2839
1uF0201
C1639
4.7uFC0201
C2678
1uF0201
C756
1uF0201
C1413
4.7uFC0201
C2712
1uF0201
C2645
1uF0201
C2756
1uF0201
C2857
1uF0201
C593
100uF
C2
01
2
C3100
1uF0201
C2724
1uF0201
C1458
1uF
0201
C601
100uF
C2
01
2
C2608
1uF0201
C33810uF0603
C3057
1uF0201
C2630
1uF0201
C547
220uF1206
C1656
4.7uFC0201
C2670
1uF0201
C32810uF06036.3VX6S
C2841
1uF0201
C2748
1uF0201
C2735
1uF0201
C34110uF0603
C599
100uF
C2
01
2
C685
1uF0201
C2534
1uF0201
C2542
1uF0201
C595
100uF
C2
01
2
C622
4.7uFC0201
C1638
4.7uFC0201
C2571
1uF0201
C3083
1uF0201
C544
330uF7343-V_LOW-PROFILE
C548
220uF1206
C575
100uF
C2
01
2
C2629
1uF0201
C24024.7uF
C0201
C806
100uF
C2
01
2
C2609
1uF0201
C2532
1uF0201
C2616
1uF0201
C567
220uF1206
C572
220uF1206
C2562
1uF0201
C747
22uF0603
C2405
4.7uF
0603
C1667
4.7uFC0201
C3091
1uF0201
C814
1uF0201
C30351uF0201
C798
22uF0603
C671
100uF
C2
01
2
C2593
1uF0201
C2543
1uF0201
C33510uF0603
C35310uF0603
C2599
1uF0201
C2763
1uF0201
C3067
1uF0201
C577
100uF
C2
01
2
C2662
1uF0201
C1419
4.7uFC0201
C2856
1uF0201
C62910uF0603
C3101
1uF0201
C2837
1uF0201
C32210uF06036.3VX6S
C2503
1uF0201
C2759
1uF0201
C754
22uF0603
C2861
1uF0201
C2711
1uF0201
C564
220uF1206
C818
100uFC2012
C718
1uF0201
C2529
1uF0201
C602
100uF
C2
01
2
C2493
1uF0201
C3076
1uF0201
C2611
1uF0201
C3094
1uF0201
C1457
1uF
0201
C1640
4.7uFC0201
C1416
4.7uFC0201
C2567
1uF0201
C604
100uF
C2
01
2
C775
1uF0201
C2751
1uF0201
C2499
1uF0201
C81122uF0603
C2757
1uF0201
C841
100uF
C2
01
2
C805
100uF
C2
01
2
C720
1uF0201
C2539
1uF0201
C80422uF0603
C2685
1uF0201
C570
220uF1206
C568
220uF1206
C2563
1uF0201
C33210uF0603
C673
100uF
C2
01
2
C2713
1uF0201
C1464
1uF0201
C2591
1uF0201
C1552
4.7uFC0201
C2765
1uF0201
C871
100uF
C2
01
2
C3054
1uF0201
C2755
1uF0201
C2831
1uF0201
C579
100uF
C2
01
2
C2684
1uF0201
C2851
1uF0201
C549
220uF1206
C30451uF0201
C591
100uF
C2
01
2
C2605
1uF0201
C3107
1uF0201
C733
10uF0402
C2830
1uF0201
C2852
1uF0201
C2639
1uF0201
C2681
1uF0201
C3090
1uF0201
C739
1uF0201
C2524
1uF0201
C2559
1uF0201
C626
1uF0201
C2843
1uF0201
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Fast Power-Down Discharge
H = 0.8mmPlace on bottom side
H = 0.8mmPlace on bottom side
H = 0.8mmPlace on bottom side
H = 0.8mmPlace on bottom side
H = 0.8mmPlace on bottom side
H = 0.8mmPlace on bottom side
H = 0.8mmPlace on bottom side
H = 0.8mmPlace on bottom side
H = 0.8mmPlace on bottom side
H = 0.8mmPlace on bottom side
H = 0.8mmPlace on bottom side
H = 0.8mmPlace on bottom side
H = 0.8mmPlace on bottom side
S10_VCC
S10_G2_1.8V0p9V 12V_PCIE_IN
12V_PCIE_IN 12V_PCIE_IN
12V_PCIE_IN
S10_VCCH_GXP_LOW S10_1V2OUT_CH11
12V_PCIE_IN
12V_PCIE_IN
S10_VCCH_GXE_LOW
S10_VCCCLK_GXE_LOW
12V_PCIE_IN
1.8V
12V_PCIE_IN
12V_PCIE_IN
3.3V_REG
12V_PCIE_IN
2V5_DDR4_CH00
12V_PCIE_IN
S10_1V2OUT_CH00
12V_PCIE_IN
2V5_DDR4_CH11
12V_PCIE_IN
VCCRTPLL_GXE
VCCERAM_EN23,62 1.8V_EN23,50
DDR4_CH11_EN23,66
VCC_EN23,58
VCCH_GXP_EN23,45
VCCH_GXE_EN23,44
VCCCLK_GXE_EN23,46
VCCIO_1V8_EN23,51
3.3V_REG_EN23,63
2.5V_DDR4_CH00_EN23,65
DDR4_CH00_EN23,672.5V_DDR4_CH11_EN23,65
VCCRT_GXE_EN23
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
53 69Wednesday, June 05, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
53 69Wednesday, June 05, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
53 69Wednesday, June 05, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R581 10
Q55FDMC8878
5
123
4
R547
4.70K
R630 10.0K
Q52
FDV305N
Q10
FDMC8878
5
123
4
Q63FDMC8878
5
123
4
R635 10.0K
R641
4.70K
R624
0.1
R631
4.70K
R6364.70K
R593 10.0K
R586 10.0K, DNI
R603 10
R550 10
R644
0.1
R5854.70K, DNI
R602 10.0K
R594 10
R577
4.70K, DNI
Q60
FDV305N
R604
4.70K, DNI
R558 10
Q25
FDV305N
R620
4.70K
R559 10.0K R625 10.0KQ37
FDV305N
Q58
FDV305N
R5794.70K Q23
FDMC8878
5
123
4Q12
FDV305N
Q53FDMC8878
5
123
4
R645 10.0K
Q56
FDV305N
R5954.70K, DNI
R637
4.70K, DNI
Q11
FDV305N
R626
4.70K
R588 10.0K
R621
0.1
R627 10
R5844.70K, DNI
Q9
FDMC8878
5
123
4
R553
4.70K, DNI
R6324.70K, DNI
R638 10
R544
0.1
R6464.70K
Q50
FDV305N
Q39FDMC8878
5
123
4
R633 10
R628
4.70K, DNI
Q61FDMC8878
5
123
4
R600 10
Q22FDMC8878
5
123
4
R560
4.70K, DNI
R580 10 , DNI
R605 10.0K
Q54
FDV305N
R575
0.1
Q59FDMC8878
5
123
4
R582 10
Q62
FDV305N
R601
4.70K, DNI
R639
0.1
R6150.1
R555
4.70K
Q57FDMC8878
5
123
4
R556 10.0K
Q24
FDV305N, DNI
R6340.1
R578
4.70K
R557
0.1
R606 10
R6290.1
R622
4.70K
R5834.70K, DNI
Q51FDMC8878
5
123
4
R607
4.70K, DNI
R587 10.0K
R6424.70K, DNI
R5760.1
R640 10.0K
R619
0.1
Q21FDMC8878, DNI
5
123
4
Q26
FDV305N
R643 10
R6144.70K
R5740.1, DNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCIE_12V to AUX_12V Power Bridge
Cboost
5V0
5V0
12V_AUX2_IN 12V_PCIE_IN
5V0
5V0
PCIE_HSC_EN55
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
54 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
54 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
54 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C1700 0.1uF0402 25V X7R
A&B=Y
U6
SN74LVC1G08_6PIN
A1
B2
GND3
VCC6
NC5
Y4
D47STPS30L30DJF-TR
R5503 0
C17031.5uF120650VX6S
C57DNI0402
R5490100K0402
1%
C16980.22uF040216VX5R
R5486 10.0K
0402
1%
R5499100K0402
1%
1
2
3
Q38SI2302CDS-T1-GE3
SOT23
C16990.1uF040225VX7R
R5500 0
R5493 2400402 1%
U93
NCP45560IMNTWG-H
VIN1
EN2
VCC3
GND4
BLEED7
SR5
VOUT9
VOUT8
VIN13
PG6
VOUT10VOUT11VOUT12
R6201 0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Rdson = 1.9mOhm for MAX16550Rdson = 0.95mOhm for MAX16545BInternal FET Ploss Max = 668mW
VIN = 10.8V / 12V / 13.2V
Cboost
ADDR = 42h
Tr = 18.8mS
ILoad = 5uA / A
FAULT to BMC
SMBA to BMC
Place close toMAX16550 VIN pin
Rocp
EN ABSMAX = 2.5V
VDD = 1.76V / 1.85V / 1.94V
Viload = 1.35VAbsmax = 2.5V
12V_PCIE = 75W = 12V @ 6.25A
ENth = 0.95V / 1V / 1.05V
R_Iload
20.6A = 1.34745V
H = 1.1mmPlace on bottom side
12V_PCIE_IN C_load ~ 5712uFH = 1.0mmPlace on bottom side
Ideal Diode
VIN absmax = 16V
Absmax = 6VVih = 1.2VVil = 0.8V
12V_PCIE Hotswap
Typ: 30A, 360W
PCIE_VDD_1V85
12V_PCIE_SLOT
12V_PCIE_HSC 12V_PCIE_IN
PCIE_VDD_1V85
3.3V_REG_INST
12V_PCIE_HSC
12V_PCIE_SLOT
3.3V_REG_INST
PCIE_HSC_FAULT_N23
PCIE_HSC_ALERT_N23
I2C1_SDA23,42,49,63,68
I2C1_SCL23,42,49,63,68
PCIE_HSC_MAX10_PG 23
PCIE_HSC_EN54
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
55 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
55 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
55 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C173510nF040250VX7R
R551210.0K,DNI04021%
C17291uF040225VX5R
R334 0
U97
LTC4357
OUT1
GND4VDD6
NC5
GATE3
IN2
EP_GND7
C1737 0.1uF0402 25V
X7R
R550610.0K04021%
C1739100uF2917_4p3mm25VTant Poly
C17300.1uF040225VX7R
C174022uF080525VX5R
C17320.01uF040225VX7R
C173647nF040225VX7R
R551097.6K04021%
R55118.2K04020.1%
C174222uF080525VX5R
C1738100uF2917_4p3mm25VTant Poly
C17330.22uF040216VX5R
D515p0SMDJ12A
R550910.0K04021%
C174122uF080525VX5R
C17310.1uF040225VX7R
C174322uF080525VX5R
R550441.2K04021%
R88 0, DNI
D50STPS30L30DJF-TR
R5507 10.0K0402 1%
R339 0
R5508 3.16K0402 1%
R55055.76K04021%
U96
MAX16550AGPN+ QFN-18
SMB_CLK1
ILOAD2
SS3
VBST4
VOUT15
VOUT26VIN1
7
VIN28
GND9
EN/UVLO10
SMB_ALERTB11
FAULTB12
PWRGD13
ROCP14
SMB_DATA15
SMB_ID16
NC17
VDD18
C17340.1uF040225VX7R
U95FDMC2514SDC
5
123
4
PCIE_HSC_EN
PCIE_HSC_BST
PCIE_HSC_ROCPPCIE_HSC_SMB_ID_R
PCIE_HSC_ILOAD
PCIE_HSC_SS
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power - Max10
*VOUT CALCULATION
*VOUTL1/2 CALCULATION
Ra
Rb
Rb=142.2/(VOUT-0.6)
1.2V@1A
U116_AGND
MAX10_VCC_1.2V
MAX10_VCCIO_2.5V
MAX10_VCCIO_1.8V
U116_AGND
U116_AGND
U116_AGND
U116_AGND
U116_AGND
U79_AGND U79_AGND
U79_AGND
U79_AGNDU79_AGND
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
56 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
56 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
56 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R569061.9K
0402
R6139118K0402
CA1 33pF0402
R5
68
74
1.2
K0402
C376
22uF0805X5R25V
C56
1uF
C24175pF0402
U79EP53F8QI
NC(SW1)1
PG
ND
2P
GN
D3
AVIN24
VFB5
NC16
VOUT7
VOUT8
AG
ND
9
AVIN110
POK11
ENABLE12
PVIN13
PVIN14
NC(SW2)15
NC(SW3)16
C241322uF0805X5R
C195710nF0402
EZ6303QI
U116
SW
(NC
1)
1S
W(N
C2
)2
SW
(NC
3)
3P
GN
D4
PG
ND
5
VO
UT
42
VO
UT
6V
OU
T7
VO
UT
8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
PGND14
PGND15
PVIN16
AVIN17
AGND18
VFB19
SS20
PGND43
VF
BL
12
1
VO
UT
L1
22
VIN
L1
23
PG
ND
24
PGND41
VIN
L2
25
VO
UT
L2
26
VF
BL
22
7
EN
L2
28
POKL229POKL130ENL131POK32BTMP33PGTE34EN35SW(NC8)36SW(NC7)37SW(NC6)38SW(NC5)39SW(NC4)40
R6136
100402
R5
68
41
0.0
K
C1892DNI0402
C375
22uF0805X5R25V
C374
22uF0805X5R25V
R56910
0402
RC1 6.65K0402
R4861K0402
1%
C196210uF
0805
R5
68
81
10
k0
40
2
RB1169k0402
C51310uF0805X5R25V
C195422uF0805X5R
C2416680pF0603
C24201uF0402
C1788DNI0402
C241510uF0805X5R25V
C241922uF,DNI0805X5R
C241822uF0805X5R
C195322uF0805X5R
R6138
237k0402
C377
22uF0805X5R25V
R5
68
51
0.0
K
R5689110k
04
02
R5
68
31
0.0
K
R56920
0402
C1789DNI0402
C196110uF
0805 RA1 169k
0402
R6137
100K
C196027pF
0402
C195927pF
0402
C195815nF
0402
R5686 100402
C241422uF0805X5R
AVIN
VFB
L1FBL2FBENL2
ENL1
EN
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power - 5V
R2
R1 = R1a + R1b
Tss = 2mS
R4
Cboot
C2
Vout = 0.6 x ( 1 + R1/R4 )
Rt
5V LDO
R3
PVIN max = 14V
C1
EN(th) rising = 2.7VEN(th) falling = 2.3VABSmax = AVin+0.3V
Freq = 503.67 KhzRt = 48000/Freq
R1b
C3H=3mm
R1a
AGND PGND
PLACE Output decoupling capsclose to the device. ConnectAGND and PGND at the point of cap GND connection.
5.0V@1A5V0_AGND
12V_AUX2_IN
5V0_AGND 5V0_AGND
5V0
5V0_AGND
5V0_AGND
5V0_AGND5V0_AGND
3.3V_REG_INST
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
57 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
57 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
C
57 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R5523 100402 1%
R553124.9K04020.1%
ER2120QI
U99
POK1
AGND2
EN3
SYNC4
M/S5
FSW6
CO
MP
7
FB
8
SS
9
PG
ND
10
PG
ND
11
PG
ND
12
PVIN18
SW17
SW16
SW15
SW14
PGND13
AV
IN24
AV
INO
23
BO
OT
22
PV
IN21
PV
IN20
PV
IN19
EP
AD
25
R5522100K04021%
C1758
4.7uF0603_h0p5510VX6S
C17590.1uF040225VX7R
C1761470pF0402X7R25V
C17600.1uF040225VX7R
C1756
22uF
0805
25V
X5R
L30
4.7uH
NRS5030T4R7MMGJV
C1757
1uF
0402
25V
X5R
C1765
22uF, DNI
0805
25V
X5R
C1893DNI0402
C1753
22uF, DNI
0805
25V
X5R
C17660.1uF0402
R55260, DNI
5%0402
R5527 10.0K,DNI0402 1%
R5530 95.3K0402 1%
R57310
0402
C1762
22uF
0805
25V
X5R
C176715pF040250VC0G/NPO
C1763
22uF
0805
25V
X5R
R55353.83K04020.1%
R553328K
04021%
C1755
22uF
0805
25V
X5R
C1754
22uF, DNI
0805
25V
X5R
C1768820pF040250V
C0G/NPO
R55321.4K04021%
C1764
22uF, DNI
0805
25V
X5R
R55343.83K04020.1%
5V0_AVINO
5V0_AVIN
5V0_PG
5V0_FSW
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
91mA
I2C ADDR = 60H
Placeclose toISL68137in layout
Place closeto FPGA
Remote sense to FPGADiff pair routing
1.2V LDO output
Notes:1) Route TMON as daisy-chain at 5x ISL99227and single trace brought to ISL68137.
2) Route FAULT# as daisy-chain at 5xISL99227 and single trace brought toISL68137.
ABSMAX = 3.6VVIHMAX = 2.55V
Note: ISL68137 initializationtakes 40mS max.
AVS_CLK = 50Mhz
Power - VCCcore part1
For PMBus dongle connection
3.3V_REG_INST
1V2_VCCS
S10_VCC
12V_AUX2_IN
1V2_VCCS
3.3V_REG_INST3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
TMON 59,60,61
TWARN_0V89_FPGA23
PWM260PWM360PWM461
I2C_LVC3_SCL6I2C_LVC3_SDA6
VCC_EN23,53
S10_VCC_SENSE19
S10_VSS_SENSE19
ISENSE1 59
REFIN1 59
ISENSE0 59
REFIN0 59
ISENSE2 60
REFIN2 60
ISENSE3 60
REFIN3 60
ISENSE4 61
REFIN4 61
REFIN 59,60,61
PWM059PWM159
0V89_FPGA_FAULT59,60,61
AVS_MDA23AVS_CLK23
AVS_SDA23
VCC_PG23
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
58 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
58 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
58 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R5593100
1%0402
R5569 1001%0402
R5582 1K0402 1%
R5578 10.0K0402 1%
R557310.0K04021%
C18023300pF
040250VX7R
R5583 00402 5%
R5587 1001%0402
R5591004025%
R71 0C17944.7uF04026.3VX5R
R556540.2K04021%
C1799470pF
0402X7R25V
R84 0
R5592004025%
C17932.2uF
060310VX5R
R85 0
R5585 1001%0402
R5576 33.21%0402
J97
TSW-103-08-G-S
11
22
33
U104
ISL68137IRAZ-T
AVS_SDA9 AVS_VDDIO
11
DNC112
DNC246
DNC347
DNC448
PG016
PG117
TWARN15
EN013
EN114
CONFIG21
SA41
PWM01
PWM12
PWM23
PWM34
PWM45
PWM56
PWM67
SCL18
SDA19
SALRT20
VINSEN22
TMON044
TMON145
VCC42
VCCS43
CS038
CSRTN037
CS136
CSRTN135
CS234
CSRTN233
CS332
CSRTN331
CS430
CSRTN429
CS528
CSRTN527
CS626
CSRTN625
VSEN040
RGND039
VSEN123
RGND124
AVS_CLK8 AVS_MDA
10
MPAD49
R5586 00402 5%
R5584 6.81K0402 1%
R5568 10.0K0402 1%
C17954.7uF04026.3VX5R
R5580 1001%0402
C1800470pF
0402X7R25V
C17964.7uF04026.3VX5R
C1797470pF
0402X7R25V
R557110.0K04021%
R559010004021%
R5574 1001%0402
R55792.2K0402
C1791 470pF0402
X7R25V
C18031uF040225VX5R
C1790 10nF0402 50V X7R
C1792470pF
0402X7R25V
R557210.0K04021%
C1798470pF
0402X7R25V
R55750, DNI
5%0402
R5589100
1%0402
VSEN_PVSEN_N
REFIN0
ISENSE1_R
ISENSE2_R
ISENSE3_R
ISENSE4_R
EN4_FPGA_CORE
ISL68137_ADDR
ISL68137_CFG
ISENSE0_R
REFIN1
REFIN2 REFIN2
REFIN3
REFIN4
ISENSE1_R
REFIN1
ISENSE0_R
REFIN0
ISENSE2_R
REFIN3
ISENSE4_R
REFIN4
VINSEN_CORE
ISENSE3_R
VCC_PG
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
~20mA/phase
~20mA/phase
Place on top
Place on top
Place closeto ISL99227in layout
PHASE 0 & 1
H=4.96mm
H=4.96mm
Route ISENSE0/REFIN0 as diff pair
Place closeto ISL99227in layout
Route ISENSE1/REFIN1 as diff pair
Power - VCCcore part2
0.8 -0.94V @150A
0.8 -0.94V @150A
5V0
5V0
12V_AUX2_IN
S10_VCC
12V_AUX2_IN
S10_VCC
S10_VCC
S10_VCC
TMON58,59,60,61
0V89_FPGA_FAULT58,60,61
REFIN058
PWM058
ISENSE058
REFIN158
TMON58,59,60,61
PWM158
ISENSE158
REFIN58,60,61
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
59 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
59 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
59 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C183622uF121025VX7R
C1832100uF120610VX5R
C1810330uF14112.5V
Tant Poly
C1813100uF120610VX5R
L32 100nH
FP0805R1-R10-R
1 2
C183422uF121025VX7R
C1825100uF120610VX5R
C1838 0.1uF0402 25V X7R
C1821100uF120610VX5R
L31 100nH
FP0805R1-R10-R
1 2
U105
ISL99227FRZ-TS2568
QFN-33
LGCTRL1
VCC2
PVCC3
PGND4
GND16
GND27
GND38
GND417
GND518
GND619
GND720
AGND29
GND833
GNDPAD35
NC5
SW19
SW210
SW311
SW412
SW513
SW614
SW715
SW816
VIN121
VIN222
VIN323
VIN427
VIN534
PHASE24
BOOT25
FAULT#26
PWM28
REFIN30
IMON31
TMON32
C1818100uF120610VX5R
R5595 00402 5%
C1811 0.1uF0402 25V X7R
C1828100uF120610VX5R
C1820100uF120610VX5R
C1826100uF120610VX5R
R5596 00402 5%
C1812100uF120610VX5R
C1829100uF120610VX5R
C180822uF, DNI121025VX7R
C1805 0.1uF0402 25V
X7RC1809
1uF060325VX7R
C183722uF, DNI121025VX7R
C1823100uF120610VX5R
C187322uF12066.3VX7R
C1804 4.7uF
0603_h0p5510VX6S
C1816100uF120610VX5R
C1830100uF120610VX5R
C187222uF12066.3VX7R
C180622uF121025VX7R
C180722uF121025VX7R
C1814100uF120610VX5R
C18351uF060325VX7R
C1815100uF120610VX5R
C1817100uF120610VX5R
C1822100uF120610VX5R
C1824100uF120610VX5R
C1833 0.1uF0402 25V X7R
R55941K0603_h0p551%
C1819100uF120610VX5R
U106
ISL99227FRZ-TS2568
QFN-33
LGCTRL1
VCC2
PVCC3
PGND4
GND16
GND27
GND38
GND417
GND518
GND619
GND720
AGND29
GND833
GNDPAD35
NC5
SW19
SW210
SW311
SW412
SW513
SW614
SW715
SW816
VIN121
VIN222
VIN323
VIN427
VIN534
PHASE24
BOOT25
FAULT#26
PWM28
REFIN30
IMON31
TMON32
C1827 4.7uF
0603_h0p5510VX6S
C1831100uF120610VX5R
SW0
PHASE0
BOOT0
SW1
PHASE1
BOOT1
REFIN
0V89_FPGA_FAULT
REFIN
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Place on top
~20mA/phase
Place on top
~20mA/phase
PHASE 2 & 3
H=4.96mm
H=4.96mm
Place closeto ISL99227in layout
Route ISENSE2/REFIN2 as diff pair
Route ISENSE3/REFIN3 as diff pair
Place closeto ISL99227in layout
Power - VCCcore part3
0.8 -0.94V @150A
0.8 -0.94V @150A
5V0
5V0
12V_AUX2_IN
12V_AUX2_IN
S10_VCC
S10_VCC
0V89_FPGA_FAULT58,59,61
REFIN258
TMON58,59,60,61
PWM258
ISENSE258
REFIN358
TMON58,59,60,61
PWM358
ISENSE358
REFIN58,59,61
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
60 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
60 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
60 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C184222uF, DNI121025VX7R
C1844 0.1uF0402 25V X7R
C18431uF060325VX7R
C184122uF121025VX7R
C184822uF121025VX7R
C1846 4.7uF
0603_h0p5510VX6S
C184722uF121025VX7R
R5597 00402 5%
C18501uF060325VX7R
C1839 4.7uF
0603_h0p5510VX6S
U108
ISL99227FRZ-TS2568
QFN-33
LGCTRL1
VCC2
PVCC3
PGND4
GND16
GND27
GND38
GND417
GND518
GND619
GND720
AGND29
GND833
GNDPAD35
NC5
SW19
SW210
SW311
SW412
SW513
SW614
SW715
SW816
VIN121
VIN222
VIN323
VIN427
VIN534
PHASE24
BOOT25
FAULT#26
PWM28
REFIN30
IMON31
TMON32
C187422uF12066.3VX7R
C184022uF121025VX7R
C188822uF12066.3VX7R
L33 100nH
FP0805R1-R10-R
1 2
C1851 0.1uF0402 25V X7R
U107
ISL99227FRZ-TS2568
QFN-33
LGCTRL1
VCC2
PVCC3
PGND4
GND16
GND27
GND38
GND417
GND518
GND619
GND720
AGND29
GND833
GNDPAD35
NC5
SW19
SW210
SW311
SW412
SW513
SW614
SW715
SW816
VIN121
VIN222
VIN323
VIN427
VIN534
PHASE24
BOOT25
FAULT#26
PWM28
REFIN30
IMON31
TMON32
R5598 00402 5%
L34 100nH
FP0805R1-R10-R
1 2
C1845 0.1uF0402 25V X7R
C184922uF, DNI121025VX7R
C1852 0.1uF0402 25V X7R
PHASE2
BOOT2
SW2
PHASE3
BOOT3
SW3
0V89_FPGA_FAULT
REFIN
REFIN
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
~20mA/phase
Place on top
PHASE 4
H=4.96mm
Place closeto ISL99227in layout
Route ISENSE4/REFIN4 as diff pair
Power - VCCcore part4
0.85@150A
5V0
12V_AUX2_IN
S10_VCC
0V89_FPGA_FAULT58,59,60
REFIN458
TMON58,59,60
PWM458
ISENSE458
REFIN58,59,60
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
61 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
61 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
61 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C185522uF121025VX7R
C185622uF, DNI121025VX7R
L35 100nH
FP0805R1-R10-R
1 2
U109
ISL99227FRZ-TS2568
QFN-33
LGCTRL1
VCC2
PVCC3
PGND4
GND16
GND27
GND38
GND417
GND518
GND619
GND720
AGND29
GND833
GNDPAD35
NC5
SW19
SW210
SW311
SW412
SW513
SW614
SW715
SW816
VIN121
VIN222
VIN323
VIN427
VIN534
PHASE24
BOOT25
FAULT#26
PWM28
REFIN30
IMON31
TMON32
C188922uF12066.3VX7R
C1854 0.1uF0402 25V X7R
C185822uF121025VX7R
C1859 0.1uF0402 25V X7R
C18571uF060325VX7R
C1853 4.7uF
0603_h0p5510VX6S
R5599 00402 5%
PHASE4
BOOT4
SW4
REFIN
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PMBus Address = 0X31h
VCCPLLDIG_SDM, VCCRTPLL_GXE, VCCFUSE_GXP
Power - VCCERAM, VCCRT_GXP, VCCRT_GXE
Cout = 2xBase = 4560uF
0.9V@60A
Rtune = 0 for 1x BaseRtune = 392 for 2x Base
RemoteSense NearFPGA Powerballs
DefaultVout =0.9v
High Current Paths
High Current Paths
0p9V
S10_FUSE_GXP
S10_VCCPLLDIG_SDM
12V_AUX2_IN
5V0
0p9V
S10_VCCRT_GXP
VCCRTPLL_GXE
0p9V
S10_VCCRT_GXE
VCCERAM_PG23
VDD33_U23062
VCCERAM_EN23,53
VDD33_U23062
EM_I2C_SDA50,63EM_I2C_SCL50,63
VDD33_U23062
VCCRT_GXP_SENSE_P33
VCCRT_GXP_SENSE_N33
VCCRT_GXE_SENSE_P33
VCCRT_GXE_SENSE_N33
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT BOARD
C
62 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT BOARD
C
62 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT BOARD
C
62 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C1883
22uF1206X5R
L37
120 Ohm, 1A
R56025.36K
0402
C1875
100UF1206
FB76A, RDC 7mOhm
C3114
22uF
0805
FB10742792780
0402
C1884
22uF1206X5R
C26747uF120616VX5R
R5604DNI0402
R561110.0K0402
C266470uF29172.5VAlum Poly
EM2260P01QI
U230
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
POK6
CTRL7
SALRT8
VDD339
VCC10
SDA11
SCL12
NC113NC214
PWM015
NC316NC417NC518
PVIN19
PVIN20
PVIN21
PVIN22
PVIN23
PVIN24
NC625
PG
ND
26
PG
ND
27
PG
ND
28
PG
ND
29
PG
ND
30
PG
ND
31
PG
ND
32
PG
ND
33
PG
ND
34
PG
ND
35
PGND36PGND37PGND38PGND39PGND40PGND41PGND42PGND43PGND44PGND45
PGND46
PGND47
PGND48
PGND49
PGND50
PGND51
PGND52
PGND53
PH054
NC755
PH156
PGND57
PGND58
PGND59
PGND60
PGND61
PGND62
PGND63
PGND64
PGND65
PGND66
PGND67
PGND68
PGND69
PGND70
PGND71
PGND72
PGND73
PGND74
PGND75
PGND76
PG
ND
77
PG
ND
78
PG
ND
79
PG
ND
80
PG
ND
81
PG
ND
82
PG
ND
83
PG
ND
84
NC885
PVIN86
PVIN87
PVIN88
PVIN89
PVIN90
PVIN91
NC992
NC1093
PWM194
NC1195NC1296
VSENP97VSENN98VTRACK99
ADDR0100 ADDR1101
RVSET102
RTUNE103
SYNC104
VOUT105VOUT106VOUT107VOUT108VOUT109VOUT110VOUT111VOUT112VOUT113VOUT114VOUT115VOUT116VOUT117VOUT118VOUT119VOUT120VOUT121VOUT122VOUT123VOUT124VOUT125VOUT126VOUT127VOUT128VOUT129VOUT130VOUT131VOUT132VOUT133VOUT134VOUT135
VO
UT
136
VO
UT
137
VO
UT
138
VO
UT
139
VO
UT
140
VO
UT
141
VO
UT
142
VO
UT
143
VO
UT
144
VO
UT
145
VO
UT
146
VO
UT
147
VO
UT
148
VO
UT
149
VO
UT
150
VO
UT
151
VO
UT
152
VO
UT
153
PGND154
PVIN155
PG
ND
156
R56310,DNI
C262100uF120610VX5R
U111_PH1
R6690 DNI
R6687 DNI
C1885
22uF1206X5R
R562
10,DNI
C71100uF120610VX5R
R5608DNI 0402
C79470uF29172.5VAlum Poly
C80100uF120610VX5R
R5616 0
R56054.70K0402
C268470uF29172.5VAlum Poly
C260100uF120610VX5R
R6688 0
L380.1uH,0.32mohm,17A
C317747UF1206
C259470uF29172.5VAlum Poly
C188610uF
1206
C1878
2.2uF0603
C3176100uF120610VX5R
C77100uF120610VX5R
R6685 0
L56
120 Ohm, 1A
C1936
100UF1206
C264470uF, DNI29172.5VAlum Poly
C3010
22uF
0805
C261100uF, DNI120610VX5R
R4921.8K
04021%
R5614DNI 0402
C1879
100uF
73
43-V
_lo
w-p
rofile
C1877DNI
04
02
R6689 DNI
C187647UF1206
C3011
22uF
0805
C265470uF, DNI29172.5VAlum Poly
R497
680 ohm
04021%
C270100uF, DNI120610VX5R
C1880
100uF
73
43-V
_lo
w-p
rofile
V67
RS
NS
1S
NS
2
R5615DNI
04
02
C3174
22uF
0805
L550.1uH,0.32mohm,17A
C3113
22uF
0805
C269470uF, DNI29172.5VAlum Poly
V68
RS
NS
1S
NS
2
U230_PWM1
C78100uF, DNI120610VX5R
C1881
22uF1206X5R
C317547uF120616VX5R
U230_PWM0
R6686 DNI
C263470uF, DNI29172.5VAlum Poly
C1882
22uF1206X5R
C87100uF, DNI120610VX5R
U111_PH0
R56010
0402
VCCERAM_PG
ALERTB_S10_VCCPLLDIG_SDM
S10_VCCERAM_SENSE_N
S10_VCCERAM_SENSE_P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power - 3.3V_REG_INST
PMBus Address = 0X44
Default Vout = 3.3V
H = 6.6mmPlace on Top side
RemoteSense NearFPGA Powerballs
connect AGND toPGND through asingle via
Rtune = 1x Base
Cout = Base = 1000uF
POWER LED
Enpirion Dongle
GND_SIGNAL5
12V_PCIE_IN
GND_SIGNAL5
GND_SIGNAL5
GND_SIGNAL5
GND_SIGNAL5
GND_SIGNAL5GND_SIGNAL5
GND_SIGNAL5
GND_SIGNAL5
5V0
12V_PCIE_IN
3.3V_REG_INST
3.3V_REG
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG
3.3V_REG_INSTM10_3.3V
VDD33_563
VDD33_563
I2C1_SDA23,42,49,55,68
I2C1_SCL23,42,49,55,68
3.3V_REG_INST_PG23
VDD33_563
3.3V_REG_EN23,533.3V_REG_PG 23
VDD33_563
EM_I2C_SDA 50,62EM_I2C_SCL 50,62
VDD33_563
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
63 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
63 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
63 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C1869
100UF
R55522.7K
0402
1%
R55503.4K
0402
C58DNI0402
C1773
100UF
C20120.1uF0402
R5546576R
0402
R6644 0
C1867
100UF
R55493.3k 0402
V66
RS
NS
1S
NS
2
C1781
22uF0805X5R
C1771
100UF
R5558
1K
0402
1%
C2008100uF
7343-V_low-profile
C1871
100UF
C1786DNI
04
02
C1782
22uF0805X5R
R6260 0
V65
RS
NS
1S
NS
2
U66_PWM1
R5555DNI
0402
C20090.1uF0402
J17
TSW-103-08-G-S
11
22
33
R554810.0K
R5557DNI 0402
C1780
22uF0805X5R
C178510uF
1206
C20110.1uF0402
C1868
100UF
U136
NCP45560IMNTWG-H
VIN1
EN2
VCC3
GND4
BLEED7
SR5
VOUT9
VOUT8
VIN13
PG6
VOUT10VOUT11VOUT12
C1775
100UF
R55611K
R5562
0
C20100.1uF0402
R664510,DNI
C1777
2.2uF0603
C1776DNI
04
02
R6074DNI0402
C1870
100UF
R55451.5K
0402
R556011k
0402
R6646
10,DNI
C1783
22uF0805X5R
C1778
100uF
734
3-V
_lo
w-p
rofile
C1774
100UF
1206
VCCT_PWRGD1
C1770
100UF
R5711
10.0K,DNI
0402
1%
D53
BLUE LED
R5556DNI
0402
C1779
100uF
734
3-V
_lo
w-p
rofile
C1772
100UF
R342 0
R55592.00K
0402
R343 0
R5537
1K
R555410.0K
0402
FB9742792780
0402
R554710.0K
R60752.2K0402
R5728DNI0402
C1784
22uF0805X5R
U101
EM2130H
AGND70
NC6868
VSENP71VSENN72
VOUT79
VOUT3
VTRACK77
ADDR17
VOUT80
ADDR08
RTUNE5
VOUT2
VCCSEN78
RVSET4
SCL15 SDA14
PG
ND
32
VDD3316
VCC66
NC7676
DGND69
PWM9
VOUT81
VINSEN6
VOUT1
SMBALERT13 CONTROL12 PGOOD11 SYNC10
PG
ND
33
PG
ND
34
PG
ND
35
PG
ND
36
PG
ND
37
PG
ND
38
PG
ND
39
PG
ND
40
PG
ND
42
PG
ND
43
PG
ND
44
PG
ND
45
PG
ND
46
PG
ND
47
PG
ND
48
PG
ND
49
PG
ND
50
PG
ND
41
PGND22
PGND23
PGND24
PGND25
PGND26
PGND27
PGND28
PGND29
PGND30
PGND31
PGND60
PGND59
PGND58
PGND57
PGND56
PGND55
PGND54
PGND53
PGND52
PGND51
PVIN61PVIN62PVIN63PVIN64
PVCC65
NC6767
NC7575
NC7474
NC7373
PVIN17
PVIN18
PVIN20
PVIN21
VO
UT
10
0
VO
UT
99
VO
UT
98
VO
UT
97
VO
UT
96
VO
UT
95
VO
UT
94
VO
UT
93
VO
UT
92
VO
UT
91
VO
UT
90
VO
UT
89
VO
UT
88
VO
UT
87
VO
UT
86
VO
UT
85
VO
UT
84
VO
UT
83
VO
UT
82
PVIN_PAD103
PGND_PAD104
AGND_PAD102
VO
UT
_P
AD
10
1
PVIN19
R55532.7K
0402
1%
R5551DNI 0402
3V3_REG_SENSE_P
3.3V_REG_INST_EN
ALERTB_3.3V_REG_INST
3.3V_REG_INST_PG
3V3_REG_SENSE_N
EM_I2C_SCL
EM_I2C_SDA
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power - 2.4V VCCFUSE_PWRGD
Ra
Rb
Rb=142.2/(VOUT-0.6)
3.3V_REG_INST
U76_AGND
U76_AGND
U76_AGND
U76_AGND
3.3V_REG_INST
U76_AGNDU76_AGND
VCCFUSE_EN23
VCCFUSE_PG23
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
64 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
64 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
64 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R614778.7K
R6143
10
R57340
0402
C2426
22uF
0805
R6264 2.2K0402
U76EP53F8QI
NC(SW1)1
PG
ND
2P
GN
D3
AVIN24
VFB5
NC16
VOUT7
VOUT8
AG
ND
9
AVIN110
POK11
ENABLE12
PVIN13
PVIN14
NC(SW2)15
NC(SW3)16
C2424
680pF
0603
C50
1uF,DNIR6144
100K,DNI
0402
1%
R6145237K
C24281uF0402
C2423
10uF
0805C2427
22uF,DNI
0805R6263
0,DNI
C2422
10uF
0805C2425
5pF
0402
VCCFUSE_PG
VCCFUSE_EN
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Vih=3.3, Vil = 0.3
Vih=3.3, Vil = 0.3
Ra
Rb=142.2/(VOUT-0.6)
Rb
Ra
Rb=142.2/(VOUT-0.6)Rb
Power - 2V5_DDR4, DDR4_VTT 0V6_DDR4_VTT_CH00
S10_1V2OUT_CH00
0V6_DDR4_VTT_CH11
S10_1V2OUT_CH11
0V6_DDR4_VTT_CH00
0V6_DDR4_VTT_CH11
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
2V5_DDR4_CH00
GND_SIGNAL6
3.3V_REG
2V5_DDR4_CH11
3.3V_REG
GND_SIGNAL6GND_SIGNAL6
GND_SIGNAL6
GND_SIGNAL7
GND_SIGNAL7
GND_SIGNAL7
GND_SIGNAL7
U166_AGND
U164_AGND
S10_1V2OUT_CH11
3.3V_REG
0V6_DDR4_VREF_CH11
U166_AGND
S10_1V2OUT_CH00
3.3V_REG
0V6_DDR4_VREF_CH00U164_AGND
U164_AGND
U164_AGND
U164_AGND
GND_SIGNAL6GND_SIGNAL6
GND_SIGNAL7GND_SIGNAL7
U166_AGND
U166_AGND
U166_AGND
0V6_DDR4_VREF_CH00_PG 23
0V6_DDR4_VREF_CH11_PG 23
0V6_DDR4_VREF_CH00_EN23
0V6_DDR4_VREF_CH11_EN23
2.5V_DDR4_CH00_EN23,53
2.5V_DDR4_CH00_PG23
2.5V_DDR4_CH11_EN23,53
2.5V_DDR4_CH11_PG23
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
65 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
65 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
65 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R6113 2.2K0402
C2458
22uF,DNI
0805
C29530.1uF0402
R618175k
C2456
5pF
0402
C246222uF06036.3VX6S
R6176
10
C2472
22uF
0805
R526
100K,DNI
C236422uF06036.3VX6S
C235422uF06036.3VX6S
C235522uF06036.3VX6SC2358
22uF06036.3VX6S
C2956
0.1uF
0402
C233422uF06036.3VX6S
R6109 10.0K,DNIR6110 2.2K
0402
C2457
22uF
0805
C53
1uF,DNI
C235122uF06036.3VX6S
C233122uF06036.3VX6S
R57350
0402
R6183
10
C235622uF06036.3VX6S
C2453
10uF
0805
C2473
22uF,DNI
0805
U166
EV1320QI
NC1
AVIN2
ENA3
POK4
SS5 C1P_1
14
C1P_213
VOUT12
VOUT11
C1N_110
AGND6
C1N_29
VDDQ16 VDDQ15
PGND8
PGND7
R6177 1.0R04021%
C234722uF06036.3VX6S
R6276 10.0K1%
R62710
0402
C2464 10uF0603
X6S6.3V
R618875k
R6274
0,DNI C235322uF06036.3VX6S
C233822uF06036.3VX6S
C233922uF06036.3VX6S
C235222uF06036.3VX6S
R6112 10.0K,DNI
C233222uF06036.3VX6S
-
+
VDD
VSS
U192
MAX4250AAUK+T
1
2
3
4
5
R6277 10.0K1%
R61860
0402
C24741uF0402
C2469
10uF
0805
C236522uF06036.3VX6S
C2455
680pF
0603
C2454
10uF
0805
U164
EV1320QI
NC1
AVIN2
ENA3
POK4
SS5 C1P_1
14
C1P_213
VOUT12
VOUT11
C1N_110
AGND6
C1N_29
VDDQ16 VDDQ15
PGND8
PGND7
R6272 10.0K1%
C2471
5pF
0402
C234622uF06036.3VX6S
C233322uF06036.3VX6S
R6179237K
R6275 2.2K0402
C2468
10uF
0805
C52
1uF,DNI
C246622uF06036.3VX6S
R6185237K
R6273 10.0K1%
C235722uF06036.3VX6S
C2954
0.1uF
0402
U165EP53F8QI
NC(SW1)1
PG
ND
2P
GN
D3
AVIN24
VFB5
NC16
VOUT7
VOUT8
AG
ND
9
AVIN110
POK11
ENABLE12
PVIN13
PVIN14
NC(SW2)15
NC(SW3)16
C2470
680pF
0603
C246715nF040225VX7R
U163EP53F8QI
NC(SW1)1
PG
ND
2P
GN
D3
AVIN24
VFB5
NC16
VOUT7
VOUT8
AG
ND
9
AVIN110
POK11
ENABLE12
PVIN13
PVIN14
NC(SW2)15
NC(SW3)16
C246110uF, DNI0603
X6S6.3V
-
+
VDD
VSS
U193
MAX4250AAUK+T
1
2
3
4
5
R6270 2.2K0402
R519100K,DNI
C2459 10uF0603
X6S6.3V
C246315nF040225VX7R
C24601uF0402
C233722uF06036.3VX6S
C29550.1uF0402
C233622uF06036.3VX6S
R6269
0,DNI
R57360
0402
C246510uF, DNI0603
X6S6.3V
R6182 1.0R04021%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power-1V2_DDR4_CH11
Ra
Rvs
R1 Ca
Css
Cb
Rb
AGND
PLACE Output decoupling capsclose to the device. ConnectAGND and PGND at the point of cap GND connection.
PGND
S10_1V2OUT_CH11 1V2_DDR4_CH11
U157_AGND
3.3V_REG
U157_AGND
U157_AGND
U157_AGND
U157_AGND
3.3V_REG
DDR4_CH11_EN23,53DDR4_CH11_PG23
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
66 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
66 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
66 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R6159 12K
R6151
10.0K,DNI
R615310.0K
R615015K,DNI04021%
C2440 27pF0402
R6265 10.0K,DNIR6266 2.2K
0402
R6155
3.57k
C24310.22uF0402
R6158 158K
C2434
47UF
C243515nF0402
C2438
47UF
R6156
0,DNI
R6162158K
R57320
0402
C2432
47UF
C2433
47UF
C2436
47UF
U157EN63A0QI
EN63A0QI-11x10MM-76QFN
NC
11
NC
22
NC
33
NC
44
NC
55
NC
66
NC
77
NC
88
NC
99
NC
10
10
NC
11
11
NC
12
12
NC
13
13
NC
14
14
NC
15
15
NC
16
16
NC
17
17
NC
18
18
NC1919VOUT20VOUT21VOUT22VOUT23VOUT24VOUT25VOUT26VOUT27VOUT28NC2929NC(SW)3030NC(SW)3131PGND32PGND33PGND34PGND35PGND36PGND37PGND38
S_
IN5
6
BG
ND
55
VD
DB
54
NC
63
53
NC
62
52
PV
IN5
1
PV
IN5
0
PV
IN4
9
PV
IN4
8
PV
IN4
7
PV
IN4
6
PV
IN4
5
PV
IN4
4
PV
IN4
3
PV
IN4
2
PV
IN4
1
PV
IN4
0
PV
IN3
9
NC7676 NC7575 NC7474 NC7373 NC7272 NC(SW)7171 NC(SW)7070 EN_PB69 FQADJ68 NC6767 VSENSE66 SS65 EAOUT64 VFB63 M/S62 AGND61 AVIN60 ENABLE59 POK58 S_OUT57 PGND(PAD)
77
R5973 0.001
R6154
0,DNI
R6157 0
C2437
47UF
DDR4_CH11_PGDDR4_CH11_EN
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power-1V2_DDR4_CH11
Ra
Rvs
R1 Ca
Css
Cb
Rb
PGND
PLACE Output decoupling capsclose to the device. ConnectAGND and PGND at the point of cap GND connection.
AGND
S10_1V2OUT_CH00 1V2_DDR4_CH00
3.3V_REG
U159_AGND
U159_AGND
U159_AGND
U159_AGND
U159_AGND
3.3V_REG
DDR4_CH00_EN23,53DDR4_CH00_PG23
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
67 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
67 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
67 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R6175158K
R616315K,DNI04021%
C2449
47UF
C2442 0.22uF0402
R6171 158K
C2443
47UF
C244615nF0402
C2445
47UF
R57330
0402
R5988 0.001
R6170 0
R6169
0,DNI
U159EN63A0QI
EN63A0QI-11x10MM-76QFN
NC
11
NC
22
NC
33
NC
44
NC
55
NC
66
NC
77
NC
88
NC
99
NC
10
10
NC
11
11
NC
12
12
NC
13
13
NC
14
14
NC
15
15
NC
16
16
NC
17
17
NC
18
18
NC1919VOUT20VOUT21VOUT22VOUT23VOUT24VOUT25VOUT26VOUT27VOUT28NC2929NC(SW)3030NC(SW)3131PGND32PGND33PGND34PGND35PGND36PGND37PGND38
S_
IN5
6
BG
ND
55
VD
DB
54
NC
63
53
NC
62
52
PV
IN5
1
PV
IN5
0
PV
IN4
9
PV
IN4
8
PV
IN4
7
PV
IN4
6
PV
IN4
5
PV
IN4
4
PV
IN4
3
PV
IN4
2
PV
IN4
1
PV
IN4
0
PV
IN3
9
NC7676 NC7575 NC7474 NC7373 NC7272 NC(SW)7171 NC(SW)7070 EN_PB69 FQADJ68 NC6767 VSENSE66 SS65 EAOUT64 VFB63 M/S62 AGND61 AVIN60 ENABLE59 POK58 S_OUT57 PGND(PAD)
77
C2447
47UF
C2444
47UF
R6172 12K
R6268 2.2K0402
R6168
3.57k
R6164
10.0K,DNI
R6167
0,DNI
R616610.0K
R6267 10.0K,DNI
C2448
47UF
C2451 27pF0402
DDR4_CH00_PGDDR4_CH00_EN
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1) M10_2V5 power good2) MAX10 configures itself from CFM3) MAX10 Initiate Power Up Sequence4) MAX 10 Release NCONFIG for S10 to configure from flash5) MAX10 NIOS boot from Flash after S10 CONF_DONE
To FPGA 1V8 bank
VGS(th) = 0.6V / 1V /1.5V
When BMC_I2C1_DISABLE = 1, MAX10BMC is blocked from accessingEEPROM and QSFP Port Controllerover I2C2 bus. This pin should beassigned as open drain output.
Default: Pos_2
Default: Pos_2
Default: Pos_2
Level Translators, IOexp
Pull-ups, downs for U198 - U199 - U200 - U201
Pull-ups, downs for U204, U205, U206 and U207
1.8V
M10_3.3V
1.8V3.3V_REG
1.8V
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
3.3V_REG
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
3.3V_REG
3.3V_REG
1.8V
1.8V3.3V_REG
1.8V3.3V_REG
1.8V3.3V_REG
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
3.3V_REG_INST
1.8V1.8V
I2C1_1V8_SCL7I2C1_SDA 23,42,49,55,63I2C1_SCL 23,42,49,55,63
I2C1_1V8_SDA7
BMC_I2C1_DISABLE7
PCIE_PERSTn21,68
UPI0_PERSTn25
PCIE_PERSTn21,68
UPI2_PERSTn27
UPI1_PERSTn26
UPI0_PCIe_SCL 12UPI0_PCIe_SDA 12
UPI1_PCIe_SCL 12UPI1_PCIe_SDA 12
UPI2_PCIe_SDA 12UPI2_PCIe_SCL 12S10_UPI0_PRNSTn_1V8 12S10_UPI0_NID0_1V8 12,17
S10_UPI0_NID1_1V8 12,17S10_UPI1_PRNSTn_1V8 12S10_UPI1_NID0_1V8 12,17S10_UPI1_NID1_1V8 12,17
S10_UPI2_PRNSTn_1V8 12S10_UPI2_NID0_1V8 12,17S10_UPI2_NID1_1V8 12,17
UPI0_SDA_3V325UPI0_SCL_3V325
UPI1_SCL_3V326UPI1_SDA_3V326
UPI0_NID0_3V325UPI0_PRNSTn_3V325
UPI2_SCL_3V327UPI2_SDA_3V327
UPI1_PRNSTn_3V326UPI0_NID1_3V325
UPI1_NID1_3V326UPI1_NID0_3V326
UPI2_NID0_3V327UPI2_PRNSTn_3V327
UPI2_NID1_3V327
S10_UPI1_PERSTn_SEL 12
S10_UPI0_PERSTn_SEL 12
S10_UPI2_PERSTn_SEL 12
PCIE_Ep_IO 12
UPI0_Ep 17UPI0_Ep_IO 12UPI0_Rp_IO 12
UPI1_Ep 17UPI1_Ep_IO 12UPI1_Rp_IO 12
UPI2_Ep 17UPI2_Ep_IO 12UPI2_Rp_IO 12
PCIE_Ep 17
PCIE_Rp_IO 12,68
PCIE_Rp_IO 12,68PCIE_Rp_IO_3V321
PCIE_LVC1V8_PRSNT2n_x1 8PCIE_LVC1V8_PRSNT2n_x4 8
PCIE_LVC1V8_PRSNT2n_x16 8PCIE_LVC1V8_PRSNT2n_x8 8
PCIE_PRSNT2n_x121PCIE_PRSNT2n_x421PCIE_PRSNT2n_x821PCIE_PRSNT2n_x1621
S10_PCIE_EDGE_WAKEn 8PCIE_EDGE_WAKEn21,23PCIE_CLKREQ_N21 S10_PCIE_CLKREQ_N 8
TRIGGER_IN69TRIGGER_OUT69
S10_LT_DATA0 8S10_LT_DATA1 8
M10_DATA023M10_DATA123M10_DATA223M10_DATA323M10_CLK23M10_SSN23M10_GPIO023M10_GPIO123
M10_DATA0_1V8 7M10_DATA1_1V8 7M10_DATA2_1V8 7M10_DATA3_1V8 7M10_CLK_1V8 7M10_SSN_1V8 7M10_GPIO0_1V8 7M10_GPIO1_1V8 7
TSENSE_ALERTn_1V8 9TSENSE_ALERTn23,33
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
68 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
68 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
Custom
68 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R6035
10.0K
0402
1%
C23590.1uF
040225VX7R
U198
MAX3378EETD+T
VL10
IO VL11
IO VL22
IO VL35
IO VL46
GND7
VCC14
IO VCC113
IO VCC212
IO VCC39
IO VCC48
TS3
NC14
NC211
EP15
R6009
10.0K,DNI04021%
R6008 10.0K0402 1%
R13510.0K04021%
R119 0
R614210.0K04021%
R6027 10.0K0402 1%
C24210.1uF0402
U19674LVC1G3157GM,115
Y11
GN
D2
Y03
Z4
VCC5
S6
R6388 DNI
R6300 DNI
U200
MAX3378EETD+T
VL10
IO VL11
IO VL22
IO VL35
IO VL46
GND7
VCC14
IO VCC113
IO VCC212
IO VCC39
IO VCC48
TS3
NC14
NC211
EP15
R6415 DNI
R6302 DNI
C29700.1uF0402
R53784.70K
R6036
10.0K
0402
1%
R6015 10.0K0402 1%
R6335 DNI
R133 4.70K1%0402
C23410.1uF
040225VX7R
R6020 10.0K0402 1%
ON
SW24
CVS-01TB
1 2
R6486 DNIU205
74LVC1G3157GM,115
Y11
GN
D2
Y03
Z4
VCC5
S6
U21174LVC1G3157GM,115
Y11
GN
D2
Y03
Z4
VCC5
S6
R6014 10.0K0402 1%
R402
10.0K
0402
1%
R6016 10.0K0402 1%
R114 0
R53794.70K
U20774LVC1G3157GM,115
Y11
GN
D2
Y03
Z4
VCC5
S6
R6414 DNI
C31050.1uF
040225VX7R
R132 4.70K1%0402
R110 0
C26510.1uF0402
C26550.1uF0402
U212
MAX3378EETD+T
VL10
IO VL11
IO VL22
IO VL35
IO VL46
GND7
VCC14
IO VCC113
IO VCC212
IO VCC39
IO VCC48
TS3
NC14
NC211
EP15
U34
FXMA2102UMX
A02
A13 B0
7
B16
VCCA1
GND4
OE5
VCCB8
C26530.1uF0402
R6299 DNI
R6024 10.0K0402 1%
R6493 DNI
R134 4.70K1%0402
C146
0.1uF040225VX7R
R6026 10.0K0402 1%
R136 4.70K1%0402
R6029 10.0K0402 1%
R6019 10.0K0402 1%
R6032 10.0K0402 1%
R6301 DNI
R6129 0,DNI
C23420.1uF
040225VX7R
C175
0.1uF
040225VX7R
U19774LVC1G3157GM,115
Y11
GN
D2
Y03
Z4
VCC5
S6
C23600.1uF
040225V X7R
ON
SW18
CVS-01TB
12
R128 4.70K1%0402
R6416 DNI
ON
SW27
CVS-01TB
1 2
R6033 10.0K0402 1%
R6303 DNI
R6030 10.0K0402 1%
R137 4.70K1%0402
ON
SW17CVS-01TB
12
R129 4.70K1%0402
C31040.1uF
040225VX7R
C23430.1uF
040225VX7R
R6021 10.0K0402 1%
ON
SW25
CVS-01TB
1 2
C29710.1uF0402
U204
MAX3378EETD+T
VL10
IO VL11
IO VL22
IO VL35
IO VL46
GND7
VCC14
IO VCC113
IO VCC212
IO VCC39
IO VCC48
TS3
NC14
NC211
EP15
U199
MAX3378EETD+T
VL10
IO VL11
IO VL22
IO VL35
IO VL46
GND7
VCC14
IO VCC113
IO VCC212
IO VCC39
IO VCC48
TS3
NC14
NC211
EP15
C23610.1uF
040225V X7R
R6010 10.0K0402 1%
R6025 10.0K0402 1%
R6013 10.0K0402 1%
ON
SW26
CVS-01TB
1 2
C23400.1uF
040225VX7R
U20674LVC1G3157GM,115
Y11
GN
D2
Y03
Z4
VCC5
S6
C31030.1uF
040225VX7R
R6028 10.0K0402 1%
R1164.70K
1%0402
U194
TXS0108EPWR
VL2
IO VL11
IO VL23
IO VL34
IO VL45
GND11
VCC19
IO VCC120
IO VCC218
IO VCC317
IO VCC416
EN10
IO VL56
IO VL67
IO VL78
IO VL89
IO VCC515
IO VCC614
IO VCC713
IO VCC812
C23300.1uF
040225VX7R
R6031 10.0K0402 1%
1
2
3Q27SI2302CDS-T1-GE3
SOT23
ON
SW16CVS-01TB
12
R6308 DNI
R614110.0K04021%
R117 4.70K1%0402
C26520.1uF0402
R613410.0K04021%
R6034 10.0K0402 1%
C23440.1uF
040225VX7R
R6298 DNI
R6289 DNI
R6018 10.0K0402 1%
R401 1001%0402
C23350.1uF
040225VX7R
R6132DNI
R1154.70K
1%0402
R127 4.70K1%0402
C23500.1uF
040225VX7R
U19574LVC1G3157GM,115
Y11
GN
D2
Y03
Z4
VCC5
S6
C23450.1uF
040225VX7R
R6017 10.0K0402 1%
U201
MAX3378EETD+T
VL10
IO VL11
IO VL22
IO VL35
IO VL46
GND7
VCC14
IO VCC113
IO VCC212
IO VCC39
IO VCC48
TS3
NC14
NC211
EP15
U202
TXS0108EPWR
VL2
IO VL11
IO VL23
IO VL34
IO VL45
GND11
VCC19
IO VCC120
IO VCC218
IO VCC317
IO VCC416
EN10
IO VL56
IO VL67
IO VL78
IO VL89
IO VCC515
IO VCC614
IO VCC713
IO VCC812
R6291 DNI
R6485 DNI
R6490 DNI
R112 0
R6319 DNI
R6012 10.0K0402 1%
R6334 DNI
C31020.1uF
040225VX7R
S10_UPI0_PERSTn_SEL
S10_UPI1_PERSTn_SEL
S10_UPI2_PERSTn_SEL
UPI0_PCIE_PERSTn
UPI2_PCIE_PERSTn
UPI0_PERSTn_SEL
UPI1_PERSTn_SEL
UPI2_PERSTn_SEL
UPI0_PERSTn_SEL
UPI1_PCIE_PERSTn
UPI1_PERSTn_SEL
PCIE_PERSTn
S10_UPI0_PRNSTn_1V8
S10_UPI1_PRNSTn_1V8
S10_UPI2_PRNSTn_1V8
UPI0_PCIe_SDA
UPI0_PCIe_SCL
UPI1_PCIe_SDA
UPI1_PCIe_SCL
UPI2_PCIe_SDA
UPI2_PCIe_SCL
S10_UPI0_NID0_1V8
S10_UPI0_NID1_1V8
S10_UPI1_NID0_1V8
S10_UPI1_NID1_1V8
S10_UPI2_NID0_1V8
S10_UPI2_NID1_1V8
UPI2_PERSTn_SEL
UPI0_PCIE_PERSTn_1V8
UPI1_PCIE_PERSTn_1V8
UPI2_PCIE_PERSTn_1V8
UPI0_Rp_IO
UPI1_Rp_IO
UPI2_Rp_IO
UPI0_EpRp_Sel
UPI1_EpRp_Sel
UPI2_EpRp_Sel
UPI0_EpRp_Sel
UPI1_EpRp_Sel
UPI2_EpRp_Sel
UPI0_Ep_IO
UPI1_Ep_IO
UPI2_Ep_IO
PCIE_Rp_IOPCIE_Ep_IO
PCIE_EPRp_Sel
PCIE_EPRp_Sel
PCIE_PERSTn_1V8
PCIE_Ep
UPI0_Ep
UPI1_Ep
UPI2_Ep
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Level translator
All I/Os are default to inputsat power-on
I2C 7-bit Addr = 0x27I2C 8-bit Addr = 0x4E-4F
3.3V_REG
1.8V
1.8V
3.3V_REG1.8V
1.8V
3.3V_REG1.8V
1.8V
3.3V_REG_INST
3.3V_REG_INST
UPI0_LSIO_RX1_PCIE25 UPI0_LSIO_RX1_PCIE_1V8 8UPI0_LSIO_RX2_PCIE25 UPI0_LSIO_RX2_PCIE_1V8 8UPI0_LSIO_RX5_PCIE25 UPI0_LSIO_RX5_PCIE_1V8 8UPI0_LSIO_RX6_PCIE25 UPI0_LSIO_RX6_PCIE_1V8 8
UPI1_LSIO_RX1_PCIE26 UPI1_LSIO_RX1_PCIE_1V8 8UPI1_LSIO_RX2_PCIE26 UPI1_LSIO_RX2_PCIE_1V8 8UPI1_LSIO_RX5_PCIE26 UPI1_LSIO_RX5_PCIE_1V8 8UPI1_LSIO_RX6_PCIE26 UPI1_LSIO_RX6_PCIE_1V8 8
UPI2_LSIO_RX1_PCIE27 UPI2_LSIO_RX1_PCIE_1V8 8UPI2_LSIO_RX2_PCIE27 UPI2_LSIO_RX2_PCIE_1V8 8UPI2_LSIO_RX5_PCIE27 UPI2_LSIO_RX5_PCIE_1V8 8UPI2_LSIO_RX6_PCIE27 UPI2_LSIO_RX6_PCIE_1V8 8
TRIGGER_IN68
TRIGGER_OUT68
SI5332_CLK_SEL0 22SI5332_CLK_SEL1 22UPI0_CLK_SEL 22UPI1_CLK_SEL 22UPI2_CLK_SEL 22SI5391_CLK_SEL0 22SI5391_CLK_SEL1 22
I2C2_SCL6,7,22,23I2C2_SDA6,7,22,23 Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
69 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
69 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
A
Stratix 10 DX FPGA DEVKIT Board
B
69 69Friday, May 24, 2019
150-0330653-A ( K49172-001)
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
U228
MAX3378EETD+T
VL10
IO VL11
IO VL22
IO VL35
IO VL46
GND7
VCC14
IO VCC113
IO VCC212
IO VCC39
IO VCC48
TS3
NC14
NC211
EP15
U232
PCA9534RGVR
QFN17
P02P13P24P35P47P58P69P710
GND6
A015
SCL12
SDA13
INT_N11
A116
A21
MPAD17
VCC14
R661910.0K,DNI04021%
C31580.1uF
040225VX7R
J93
DNI
1
C32080.1uF
040225VX7R
R665310.0K,DNI04021%
U227
MAX3378EETD+T
VL10
IO VL11
IO VL22
IO VL35
IO VL46
GND7
VCC14
IO VCC113
IO VCC212
IO VCC39
IO VCC48
TS3
NC14
NC211
EP15
R662110.0K,DNI04021%
C31590.1uF
040225VX7R
C31560.1uF
040225VX7R
R6652 10.0K0402 1%
J94
DNI
1
R664910.0K0402
1%
C31540.1uF
040225VX7R
C31570.1uF
040225VX7R
U229
MAX3378EETD+T
VL10
IO VL11
IO VL22
IO VL35
IO VL46
GND7
VCC14
IO VCC113
IO VCC212
IO VCC39
IO VCC48
TS3
NC14
NC211
EP15
R665010.0K0402
1%
R665110.0K0402
1%
C31550.1uF
040225VX7R
I2CGPIO_A2
I2CGPIO_A1
I2CGPIO_A0