Timing requirements
32
Outline Timing Requirements Area problem New Yield Formulations Die Cost Timing Requirements for SEl and clock signals Mostafa Said Sayed [email protected] June 4, 2013 Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
Transcript of Timing requirements
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
Timing Requirements for SEl and clock signals
Mostafa Said [email protected]
June 4, 2013
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
1 Timing RequirementsSEL high period TH requirementsClock edge requirements
2 Area problemCritical value for DTSV
3 New Yield FormulationsTSV yield YTSVDie yield YdieW2W overall yield YW2W
4 Die Cost(1)Preparation cost Cprep(2)Execution cost Cprep
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
SEL high period TH requirementsClock edge requirements
TH requirements
Assume that the delay of the transmission gate GT is tpand the delay of the TSV is tTSV .The SEL high period TH must maintain at 1 for at least tp tocatch the real value of V2.
Figure: TSV-BOX delays.Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
SEL high period TH requirementsClock edge requirements
TH requirements - Cont.
Both SEL and Vo signals will encounter a delay tTSVthrough the TSV to reach the top layerSince tTSV delay is common in both signals therefore it willnot affect the operation of the DeMUX.Vo will encounter another delay through the TG of theDeMUX equal to tp also.Therefore SEL must wait tp until Vo reaches DeMUX andanother tp until Vo passes through the TG of the DeMUX,so now:
TH − tp ≥ tp, (1)
therefore:TH ≥ 2tp. (2)
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
SEL high period TH requirementsClock edge requirements
TH requirements - Cont.
Figure: TH requirements.
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
SEL high period TH requirementsClock edge requirements
Clock edge requirements.
Suppose that both V1 and V2 will be the inputs of two DFFswith equal setup time tsu.Since V2 is delayed with 2tp+tTSV , then the clock risingedge for the DFF should rise at:
2tp + tTSV + tsu. (3)
But V1 is delayed with 2tp+tTSV +TH , so the clock risingedge of the other DFF should rise at:
2tp + tTSV + tsu + TH . (4)
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
SEL high period TH requirementsClock edge requirements
Clock edge requirements - Cont.
Since there is one clock signal, then the clock of this layershould have a rising edge at:
2tp + tTSV + tsu + TH , (5)
which will be suffice for both V1 and V2 to be read correctlyin both FFs.
Figure: Clock edge requirements.
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
Critical value for DTSV
When DTSV is small there may be no reduction in areaThe critical or threshold value DTSVth is the value at whichno reduction in area occursTo determine the DTSVth Let A1=A2Then
Adie + NTSV ATSV = Adie +NTSV
2(ATSV + 2AMUX ) (6)
12
ATSV = AMUX− > ATSV = 2AMUX (7)
πr2 = 2AMUX (8)
r2 =2AMUX
π(9)
r =DTSV
2+ KOZavg =
√2AMUX
π(10)
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
Critical value for DTSV
∵ AMUX = 36 µm in TSMC 180 nm (11)
∴ DTSV + 2KOZavg = 9.654 µm (12)
∴ For area reduction DTSV + 2KOZavg ≥ 9.654 µm (13)
For DTSV =8 µm –> KOZavg=3.25 µm∵ 8+6.5=14.5 > 9.654∴ there will be area reductionWhile for DTSV =5 µm –> KOZavg=0.75 µ∵ 5+1.5=6.5 < 9.654∴ there will be no area reduction
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
Critical value for DTSV
The solution for this problem is to decrease the MUX areaTo decrease the MUX area, it must be implemented usinglower dimension technology that we do not have here inEJUSTI am currently looking for a college that have TSMC 130nm technologyThe main problem is that area will affect also die yield andcost (as will be seen later) since it’s conversely depends ondie area
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
TSV yield YTSVDie yield YdieW2W overall yield YW2W
Introduction
In [Cost-Effective Integration of Three-Dimensional (3D)ICs Emphasizing Testing Cost Analysis] three kinds of3D-IC yields have proposed
1 TSV yield YTSV2 Die yield Ydie3 Overall W2W yield YW2W
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
TSV yield YTSVDie yield YdieW2W overall yield YW2W
TSV yield YTSV
The TSV yield is the probability that all TSVs have nodefects.Suppose that the probability for a faulty TSV is fTSV , then:
YTSV = Probability [all TSVs are non − faulty ]
= (1− fTSV )NTSV . (14)
The TSV yield of the traditional 3D-IC YTSV1 will be:
YTSV1 = (1− fTSV )NTSV , (15)
The TSV yield of the 3D-IC with TSV-BOX YTSV2 :
YTSV2 = (1− fTSV )NTSV
2 . (16)
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
TSV yield YTSVDie yield YdieW2W overall yield YW2W
TSV yield YTSV - Cont.
But since (1− fTSV ) < 1, so:
YTSV2 > YTSV1 . (17)
According to the same reference fTSV varies from 50 ppmto 5% in current TSV process technology.
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
TSV yield YTSVDie yield YdieW2W overall yield YW2W
Die yield Ydie
The die yield is modeled according to the distribution of therandom number of defects on the die.It has been shown that the defects are usually notrandomly distributed across the chip, but are alwaysclustered. The widely used formula is the Gamma functionbased yield model:
Ydie = (1 +DoAdie
α)−α. (18)
The parameter α is a constant depends upon thecomplexity of the manufacturing process, according to thereference α is typically 2
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
TSV yield YTSVDie yield YdieW2W overall yield YW2W
Die yield Ydie - Cont.
Now we can determine the die yield before and after TSVmultiplexing, Ydie1 and Ydie2 respectively, therefore:
Ydie1 = (1 +DoAdie1
α)−α, (19)
Ydie2 = (1 +DoAdie2
α)−α. (20)
As stated from the previous equations, the die yield isdependent on die area.
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
TSV yield YTSVDie yield YdieW2W overall yield YW2W
W2W overall yield YW2W
The overall yield of the 3D chip using W2W bonding can becalculated as:
YW2W = [1 +Do
α(AdieN + ADFT )]
−α
·N−1∏i=1
YS,W2W ,i · (1 +DoAdiei
α)−α, (21)
where ADFT is the area taken by the circuit of the DFT test,and YS,W2W ,i denotes the stacking yield between layer iand layer i-1
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
TSV yield YTSVDie yield YdieW2W overall yield YW2W
W2W overall yield YW2W - Cont.
YS,W2W ,i it is calculated as follows:
YS,W2W = Ybonding · YTSV , (22)
where Ybonding captures the yield loss of the chip due tofaults in the bonding processes and it’s independent of thenumber of TSVs and YTSV is the TSV yield discussedbefore.
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
TSV yield YTSVDie yield YdieW2W overall yield YW2W
W2W overall yield YW2W - Cont.
Three assumptions will be assumed to facilitate thecalculations of the overall yield:
1 Assume that there is no DFT test done to the chip therefore:
ADFT = 0. (23)
2 Let all the dies or layers to have the same area so,
Adie1 = Adie2 = · · · = AdieN = Adie. (24)
3 Assume that the number of TSV per layer is the same thenwe can say that
YS,W2W ,1 = YS,W2W ,2 = · · · = YS,W2W ,N−1 = YS,W2W . (25)
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
TSV yield YTSVDie yield YdieW2W overall yield YW2W
W2W overall yield YW2W - Cont.
Now, Eq. 21 reduces to
YW2W = [1 +DoAdie
α]−Nα · Y N−1
S,W2W . (26)
As stated also in the equation above that YW2W alsodependent on die area
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
(1)Preparation cost Cprep(2)Execution cost Cprep
Introduction
In [Modeling the Economics of Testing: A DFT Perspective]the die cost is
Ctest = Cprep + Cexec + Csilicon + Cquality (27)
Cprep captures fixed costs of test generation such as testerprogram creation and nonrecurring costs.Cexec consists of costs of test-related hardware such asprobe cards.Csilicon is the cost required to incorporate DFT features(here it will be zero).Cquality is the cost increase mainly due to the fault dies thatpass the test while they are real faulty.
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
(1)Preparation cost Cprep(2)Execution cost Cprep
(1)Preparation cost Cprep
The preparation cost is
Cprep =(Ctest gen + Ctest prog + CDFT design)
Ydie, (28)
Ctest gen is the test-pattern generation costCtest prog is the tester-program preparation cost,CDFT design is the additional design cost for DFT (will be setto zero)
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
(1)Preparation cost Cprep(2)Execution cost Cprep
(1)Preparation cost Cprep - Cont.
Ctest gen = (Rperson hour Ttest gen)/V (29)
Ttest gen = Ktest gen · eAdie (30)
Ctest prog = βtest progCtest gen (31)
CDFT design = 0,assuming there is not DFT test (32)
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
(1)Preparation cost Cprep(2)Execution cost Cprep
(1)Preparation cost Cprep - Cont.
Parameter Description Range or valueRperson hour Cost of one person-hour
for test generation $50/hrTtest gen Test generation time Ktest gen · eAdie .V Production volume or the
total number of ICs produced from (105) to (108)Ktest gen Constant multiplier that
relates test generation timeto the IC die area A 5122 hr
βtest prog A translating factor 0.20
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
(1)Preparation cost Cprep(2)Execution cost Cprep
(2)Execution cost Cexec.
Cexec =(Chw + Ctester )
Ydie(33)
The cost per die of using hardware for testing (excluding thetester) Chw is
Chw =QprobedV/Nprobe lifee
V(34)
The cost per die of using the tester Ctester is
Ctester = [Ract + Rinact(1− βutil)
βutil]Ttest (35)
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
(1)Preparation cost Cprep(2)Execution cost Cprep
(2)Execution cost Cexec. - Cont.
Where Ract is the cost rate (dollars per second) for an activetester, Rinact is the cost rate for an inactive tester,
Ract = Rinact(1 + βact) and Rinact =(Qcapitalβdepr )
Tsec per yr(36)
Qcapital = Kcapital · K√
Apins (37)
the tester utilization factor (the percentage of time the tester isactually testing ICs) βutil is:
βutil = TtestV/(Tsec per yrbTtestV
Tsec per yrc) (38)
the average time(seconds) required to test a single IC Ttest is:
Ttest = Tsetup + [Ydie + βfail(1− Ydie)]Kt timeA2die (39)
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
(1)Preparation cost Cprep(2)Execution cost Cprep
(2)Execution cost Cexec. - Cont.
Parameter Description Range or valueQprobe The unit price
of a probe card $1000Nprobe life The number of ICs a probe
card can test 105 diesQcapital The tester price Eq. 37Kcapital Tester price per pin $7,800/pinKpins Relates the number of pins to
the IC die area A 141/cm
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
(1)Preparation cost Cprep(2)Execution cost Cprep
(2)Execution cost Cexec. - Cont.
Parameter Description Range or valueβdepr Depreciation rate 0.40βact The fractional increase in rate
when a tester is actively used 0.25βfail The average percentage of
good-die test time requiredto test a defective IC not given
Tsetup The setup time for an ICon the tester not given
Kt time a constant multiplier that relatestest time to IC die area A 4.8 s/cm2
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
(1)Preparation cost Cprep(2)Execution cost Cprep
(3)Imperfect test quality Cquality .
Cquality = Closs perform + Cescape + Closs yield (40)
Closs perform is the loss in profit from performancedegradation because of added DFT circuitry (will be set to0)Cescape is the cost of test escape
Cescape = Mcost · αescape · Er (41)
where Er is the test escape rate
Er = 1− Y 1−fdie (42)
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
(1)Preparation cost Cprep(2)Execution cost Cprep
(3)Imperfect test quality Cquality . - Cont.
Mcost is the manufacturing cost
Mcost = Cbasic + Cfab (43)
whereCbasic = Cprep + Cexec (44)
which is calculated before, and
Cfab =Qwafer
πR2waferβwaf die
Adie
Ydie(45)
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
(1)Preparation cost Cprep(2)Execution cost Cprep
(3)Imperfect test quality Cquality . - Cont.
Parameter Description Range or valuef Fault coverage 0.95 to 0.99αescape the multiplying factor representing
the risk incurred by acceptinga defective IC as good 1 to 20
βwaf die the percentage of wafer area thatcan be divided into dies 0.90
Qwafer wafer cost $1,300Rwafer wafer radius 100 mm
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
(1)Preparation cost Cprep(2)Execution cost Cprep
Conclusions about die cost
1 Cdie is not constant as was expected before2 Cdie is dependent on die area Adie
3 To compute Cdie there are still 2 parameters that’s notknown yet which I do not find in that paper βfail and Tsetup
4 One way to find them is that, Fig. 2 in the paper draws theTtest , so we can pick up 2 points on the curve and solvethat 2 unknown linear system to find those unknowns
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
OutlineTiming Requirements
Area problemNew Yield Formulations
Die Cost
The end
Thanks
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
