Timing Analysis in Quartus

© 2000 Altera Corporation

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Timing Analysis in Quartus


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Features

Quartus is capable of doing single clock design timing analysis and multi-clock design timing analysis

Single clock timing analysis– Fmax (maximum clocking frequency)– Tsu, Th, Tco (setup time, hold time, clock-to-out time)– Slack analysis for Fmax (incl. delays to/from pins)

Multi-clock analysis– Allows user to analyze timing for a design containing register-to-

register paths which are controlled by different clocks– Slack analysis is used

Combinatorial Loop Detection– Quartus automatically detects combinatorial loops


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Features

Different types of timing information (Refer to the compilation section for more information) – Timing without place & route– Timing with place & route– A mix of both for a hierarchical design

By default, timing analysis is performed automatically after compilation– Can be disabled

Timing information can be exported to other EDA tools via VHDL, Verilog and Standard Delay File (SDF)


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In This Section

Timing analysis for a single clock system– Register Performance– Setup Time– Hold Time– Clock-to-Out

Making Timing Assignments Timing analysis of a multi-clock system How to make multi-cycle assignments Timing Wizard


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Compile Design

Step 2: Investigate the type of delayin this design

Step 1:The internal fmax is 83.19 Mhz. This value is automatically given for each clock in the Message Window (Processing Tab)


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Timing information is part of the Compilation Report– Summary

Timing Analyses– fmax (not incl. delays to/from pins) or

fmax (incl. delays to/from pins)– Register-to-Register Table– tsu (Input Setup Times)– th (Input Hold Times)– tco (Clock to Out Delays)– tpd (Pin to Pin Delays)

All timing results are reported here

Reporting Timing Results


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fmax (not incl. delays to/from pins)

Clock Period = Clock-to-out + Data Delay + Setup Time - Clock Skew = tco + B + tsu - (E - C)

Fmax = 1/Clock Period

B

C

tco tsu

E

Clock Period


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fmax Analysis

Select fmax

Worst fmax

Destination Register

Quartus Detected Clock

fmax values are listed in ascending order. The worst fmax is listed on the top.


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fmax Analysis

Expand to see the source registers feeding the selected destination register

Source registers and associated fmax values

Timing Analysis By Default Lists 10 Worst Paths– Can Change in Project -> Timing Settings (discussed later)


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fmax Analysis

Highlight & right mouse and select List Paths

To Analyze the Path More Closely

The steps above are similar for all timing path analysis in Quartus


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fmax Analysis

Data Delay (B)

Source Register Clock Delay (C)

Setup Time (tsu)

B

C

tco tsu

E

Clock Period

Destination Register Clock Delay (E)

Clock to Output (tco)

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0.33 ns + 11.257 ns + 0.45 ns + 0.00= 83.08 MHz

Messages Window (System Tab) in Quartus


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fmax Analysis

Interconnect Delay

Cell Delay Running Total

The convention above is similar for all timing path analysis in Quartus

This signal path consists of 11 locations

Destination Cell


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0.000 ns + 0.191 ns = 0.191 ns0.000 ns is the carry chain delay (interconnect delay)0.191 ns is the combinatorial delay

Note:If the delay path involves a carry chain, you can only see the delay path value in the Floorplan when the Floorplan is set to Logic Cell View. LAB View does not show that delay path.

0.191ns is equalto the carry chain delayplus combinatorial delay

Floorplan:Logic Cell View

Carry Chain in Data Delay Path


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Highlight path

Right click & select Locate

Locate Delay Path in Floorplan

The steps above are similar for all timing path analysis in Quartus


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11.257 ns is thetotal register to register delay path

Locate Delay Path in Floorplan


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Fmax (incl. delays to/from pins)

System Fmax = 1 / (the longest of the 3 following delays: Clock Period, Input Pin Period, Output Pin Period)

Clock Period = C + tco + B - E + tsu

Input Pin Period = External Input Delay + A - C + tsu

Output Pin Period= E + tco + Q + External Output Delay

A

C

tco tsu

EExternal

Input DelayExternal

Output Delay

Clock PeriodInput Pin Period Out Pin Period

B Q


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Input Pin Period


A

C

tsu

ExternalInput Delay

Input Pin Period

Value entered in Quartus (shown later)


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External Input Delay

External Input Delay is used to model the delay between an imaginary register and a register inside an Altera device

External Input Delay = EC + tco + ET


EC

ET A

C

tco tsu

Altera DeviceExternal Input Delay

Imaginary Register


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Output Pin Period

Output Pin Period = E + tco + Q + External Output Delay

tco

ExternalOutput Delay

Output Pin Period

Q

E

Value entered in Quartus (shown later)


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External Output Delay

External Output Delay is used to model the delay between a registered output from an Altera device to an imaginary register

External Output Delay = ET + tsu - EC

Output Pin Period = E + tco + Q + External Output Delay

E

Q ET

tco

dst

External Output DelayAltera Device

EC

Imaginary Register

tsu


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Fmax (incl. delays to/from pins)

Select fmax (incl. Delays to/from pins)

Fmax values

The worst fmax is shown at the top by default.

External Delay is shown in Messages Window after List Path


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Setting External Input/Output Delay

Default (Global) External Delay for all I/Os

1) Project -> Timing Settings

2) Select Default External Delays

3) Set Delay Value(s)


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Setting External Input/Output Delay

Individual Pin(s)

1) Tools -> Assignment Organizer

2) Locate Pin(s)

3) Select Timing from Assignment Categories

3) Set Delay Value(s) for Pin(s)


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Setup Time Analysis

Clock delay

tsu

Data delay

tsu = data delay - clock delay + intrinsic tsu

intrinsic tsu


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Setup Time Analysis

All Registers Fed by Pin

Clock NameSelect tsu

Input Pin Name

The greatest setup time is shown at the top by default.


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thold Analysis

Clock delay

thold

Data delay

thold = clock delay - data delay + intrinsic thold

intrinsic thold


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thold Analysis

Register Name

Clock NameSelect th

Input Pin (Data) Name

Negative hold times are shown as “<= 0”

The longest hold time is shown at the top by default.


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tco Analysis

Data delay

tco

Clock delay

clock delay + intrinsic tco + data delay = tco

intrinsic tco


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tco Analysis

Output Pin Name

Clock Name

Select tco

Register Name

The slowest clock-to-output time is shown at the top by default.


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Used to Limit Which Paths Are Displayed by Timing Analyzer

Two Ways to Set Options– Project -> Timing Settings -> Other Requirements & Options– Project -> Timing Wizard

Examples– Cut Off Feedback From I/O Pins (next slide)– Cut Off Clear and Preset Signal Paths

• If checked, Quartus Will Not Analyze Register Clear and Preset Delays

– Cut Off Read During Write Signal Paths• Turn ON if Read During Write is an Invalid Path

Timing Analysis Options


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Option: Cut Off Feedback from I/O Pin

clk

Q DA

Register 1 Register 2

Global Timing Option: Cut off feedback from I/O Pin Used to break I/O pin from the analysis When on, paths A and B are valid. C is not valid. When off, paths A, B, and C are valid.

I/O

Pin

C

B


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Used to Limit How Many Paths Are Displayed by Timing Analyzer

How to Set Option– Project -> Timing Settings -> Timing Analysis Reporting

Examples– Show “XX” Source Nodes Per Destination Node

• Controls by Number How Many Paths Are Displayed– Exclude Paths With fmax Greater Than “XX”

• Controls by Parameter Value (fmax) How Many Paths Are Displayed

– Exclude Paths For tsu, tco, thd Also



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List 10 Paths

List Paths with fmax less than 50 MHz

List Paths with tsu greater than 3 ns


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Single Clock Timing Analysis

The timing analysis that we just went over can be classified as a single clock frequency analysis

Single clock frequency analysis is automatically done during each compile

Quartus will automatically detect clocks if no assignments are made– More information about clock assignments is coming up in multi-

clock timing analysis

Check results in Report Window


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Timing Assignments

Timing assignments have two impacts on designs – 1. During timing analysis, they specify required times the design

is measured against– 2. During compilation, they become timing requirements which

Quartus has to meet when performing timing driven compilation (TDC)• Note: by default, TDC is on

5 types of timing assignments exist:– fmax, tsu, thold, tco, tpd

These timing assignments can be assigned globally or locally


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Examples of Timing Assignments

fmax timing assignment

The values are BLACK, because Actual fmax meets the Required fmax

tsu timing assignment. The numbers are RED, because the Actual tsu does not meet the Required tsu

Timing Assignments used in Timing Analysis


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Timing Driven Compilation

Timing Driven Compilation (TDC) directs the compiler to synthesize and place logic to meet timing specified requirements– Critical paths will be placed closer together in the device

Optimize for I/O Timing and/or Internal Timing

Choose Normal or Extra Effort (works harder & takes longer)


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Global Assignment: Timing Settings

For a design with separate clocks, you can enter the required fmax. The Default required fmax will be applied to each individual clock in the design.

Global Clock Assignment for a single clock design


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Global Assignments - Timing Settings

Global tsu. All input or bidirectional pins are measured against this tsu requirement

Global tpd. All pin-to-pin delays are measured against this tpd requirement

Global tco. All registers driving outputs or bidirectional pins are measured against this tco requirement

Global th. All input or bidirectional pins are measured against this th requirement


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Individual Assignments

tsu (setup time) and th (hold time) assignments– Single point assignment– Point-to-point assignment

tco (clock-to-out) assignment– Single point assignment– Point-to-point assignment


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Timing Assignments

What can be tagged with a timing assignments?– Registers (all)– Clock Pins (all)– Input Pins (tsu, th)– Output Pins (tco)– Bidirectional Pins (all)


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Assign single point setup/hold requirement to the data pin

Setup/Hold Requirements

Assignments can be either single point or point-to-point Single point setup/hold requirements

– States that the setup/hold time is required on every register that the pin feeds


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Assign point-to-point setup requirement to the input pin and the destination register

Setup/Hold Requirement: Point-to-Point

The setup/hold time is required only for the specified path

Reg1

Reg2data0


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......

Clock To Out Requirements

Either a single point or a point-to-point assignment Same idea as setup/hold time requirements Tco requirement on a clock pin

– Means that all Tco paths that start from the specified clock must meet this requirement


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tco requirement on an output pin– Means that all paths from clocks to the specified output pin must

meet this requirement


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Point-to-point tco requirement– Can specify that all paths that go from a specific clock pin to a

specific output pin must meet this requirement


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Example: Assign Setup Requirement

Step 2: Select Timing from the Assignment Category box

Step 3: Choose tsu Requirement from the drop-down list in the Settings section

Step 1: Enter the data pin name or use the Node Finder to locate data pin name and/or register name

Menu Bar: Tools > Assignment Organizer...


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Example: Assign Setup Requirement

Step 4: Type in the setup requirement

Step 6: Click Add to add the assignment

Step 5: Use Fed by: to create a point-to-point requirement


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Multi-Clock Frequency Analysis

Allows user to analyze timing for a design containing register-to-register paths which are controlled by different clocks– Unless Specified, Quartus Treats Individual Clocks As Having the

Same Frequency and Phase

clk1

tco tsu

Combinatorial logic

clk2

capturing edge

launching edge

clk1

clk2

dataRegister 1 Register 2


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Slack Between Two Clock Domains

Slack is used to keep track of the delay between Register 1 and Register 2Positive Slack– If the slack is positive, then the data from Register 1 will meet the

setup time of Register 2

Negative Slack– If the slack is negative, then the data from Register 1 will violate

the setup time of Register 2

clk1

tco tsu

Combinatorial logic

clk2



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Equation for Slack

Slack = Required Time - Actual TimeSlack = Slack Clock Period - ( Intrinsic tco + Data Delay + Intrinsic tsu )

launching edge

clk1

clk2

capturing edge

Slack clock period

clk1

tco tsu

Combinatorial logic

clk2


data delay


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Calculating Slack in Quartus

In order for Quartus to calculate the Slack between registers, timing assignments need to be entered by the user

IMPORTANT: The slack section inside the compilation report file does not appear automatically for a multi-clock design – Timing assignments need to take place first


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Slack Analysis: Steps to Follow

Follow the steps below to prepare Quartus for Slack Analysis– Create Clock Settings

• Define a base clock• Define other clock/s that is/are relative to the base clock

– Assign Clock Settings to actual clocks– Recompile design– Look at result in the slack timing table


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Create Clock Settings

Minimum of 2 clock settings exist for a multi-clock design:– One is a base clock– Second is a derived clock referenced to a “base” clock

• Derived clocks can be any ratio (m/d) of base clock plus an added offset, if desired.

Note: If the design has more than 2 clocks, additional derived or base clocks can be created

offset

capturing edge

launching edge

base clock

derived clock

derived clock = base clock x (m/d) + offset


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Create Clock Setting: Base Clock

Menu Bar: Project > Timing Settings...

Step 1: Click New to Add New Setting


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Create Clock Setting: Base Clock


Step 2: Enter the name of the clock setting

Step 3: Select Independent of other clock settings

Step 4: Adjust fmax and Duty Cycle

Step 5: Click OK to Add Setting


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Create Clock Setting: Derived Clock


Step 1: Click New to Add a New Setting


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Step 2: Enter the Name of the Derived Clock Setting

Step 3: Select clock setting that this derived clock is based on

Step 4: Click on Derived Clock Requirements


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Step 5: Adjust ratio and offset. The derived clock duty cycle is not affected by the multiply base or the divide base. Invert base clock is also available. Click OK when done.

Step 6: Click OK to Add Setting


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Current Clock Settings

At this point, an absolute clock setting called base clock and a derived clock setting called derived clock have been created. The next step is to apply these clock settings to the actual clock nets.

Absolute clock settingcalled base

Derived clock settingcalled derived


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– Assign Clock Settings to actual clocks– Recompile design– Look at slack results in compilation report file


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Assign Absolute Clock Settings to Clock

Menu Bar: Tools > Assignment Organizer... Step 1: Enter the name of the clock pin. The naming convention is: |<project name>|<name> of the pin>

or click on the Node Finder to select the clock pin

Step 2: Click on Timing and select Clock Setting

Step 3: Select Base Clock Settings for this specific clock pin. Click on Add

Derived Clock Setting:Repeat Step 1 to Step 3 for the derived clock setting


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Recompile Design & View Slack Information

Recompile design

Slack

During compilation,slack information is reported in the message window


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Slack Distribution

IMPORTANT: Negative Slack Timeneeds to be corrected in orderfor the design to work

Select

Determine if any and/or how many nodes receive a negative slack?


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Slack Time Table

Slack Time Table offers more details about the source nodes and destination nodes– Positive slack means the timing was met– Negative slack shows by how much the timing was not met– IMPORTANT: Design needs to be altered or multi-cycle timing

requirement/s is/are needed to resolve the negative slack issues

Negative slack times show up in red and are listed at the top of the table

Select


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Multicycle Paths

Signal Paths That Intentionally Require More Than One Cycle to Become Stable– Must Be Considered in Design Implementation

Declaring a Multicycle Path Tells the Timing Analyzer to Account for Multiple Clock Edges Between Nodes or Clock Domains

launching edge

base clock

derived clock

capturing edge


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Assigning Multicycle Paths

Destination Register– Multi-cycle assignment is applied to all signal paths feeding

register

Register-to-Register– Point-to-point assignment that applies to one source register and

one destination register

Two Clock Domains– Assignment applies to all signals that travel from one clock

domain to another

launching edge

base clock

derived clock

capturing edge


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Comparable Offset vs. Clock Period

If the value of your offset is comparable to the value of the clock period, then a multi-cycle assignment on the derived clock is usually unnecessary.– ex. offset = 11ns, clock period = 20ns

offset

capturing edge

launching edge

base clock

derived clock


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Relatively Small Offset vs. Clock Period

If the offset value is relatively small compared to the clock period, then a multi-cycle assignment is usually necessary on the derived clock – Ex. Clock period = 10ns, offset = 2ns– The offset can be thought of as clock skew

offsetoffsetIntended capturing edge

launching edge

However, by default, Quartus assumes this is the capturing edge

base clock

derived clock


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launching edgetrue clock(base clock)

complement clock(derived clock)

capturing edge

Inverted Clock

If your design uses both the true and complement of the same clock signal, then a multi-cycle assignment is not necessary– You can assign the true clock as the base clock– You can assign the complement as the inverse of the base clock


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base clock(source)

derived clock(destination)

Non-Integer Multiples

If the design clocks are non-integer multiples of each other, then a multi-cycle assignment may be necessary– Quartus analyzes two closest edges of base & derived clocks

Ex. base clock = derived clock * 3/4

These two edges are most likely to cause a setup violation of the destination register


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base clock(source)

derived clock(destination)

Non-Integer Multiples

If the design clocks are non-integer multiples of each other, then a multi-cycle assignment may be necessary– Quartus analyzes two closest edges of base & derived clocks

launching edge

capturing edge

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Ex. base clock = derived clock * 3/4


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Multi-Cycle Assignment

Multi-cycle assignment on the derived clock indicates the capturing edge is not the closest rising edge.

offsetoffsetcapturing edge

launching edge

Multi-cycle assignment indicates this is the capturing edge

base clock

derived clock

1) For multi-cycle assignments, the capturing edge is the reference edge

2) The base clock is the reference clock for counting the number of edges between the capturing edge and launching edge

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Making a Multi-Cycle Assignment

1) Choose Timing and Multicycle from the Assignment List

Menu Bar: Tools > Assignment Organizer...

2) Specify the number of edges

3) Use Fed by if creating two clock assignment or point-to-point


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Easy way to enter timing assignments Consolidates all timing assignments in one menu

– Individual clock settings OR overall circuit frequency

– Default system timing

• tsu

• th

• tco

• tpd

– Default external input/output delays

– Enable/Disable timing analysis

during compilation

– Timing driven compilation

Timing Wizard


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Summary

Timing analysis for a single clock system– Registered Performance– Setup Time– Hold Time– Clock-to-Out

Making Timing Assignments Multi-clock timing analysis Multi-cycle timing assignments Timing Wizard

Timing Analysis in Quartus

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