Time-Interleaved ADCs - Theory and Design -...
Transcript of Time-Interleaved ADCs - Theory and Design -...
Time-Interleaved ADCsTheory and Design
Manar El-Chammas
Texas Instruments
December 11, 2011
Who am I?
Received B.E. from A.U.B. in 2004
Received Ph.D. from Stanford University in 2010I Thesis: “Background calibration of timing-skew in time-interleaved
ADCs”I Ph.D. Advisor: Boris MurmannI Research interests: Integrated circuits, background calibration, low
power design
Currently working at Texas Instruments (Dallas, TX) on high-speeddata converters
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Tutorial objectives
To understand the theory and operation of time-interleaved ADCsand how to design them
At the end of this tutorial, you will have a toolbox to analyzetime-interleaved ADCs with and a starting point from which todesign one
�� ��Stop me whenever you have questions
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A broad-stroke outline
Overview of data converters
The time-interleaved ADC
Quantitative analysis of time-varying errors
Design of time-interleaved ADCs
Calibration
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Part I
Overview of Data Converters
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Introduction
Data converters important part of signal chain
[Slide taken from B. Murmann notes]
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Data converter applications
Consumer electronicsI Video and audioI Digital camerasI Automotive systems
Communication systemsI Wireless infrastructureI Ethernet
Computing and controlI Storage mediaI Feedback systems
InstrumentationI Medical equipmentI Oscilloscopes
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Examples
Agilent oscilloscope
Published in ISSCC 2003
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Examples
1 kS/s ADC for medical implants
Published in ESSCIRC 2010
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Examples
TI ADC used in wireless infrastructure
Published in ISSCC 2010
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Reference books
Principles of Data Conversion System Design, Behzad Razavi
Data Converters, F. Maloberti
CMOS Data Converters for Communications, Mikael Gustavsson et al.
Understanding Delta-Sigma Data Converters, Richard Schreier et al.
Data Conversion Handbook, Analog Devices Inc.
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Analog-to-digital conversion
Definition
The conversion from a continuous-time signal to a discrete-timerepresentation
ADCIN OUT
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Analog-to-digital conversion
Analog-to-digital conversion consists of two operations ...
Sampling
Quantization
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Sampling and quantization
Sampling
(Discretizing in time)
Quantization
(Discretizing in amplitude)
[Murmann notes]
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Sampling and quantization
Most common approach is to discretize uniformly in both time andamplitude
These two concepts alone can fill an entire semester ...
For more on these, see reference books
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Types of ADCs: the flash ADC
Flash ADC has 2B − 1 comparators
Extremely fast with limited resolution
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Types of ADCs: the pipeline ADC
Pipeline ADCs have moderate speed and high resolution
[Image from B. Murmann notes]
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Types of ADCs
SAR
Sigma-delta
Algorithmic
Single-slope
Time-to-digital
... references previously mentioned discuss most of these
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Part II
The Time-Interleaved ADC
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Introduction to time-interleaved ADCs
Definition
An ADC that cycles through a set of N sub-ADCs, such that the aggregatesample-rate is N times the sample-rate of the individual sub-ADCs
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Introduction to time-interleaved ADCs
0(t)
x(t) y[n]
ADC0
ADC1
ADCN-1
1(t)
N-1(t)
. . .
.
Sub-ADCs tend to be identical
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Back in 1980 ...
William Black, Ph.D. thesis“High Speed CMOS A/Dconversion techniques”
Published “Time-InterleavedConverter Arrays”
[Black 1980]�� ��This “high speed” technique was for a 7-bit 2.5 MHz ADC
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... 30 years later
Time-interleaved ADCs are still a serious research area
Multi-GHZ ADCs are the normI Agilent, 2003: 80-way interleaved 20 GS/sI Fujitsu, 2009: 4-way interleaved 56 GS/sI Nortel, 2010: 16-way interleaved 40 GS/s
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How exactly does it work?
Intuitive in the time-domain
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First ADC samples the signal ...Example of Two Interleaved Sub-ADCs
12
x(t) y[n]
ADC0
ADC1
x(t)
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Second ADC samples the signal ...Example of Two Interleaved Sub-ADCs
13
x(t) y[n]
ADC0
ADC1
x(t)
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And again, first ADC samples the signal ...Example of Two Interleaved Sub-ADCs
14
x(t) y[n]
ADC0
ADC1
x(t)
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Time-domain analysis
Each sub-ADC output is (ignoring quantization)
yi [n] = x ((nN + i)Ts) (1)
where Ts is sampling period, N is interleaving factor, andi = 0, ...,N − 1
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Time-domain analysis
0(t)
x(t) y[n]
ADC0
ADC1
ADCN-1
1(t)
N-1(t)
. . .
.
Output multiplexer combines these streams such that
y [n] = yi
[n − i
N
]where i = n mod N (2)
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Frequency-domain analysis
This is less intuitive ...
Can take the discrete-time Fourier transform (DTFT) of the(upsampled) sub-ADC outputs and the time-interleaved ADC output
In theory, ...
Y (f ) =N−1∑i=0
Yi (f ) (3)
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Frequency-domain analysis
Assume you have an input signal with the following DTFT
0 0.2 0.4 0.6 0.8 1
0
0.2
0.4
0.6
0.8
1
|X(f
)|
f
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Frequency-domain analysis
The resulting (upsampled) sub-ADC output DTFT will be
0 0.2 0.4 0.6 0.8 1
0
0.05
0.1
0.15
0.2
0.25
|Y0(f
)|
f
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Frequency-domain analysis
Replicas have different phases for each of the sub-ADCs
When summed, the phases cancel each other out
You will get the same spectrum as the input
0 0.2 0.4 0.6 0.8 1
0
0.2
0.4
0.6
0.8
1
|Y(f
)|
f
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Time-varying errors
In theory, theory and practice are the same.
In practice, they are not.
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Time-varying errors
Ideally, a time-interleaved ADC can be blackboxed into a singlemonolithic ADC
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Time-varying errors
Offset
Gain
Timing skew
(Bandwidth)
0(t- 0)
x(t) y[n]
ADC0
ADC1
ADCN-1
1(t- 1)
N-1(t- N-1)oN-1
GN-1
o1
G1
o0
G0
. . .
.
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Time-varying errors
Ideal
-1 0 1 2 3 4 5 6 7 8 9 10
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
x(t)
Offset
-1 0 1 2 3 4 5 6 7 8 9 10
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
x(t)
Gain
-1 0 1 2 3 4 5 6 7 8 9 10
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
x(t)
Timing Skew
-1 0 1 2 3 4 5 6 7 8 9 10
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
x(t)
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Sources of errors
PVT (Process, voltage, temperature) variations
Current flow, layout nonidealities, mismatch in stray capacitance, etc.
�� ��All of these will limit your ADC performance
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Offset mismatch
Each sub-ADC ideally digitizes x(t)
yi [n] = x ((nN + i)Ts) (4)
Each sub-ADC actually digitizes x(t) + oi
yi [n] = x ((nN + i)Ts) + oi (5)
oi is different for each sub-ADC
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Frequency-domain effects
0 0.2 0.4 0.6 0.8 1
0
0.05
0.1
0.15
0.2
0.25|Y
0(f)|
f
The DTFT of the sub-ADC changes because of these offsets
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Frequency-domain effects
0 0.2 0.4 0.6 0.8 1
0
0.5
1
|Y(f
)|
f
The DTFT of the ADC has spurs at frequencies i · fs/N
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Gain mismatch
Each sub-ADC ideally digitizes x(t)
yi [n] = x ((nN + i)Ts) (6)
Each sub-ADC actually digitizes Gix(t)
yi [n] = Gix ((nN + i)Ts) (7)
Gi is different for each sub-ADC
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Frequency-domain effects
0 0.2 0.4 0.6 0.8 1
0
0.05
0.1
0.15
0.2|Y
0(f)|
f
The DTFT of the sub-ADC changes because of these gain differences
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Frequency-domain effects
0 0.2 0.4 0.6 0.8 1
0
0.2
0.4
0.6
0.8|Y
(f)|
f
The DTFT of the ADC has replicas at frequencies fin − i · fs/N
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Timing skew
Each sub-ADC ideally digitizes x(t)
yi [n] = x ((nN + i)Ts) (8)
Each sub-ADC actually digitizes x(t − τi )
yi [n] = x ((nN + i)Ts − τi ) (9)
τi is different for each sub-ADC
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Frequency-domain effects
0 0.2 0.4 0.6 0.8 1
0
0.05
0.1
0.15
0.2
0.25|Y
0(f)|
f
The DTFT of the sub-ADC changes because of timing skew
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Frequency-domain effects
0 0.2 0.4 0.6 0.8 1
0
0.2
0.4
0.6
0.8
1|Y
(f)|
f
The DTFT of the ADC has replicas at frequencies fin − i · fs/N
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Some notes
Gain and offset mismatch are “static” errors
Impact independent of input frequency
But ... what if gain is a function of frequency? (which it is)
And ... what if the gain transfer function varies? (which it will)
You have bandwidth mismatch ...
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Some notes ... continued
Timing skew is not a “static” errorSampling Error Due to Timing Skew
Skew
Error Error
x(t)
Ideal Sampling
Point
Actual Sampling
Point
SkewIdeal
Sampling Point
Actual Sampling
Point
x(t)
t t
18
“Fast” signals suffer more sampling error due to timing skew than “slow” signals
“Fast” signals suffer more sampling error due to timing skew than“slow” signals
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Why is timing skew such a problem?
ADCs are generally uniform sampling systems
What if two consecutive samples aren’t at times nTs and (n + 1)Ts?
I If the deviation is random, you have jitterI If the deviation is deterministically time-varying because you are
interleaving, you have timing skew
I Timing skew becomes jitter as N →∞
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How much of a problem is timing skew?
Interleave N B-bit sub-ADCs
Input signal is sinusoid with frequency fin
στ =
√(N
N − 1
)·(
1
22B
)·(
2
3(2πfin)2
)(10)
[Jenq 1988]
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How much of a problem is timing skew?
0.1 1 102
3
4
5
6
7
8
AD
C R
esol
utio
n [B
its]
Standard Deviation of Skew [ps]
fin
= 2 GHz
fin
= 4 GHz
fin
= 8 GHz
fin
= 16 GHz
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Sources of timing skew
Vout1
Vin
Vout2
0 0.2 0.4 0.6 0.8 10
0.5
1
1.5
2
2.5
3
3σ T
imin
g Sk
ew [
ps]
Normalized Power
Threshold mismatch causes delay change
Rule: Halve deviation with four-fold increase in power (Pelgrom’sequation)
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Sources of timing skew
Vout1
Vin
Vout2
C
C+ C
0 2 4 6 8 10 12 14 160
2
4
6
8
∆ C / C [%]
3σ T
imin
g Sk
ew [
ps]
Trace RC differences cause delay change
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Sources of timing skew
Phas
e G
ener
ator
To Sub-ADC
Vin
Vin
To Sub-ADC
Can easily have over 10 ps skew [Agrawal 2008]
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Part III
Quantitative Analysis of Time-Varying Errors
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Errors exist. What can we do?
Step 1: Quantify error you can tolerate
Step 2: Define your design space
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The sinusoidal approach
Most ADC simulated with a sine wave input
Allows you to define dynamic performance metrics
I Fundamental tone and harmonicsI SFDR: Spurious free dynamic rangeI SNR: Signal to noise ratioI SNDR: Signal to noise and distortion ratio
Can do the same for time-varying errors
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Bounds on time-varying errors (part 1)
Bound on offset
σo =
√(N
N − 1
)·(
A2
3 · 22B
)(11)
Bound on gain
σg =
√(N
N − 1
)·(
2
3 · 22B
)(12)
Bound on timing skew
στ =
√(N
N − 1
)·(
2
3 · 22B · (2πfin)2
)(13)
[Jamal 2001]
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Examples
5-bit ADC with input amplitude A = 1 and N = 2I σo = 25 mVI σg = 3.6 %I στ = 1
175·fin(e.g. fin = 100 MHz, στ ≈ 57 ps)
12-bit ADC with input amplitude A = 1 and N = 2I σo = 0.2 mVI σg = 0.028 %I στ = 1
22,000·fin(e.g. fin = 100 MHz, στ ≈ 0.5 ps)
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Bounds on time-varying errors (part 2)
In real-world applications, ADCs don’t sample sine waves
Many systems are broadband
Tx Rx Data OutData In
Channel
High-Speed Serial Link
5�� ��Using a sine wave at Nyquist will overdesign your system
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Cost of overdesign
More chip area
More power
Longer design cycle
More $$$
Use minimum-mean square error to derive more realistic bounds
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“Best-fit” approach
y [n] = xo [n] + e[n] (14)
xo [n] is the “best-fit”
xo [n] = G x (nTs − τ) (15)
Nontrivial to solve in the general sense
Solvable for WSS and WSCS signals [El-Chammas 2009]
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Intuition
Gai
n (G
)
Skew (t)
Gai
n (G
)
Skew (t)
Find vector that minimizes distance to sub-ADC vectors
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Wide-sense stationary
Definition
A signal is wide-sense stationary (WSS) if its mean and autocorrelation arenot a function of time
m(t1) = m(t2) = m (16)
R(t1, t1 + τ) = R(t2, t2 + τ) = R(τ) (17)
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Calculate the MSE
f (G , τ) = E[e[n]2
]− E [e[n]]2 (18)
Remember:
e[n] = y [n]− xo [n] (19)
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Calculate the MSE
f (G , τ) =
(G 2P +
P
N
N−1∑i=0
G 2i − 2
G
N
N−1∑i=0
Gi R(τi − τ) +1
N
N−1∑i=0
o2i
)−
1
N2
(N−1∑i=0
oi
)2
(20)
(work your “write” arm muscles and derive this)
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Calculate the “best-fit” parameters
�� ��Minimize f (G , τ)
Differentiate with respect to G and τ and set to zero
G =1
NP
N−1∑i=0
GiR(τ − τi ) (21)
τ = arg maxτ
N−1∑i=0
GiR(τ − τi ) (22)
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Mismatch or quantization limited?
SNRf =P
f (G , τ)≷
3
2· 22B = SNRQ (23)
f (G , τ) ≶2 · P
3 · 22B(24)
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Effect of timing skew
Impact on timing skew is different than previously shown
Assume oi = 0 and Gi = 1
1
P
N−1∑i=0
R(τ − τi ) ≥ N
√SNRQ − 1
SNRQ(25)
Let’s make one more assumption: the autocorrelation is second orderdifferentiable
R(τ) ≈ R(0) +����XXXXR ′(0)τ +
R ′′(0)
2τ2 (26)
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Effect of timing skew
στ ≤
√(N
N − 1
)·(
2
3 · 22B
)·(
1
|R ′′(0)|
)(27)
Function of three parameters (N, B, and R ′′(0))
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More on autocorrelation intuition
Autocorrelation related to speed of signal
t
x(t)
R(t)
t
t
x(t)
R(t)
t
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Importance of signal statistics
R(τ) = sinc(2fcτ) (28)
R ′′(0) = −1
3(2πfc )2 (29)
If you had used sine wave analysis, you would overconstrain thevariance of τ by 3
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Importance of signal statistics
Same applies to more realistic signals (e.g. WSCS)
If timing skew is a problem, then improve your design space byknowing your system
Sidenote: this viewpoint also extends to nonlinearities and jitter (Seee.g. [Gupta 2006] and [Da Dalt 2002])
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Questions?
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Part IV
Design of Time-Interleaved ADCs
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The coolest ADCs from the past 10 years
Agilent, 2003, ISSCC
Terranetics, JSSC 2006
Nortel, ISSCC 2010
Fujitsu, OFC 2010
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Interleaving 80 pipeline ADCs
20 GS/s 8 bit ADC
Correct for gain, offset, and timing skew [Poulton 2003]
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Interleaving 4 pipeline ADCs
1 GS/s 11 bit ADC
Correct for gain and offset [Gupta 2006]
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Interleaving 16(0) SAR ADCs
40 GS/s 6 bit ADC
Correct for gain, offset, and timing skew [Greshishchev 2010]
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A 56 GS/s ADC
56 GS/s 8 bit ADC and interleaved 4x80 ADCs [Dedic 2010]
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Choosing the design space
You have: input signal statistics + bit resolution + application space
Calculate acceptable bounds on time-varying errors
Choose sub-ADC architecture (beyond scope of tutorial)
Choose interleaving factor
Design clocking network
Deal with time-varying errors�� ��Looks simpler than it is
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Sub-ADC architecture
Extremely low end resolution and high end resolution choice is easyI Flash ADCs for 3 bitsI Sigma-Delta for 24 bits
SAR, pipeline, ...
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Sub-ADC architecture
10-6
http://www.stanford.edu/~murmann/adcsurvey.html
10-8
10-7
10-10
10-9
s [Jou
les] fJ100
conv-step2ENOBs
PFOMf
10-11
10
P/f s
FlashPipelineSAR
1 766 02
SNDR[ dB] .ENOB.
20 30 40 50 60 70 80 90 100 11010
-13
10-12
SARSigma-DeltaOther
SNDR [dB]
[Image from Murmann class notes]
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Interleaving can lower power*
Lessons from parallel processing [Horowitz 2006]
* at the expense of complexity, area, and headache
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Interleaving can lower power
[Maloberti 2008]
11-bit ADC at 100 MS/s needs ∼ 15 mW
At 800 MS/s needs ∼ 700 mW
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Interleaving can lower power
3 4 5 6 7 8 9 10 11 12
30
35
40
45
50
55
60
65
70
75
Interleaving Factor
Pow
er [
mW
]
Increasing fs will force you to hit a technological wall
True even in the smallest ADC element - the comparator
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Clocking network
Phase Generator
0(t) 1(t) N-1(t)
Phase Generator
0(t) 1(t) N-1(t)
Input Clock
Sub-ADC Clocks
. . . . . . . .
t
0(t)
1(t)
2(t)
N-1(t)
Ts
Ts
Ts
Need to provide N clocks to sub-ADCs
Ideally offset by Ts
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Clocking network
Phase locked loops and delay locked loops
Can use frequencies lower than sub-ADC sample rates
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Clocking network
Clock-gating
Use full-rate clocks and control sub-ADC clock with digital logic (e.g.[Louwsma 2008])
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Clocking network
Shift registers (e.g. [Gao 2008])
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Time-varying errors?
You’ve chosen your sub-ADC architecture
and your interleaving factor
and designed your clocking network
How do you deal with time-varying errors?
Two approaches: correct by design or correct with calibration
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 92 / 158
Approach 1: by design
voffset ≈3√WL
mV /µm (30)
Pelgrom’s Model
12-bit ADC, 1 Vp−p requires less than 0.3 mV offset
WL > 100µm2
In 65 nm CMOS, W > 1.5 mm ...
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Approach 1: by design
There exist analog offset-minimization techniques for amplifiers andcomparators
[Suarez 1975]
Most of these are extremely old
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 94 / 158
Approach 1: by design
Trimming
Dynamic techniques: auto-zeroing or chopping
[Makinwa 2002]
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 95 / 158
Approach 1: by design
Introduce redundancy
[Ginsburg 2008]
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Approach 1: by design
Introduce redundancy
[Ginsburg 2008]
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Alternative approach for offset and gain
Correct with calibration
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Some design techniques for timing skew
Timing skew problem exists between track-and-holds
Use a front-end sampler
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Front-end sampler
[Poulton 1987]
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Front-end sampler
Possible Solution: Hide Timing Skew
28
S. Gupta et al, “A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture “, IEEE JSSC, Dec. 2006, vol. 41, pp. 2650 - 2657
Add a sampler to the ADC front-endAdd a sampler to the ADC front-end and use a full-rate clock
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 101 / 158
Front-end sampler
Possible Solution: Hide Timing Skew
29
Add a sampler to the ADC front-end and use a full-rate clockAdd a sampler to the ADC front-end and use a full-rate clockto hold the input every clock period
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Front-end sampler
Possible Solution: Hide Timing SkewPossible Solution: Hide Timing SkewPossible Solution: Hide Timing Skew
Sub-ADC clocks have some margin for errorSub-ADC clocks have some margin for error
Requires a full-rate clock and a sampler Requires a full-rate clock and a sampler that can settle fast enoughthat can settle fast enough
3131M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 103 / 158
Front-end sampler
[Gupta 2006]
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 104 / 158
Use a better clocking scheme
Front-end samplers have limited application
[Louwsma 2008]
10 b, 1.35 GS/s
Transistor threshold limitation
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 105 / 158
Part V
Calibration
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 106 / 158
Approach 2: use calibration
Straightforward for offset and gain
Not as trivial for timing skew
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 107 / 158
Calibration = estimation + correction
Definition
Estimation: An approximation of the value or extent of something
Definition
Correction: The action or process of correcting something
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Types of calibration
Digital vs. mixed-signal
Foreground vs. background
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 109 / 158
Digital calibration
Adaptive FilterADC0
ADC1
y0[n]y0[n]
y1[n]
x(t)
~
~
Digital
Backend
y1[n]
Detection
Adaptive Filter
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Mixed-signal calibration
ADC0
ADC1
y0[n]
y1[n]
x(t)
Digital
Backend
Detection
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 111 / 158
Foreground calibration
InputOutput
Test
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 112 / 158
Foreground calibration
Input No OutputTest
Detection
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 113 / 158
Background calibration
Input Output
Detection
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 114 / 158
Offset and gain“almost” solved problem
Still a research topic
But ... there is a popular solution
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 115 / 158
Correcting offset
Estimation ...oi ∝
∑j
Di ,j (31)
Correction ...Di ,j = Di ,j − oi (32)
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 116 / 158
Correcting gain
Estimation ...Gi ∝
∑j
(Di ,j )2 (33)
Correction ...Di ,j = Di ,j/Gi (34)
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 117 / 158
Example 1 (1998)
[Fu 1998]
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Example 1 (1998)
[Fu 1998]
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Example 1 (1998)
10-bit, 40 MS/s, two-way interleaved ADC [Fu 1998]
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Example 2 (2001)
[Jamal 2001]
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 121 / 158
Example 2 (2001)
[Jamal 2001]
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Example 3 (2007)
[Oh 2007]
Makes use of pilot tones in OFDM systems
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 123 / 158
Example 3 (2007)
[Oh 2007]
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 124 / 158
Example 3 (2007)
[Oh 2007]
6-bit, 200 MS/sM. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 125 / 158
And timing skew?
Still ongoing research
No single winner
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Example 1 (2001)
[Jamal 2001]
Requires fractional delay filter
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Example 1 (2001)
[Jamal 2001]
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Example 2 (2003)
[Poulton 2003]
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Example 2 (2003)
[Poulton 2003]
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Example 2 (2003)
Foreground calibration
Apply pulse train with fast edges
Use FFT to measure phase delay of T/H
Adjust time delay
Rinse and repeat
[Poulton 2003]
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Example 3 (2005)
[Elbornsson 2005]
Digital and background calibration
Uses cost function based on input statistics
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 132 / 158
Example 3 (2005)
[Elbornsson 2005]
Use inverse DTFT to reconstruct signal using timing estimation
Update timing estimation with cost function (i.e. has cost functiondecreased or increased?)
Requires bandlimited signal (common limitation to many blindcalibration algorithms)
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Example 4 (2008)
[Haftbaradaran 2008]
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 134 / 158
Example 4 (2008)
[Haftbaradaran 2008]
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 135 / 158
Example 4 (2008)
[Haftbaradaran 2008]
Has 0.86 ps delay change (on average)
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Example 4 (2008)
[Haftbaradaran 2008]
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Example 5 (2010)
[Huang 2010]
6-bit 16 GS/s flash ADC
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 138 / 158
Example 5 (2010)
[Huang 2010]
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 139 / 158
Example 5 (2010)
[Huang 2010]
Change capacitive load on delay cells (similar to [Poulton 2003])
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 140 / 158
Example 6 (2010)
[El-Chammas 2010]
5-bit 12 GS/sAdd extra channel (used 1-bit ADC in implementation)M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 141 / 158
Example 6 (2010)
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 142 / 158
Example 6 (2010)
Maximize correlation between extra ADC and each sub-ADC byadjusting delay cell
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 143 / 158
Example 6 (2010)
Adjust delay cell load (around 0.3 ps resolution)
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 144 / 158
Example 6 (2010)
Several hundred milliseconds for initial convergence
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 145 / 158
Example 7 (2011)
[Payne 2011]
12 bit 1GS/s ADCCorrect gain and offset in DSPCorrect timing skew and bandwidth in analog
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 146 / 158
And many more ...
There are many more approaches for timing skew calibration
Some require energy free bands, and others don’t
Some use fractional delay filters, and others tune delay with delay cells
There is much research in both the estimation and correction blocks
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Current time-interleaved ADCs
15 20 25 30 35 40 45 50 55 6010
−1
100
101
102
103
104
Ene
rgy
[pJ]
SNDR [dB]
ADCsFOM=1 pJ/conv−stepFOM=0.1 pJ/conv−step
ADCs faster than 1 GS/s (published in ISSCC and VLSI)
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 148 / 158
Current time-interleaved ADCs
15 20 25 30 35 40 4510
0
101
102
103
Ene
rgy
[pJ]
SNDR [dB]
Other ADCsThis WorkFOM=1 pJ/conv−step
ADCs faster than 10 GS/s
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 149 / 158
Making sense of the noise
Can either minimize mismatch through careful design and layout
Or can use calibration
“Optimal” type of calibration is application and system dependent
Be careful of throwing everything at the digital backend
A lot of room for future research
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 150 / 158
Making sense of the noise
What are some common themes?
Some operations are better done in digital
Others are better in analog
Co-optimization of calibration and circuit design
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 151 / 158
Summary
Time-interleaved ADCs important in pushing performance
Time-varying errors set performance limitations
System-level analysis improves design space specifications (e.g.mismatch constraints and ADC architecture)
Calibration techniques extremely useful in compensating for errors
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 152 / 158
Questions
Email: [email protected], [email protected]
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 153 / 158
Thank you
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 154 / 158
References
R.E. Suarez, P.R. Gray, and D.A. Hodges, “All-MOS Charge RedistributionAnalog-to-Digital Conversion Techniques–Part II,” IEEE Journal of Solid-State Circuits,vol. sc-10, no. 6, pp. 379-385, Dec. 1975
W. Black and D. Hodges, “Time Interleaved Converter Arrays,” IEEE Journal ofSolid-State Circuits, vol. 15, no. 6, pp. 1022-1029, Dec. 1980
K. Poulton, J. Corcoran, and T. Hornak, “A 1-GHz 6-bit ADC System,” IEEE Journal ofSolid-State Circuits, vol. 22, no. 6, pp. 962-970, Dec. 1987
Y.-C. Jenq, “Digital Spectra of Nonuniformly Sampled Signals: Fundamentals andHigh-Speed Waveform Digitizers,” IEEE Transactions on Instrumentation andMeasurement, vol. 37, no. 2, pp. 245-251, June 1988
D. Fu, K.C. Dyer, S.H. Lewis, and P.J. Hurst, “A Digital Background CalibrationTechnique for Time-Interleaved Analog-to-Digital Converters,” IEEE Journal ofSolid-State Circuits, vol. 33, no. 12, pp. 1904-1911, Dec. 1998
S. Jamal, “Digital Background Calibration of Time-Interleaved Analog-to-DigitalConverters,” Ph.D. dissertation, U.C. Davis, Davis, CA, 2001
N. Da Dalt, M. Hareneck, C. Sandner, and A. Wiesbauer, “On the Jitter Requirements ofthe Sampling Clock for Analog-to-Digital Converters,” IEEE Transactions on Circuits andSystems I: Fundamental Theory and Applications, vol. 49, no. 9, pp. 1354-1360, Sept.2002
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 155 / 158
References
K. Makinwa, “Dynamic Offset-Cancellation Techniques,” Smart Sensor Systems, 2002
K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C.Tan, and A. Montijo, “A 20 GS/s 8 b ADC with a 1 MB Memory in 0.18 µm CMOS,” inProceedings of IEEE International Solid-State Circuits Conference, vol. 1, Feb. 2003, pp.318-496
J. Elbornsson, F. Gustafsson, and J.-E. Eklund, “Blind Equalization of Time Errors in aTime-Interleaved ADC System”, IEEE Transactions on Signal Processing, vol. 53, no. 4,pp. 1413-1424, Apr. 2005
S. Gupta, M. Inergield, and J. Wang, “A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mWPower Realized by a High Bandwidth Scalable Time-Interleaved Architecture,” IEEEJournal of Solid-State Circuits, vol. 41, no. 12, pp. 2650-2657, Dec. 2006
M. Horowitz, “Scaling, Power and the Future of CMOS,” Workshop on On- and Off-ChipInterconnection Networks for Multicore Systems, Stanford, CA, Dec. 2006
Y. Oh and B. Murmann, “A Low-Power, 6-bit Time-Interleaved SAR ADC Using OFDMPilot Tone Calibration,” in Proceedings of IEEE Custom Integrated Circuits Conf., SanJose, CA, Sep. 2007, pp. 193-194
B. Ginsburg and A. Chandrakasan, “Highly Interleaved 5b 250 MS/s ADC withRedundant Channels in 65nm CMOS,” in Proceedings of IEEE International Solid-StateCircuits Conference, vol. 1, Feb. 2008, pp. 240-610
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 156 / 158
References
A. Haftbaradaran and K.W. Martin, “A Background Sample-Time Error CalibrationTechnique Using Random Data for Wide-Band High-Resolution Time-Interleaved ADCs,”IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, no. 3, pp. 234-238,Mar. 2008
S. Louwsma, A. van Tuijl, M. Vertregt, and B. Nauta, “A 1.35 GS/s, 10 b, 175 mWTime-Interleaved AD Converter in 0.13 µm CMOS,” IEEE Journal of Solid-State Circuits,vol. 43, no. 4, pp. 778-786, Apr. 2008
X. Gao, E. Klumperink, and B. Nauta, “Advantages of Shift Registers Over DLLs forFlexible Low Jitter Multiphase Clock Generation,” IEEE Transactions on Circuits andSystems II: Express Briefs, vol. 55, no. 3, pp. 244-248, Mar. 2008
F. Maloberti, “High-Performance Data Converters: Trends, Process Technologies andDesign Challenges,” IEEE Asia Pacific Conference on Circuits and Systems, vol. 1, Nov.2008, pp. 12-16
M. El-Chammas and B. Murmann, “General Analysis on the Impact of Phase-Skew inTime-Interleaved ADCs,” IEEE Transactions on Circuits and Systems I: Regular Papers,vol. 56, no. 5, pp. 902-910, May 2009
A. Agrawal, A. Liu, P. Hanumolu, and G.-Y. Wei, “An 8×5 Gb/s Parallel Receiver WithCollaborative Riming Recovery,” IEEE Journal of Solid-State Circuits, vol. 44, no. 11, pp.3120-3130, Nov. 2009
M. El-Chammas (TI) Time-Interleaved ADCs Dec. 2011 157 / 158
References
Y. Greshishchev, J. Aguirre, M. Besson, R. Gibbins, C. Falt, P. Flemke, N. Ben-Hamida,D. Pollex, P. Schvan, and S.-C. Wang, “A 40 GS/s 6b ADC in 65nm CMOS,” inProceedings of IEEE International Solid-State Circuits Conference, vol. 1, Feb. 2010, pp.390-391
I. Dedic, “56 GS/s ADC Enabling 100GbE,” OFC 2010
B. Murmann, EE315B 2010 Class Notes, Stanford University,
C.-C. Huang, C.-Y. Wang, and J.-T. Wu, “A CMOS 6-bit 16-GS/s Time-Interleaved ADCwith Digital Background Calibration,” in VLSI Circuits Symposium, Digest of TechnicalPapers, June 2010, pp. 159-160
M. El-Chammas and B. Murmann, “A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADCWith Background Timing Skew Calibration,” in VLSI Circuits Symposium, Digest ofTechnical Papers, June 2010, pp. 157-158
R. Payne, et al., “A 12b 1GS/s SiGe BiCMOS Two-Way Time-Interleaved Pipeline ADC,”in Proceedings of IEEE International Solid-State Circuits Conference, vol. 1, Feb. 2011,pp. 182-183
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