Tightly Coupled Microprocessors

8/13/2019 Tightly Coupled Microprocessors

1/14


2/14

MIMD Systems

Each PE Works

independently ofothers.

Processor 1 is said to beindependent of

processors 2,3..N atany instant, if and only

if task being executedby processor 1 has nointeractions with tasksexecuted by processor2,3.N and vice-versa.

However results from

processor X may beneeded by processorY.

h

r

t


3/14

This can be done by directlysending the results torequiring processors or

storing them in a sharedmemory.

Which causes the basis popular MIMD organizat

(a) Shared Memory or TightArchitecture.

(b) Message Passing or LoosCoupled Architecture.


4/14

Shared Memory Architecture/Tightly CoupleArchitecture

AnyProcessor

i canaccess anymemory

module jthroughinterconnec

tionnetwork.

The resultsof the

computation are

stored inthe

memory bytheprocessor

thatexecutedthe task.

If thresultsrequireother ta

they mbe accefrom memo


5/14

Called TightlyCoupled

Architecture, sincethe processors are

interconnectedsuch that theinterchange ofdata between

them through the

shared memory isquite rapid.

Memory accesstime is same forall processors

hence also calledas Uniform

MemoryArchitecture

(UMA).

If Processors aredifferent 32-bitand 16-bit and

memory consists of32-bit words, eachmemory word mustbe converted intowords for the use

of 16-bit

processors. This isan Overhead.

Another problem isMemory

Contention whichoccurs when two

or more processorstry to access same

shared memoryblock.

Since memoryblock can be

accessed only bone processor a

time, all theothers requestithe same blocmust wait untifirst processor

through using i


6/14

Message Passing Architecture/Loosely CoupleArchitecture

There isno sharedmemoryat all in

thesystem,

each

processorhas a localmemory

blockattached

to it.

Theconglomeration

of all localmemories is thetotal memory

that the systempossesses. It is

also calledDistributed

MIMD.

If daexchan

requibetweeprocess

thiconfiguthe requ

processendmessage

in whmemorreque

data is s


7/14

The requestedprocessor finishes itstask under process

then access itsmemory for the

requested data andpasses it on to

interconnection

network whichroutes it towards therequesting processor.

For all this timerequesting processor

sits idle incurringlarge overheads.

Memory access timevaries between the

processors andhence these

architectures areknown as Non-

Uniform Memory

Access (NUMA).


8/14

Comparison Of Tightly Coupled Vs. LooselyCoupled Architecture

Tightly Coupled Architecture Loosely Coupled Architecture

1. More rapid data interchange betweenprocessors in comparison to Loosely

Coupled Architecture.

1. Less rapid data interchange betweeprocessors in comparison to Tightly

Coupled Architecture.

2. More memory contention problem. 2. Less memory contention incomparison to tightly coupled

architecture.

3. Also called as shared memoryarchitectures, UMA, Multiprocessor

system.

3. Also called as message passingarchitectures, NUMA, Multicomputer

system.


9/14

Examples of Tightly Coupled Multiprocessors

1. Cyber-170 Architecture

Consists of

twosubsystems

(a) Central

processingsubsystem

(b)Peripheral

processingsubsystem

Both haveaccess to

commoncentralmemory

Through CMController,which is a

high speedCross bar

switch


10/14

1. A Cyber-170 Multiprocessor Configurationwith two processors

CM and ECM form two levelmemory hierarchy.

CMC becomes switchingcentre and performs functionof ISIN, IOPIN and PMIN.


11/14

2. Honeywell 60/66 Architecture

Every centralprocessor and every

I/O Mux is connectedto every systemcontroller (SC).

This provides

adequate redundancyin paths for highavailability.

In event of failure on

the SC, all IOMs arestill accessible byeach processor.

SC acts a

controassociamemor


12/14

A Honeywell 60/66 multiprocessor system

SC also acts as an intelligentswitch to route interruptsand other communicationsamong the various systemcomponents.

When more than one elementattempts to access the samememory module, thecorresponding SC resolves theconflict.

This triple redundancyenhances availability and

fault tolerance.


13/14

3. The PDP-10 multiprocessor

There are two configurations ofPDP-10 multiprocessor systemwith multi-ported memorymodules. Each CPU has a cacheof 2K words, where each word is36 bits.

Fig. shows Asymmetric Master-Slave configuration, the twoprocessors are identical, butasymmetry is result ofconnection of peripherals to themaster only.

Slave can not initiate peripheraloperations nor respond to an

interrupt directly.


14/14

Fig. shows a symmetric configuration, bothprocessors are connected to a set of shared fastand slow peripherals, however each datachannel is attached to one processor, which isthe only processor that can use it.

Slow peripherals are connected to both

processors via a switch. There is no cache invalidate interface between

them. It is assumed that a software solution isused to enforce cache consistency.

Inherent redundancy in a multiprocessor systemprobably increases its ability to be faulttolerant.

Tightly Coupled Microprocessors

Documents

Transcript of Tightly Coupled Microprocessors