This is Only a Test

Please Take Out ONE 8-1/2" x 11"

Sheet of Paper and a #2 Pencil

If You Did Not Bring Paper or Pencil, Please Wait until They Have Been Provided to You

The Test Will Not Begin until Everyone

is Ready

Is Everyone Ready?

Good! Let's Begin

Question #1: ECE2010

Write the V-I Equation for this Circuit Element:


Write the Boolean Logic Expression

for this Circuit Element:


Write the V-I Equation for this Circuit Element:

Remember to Answer Each

Question Completely!

Your Education is Important to Us


Determine the Gain of This Circuit:

vOUT1

1 kΩ 2 kΩ

1 mA


Find the Bias Currents of Each Transistor in This

Circuit:

VIPVOP

VIM VOM

VB3VB4

VB2

VB1VB5 VB5

Question #9: ECE529C

Determine the kT/C Noise in the

Following Circuit:

V OUT

+5V

+15V

5 kΩ

t = 0

1 µF

Question #12: ECE679Q(Advanced Cryptography)

WXR IJFYC SBHRW UWFGD PK Q

BLTNRN?

Question #16: ECE689B

Determine the Phase Margin of the

Following Circuit:

RCLK

RDATA

Vin

RCLK

RDATA

Vin

Receive end

fiberlink

Clock recovery

Question #120:

Did you Notice the Person Next To You

Hasn't Missed a Problem Yet?

ADC "A"

€

xA

€

vIN

€

xB

ERRORESTIMATION

+

+

+

-€

x

€

Δx = xB − xA

ADC "B"

€

x

€

t

ADC "A" ADC "B"

SWITCHEDCAPNETWORK

OP-AMP

COMPARATORS

“A” L.U.T.

€

dkA

€

vIN

€

1ˆ G A

⎛

⎝ ⎜

⎞

⎠ ⎟

k

€

k1G

⎛ ⎝ ⎜

⎞ ⎠ ⎟k

€

xA

€

SDKA

ERROREST.

€

Δx

€

ˆ ε A

€

μ

€

ˆ G A

€

+

€

−

€

x

€

ˆ ε B

€

μ

€

SDKB

€

xB

€

ˆ G B

€

1ˆ G B

⎛

⎝ ⎜

⎞

⎠ ⎟

k

€

dkB

€

+

€

+

OFF-CHIP DIGITAL PROCESSOR (FPGA)

PATH A

PATH B

S/H

€

GA

COMPS€

+

€

−

COMPS

S/H

€

GB

DAC

€

+

€

−

CYCLIC RESIDUE AMPLIFIERS

“B” L.U.T.

ERRORCOEFF

L.U.T.

DAC

“... a figure of the way the strong of mind and strong of arm should fit together,

One thick where one is thin and vice versa. ”

V T

N H

• Key idea: two “partners”trying to do the same thing

in different ways

LIBERAL

ARTS

Remember, This is Only a Test

€

vIN

⇓

vRES(1) = GvIN − d1VREF

⇓

vRES(2) = G GvIN − d1VREF[ ]

vRES(1)6 7 4 4 8 4 4 − d2VREF

⇓

vRES(3) = G G GvIN − d1VREF[ ] − d2VREF[ ]

vRES(2)6 7 4 4 4 4 4 8 4 4 4 4 4 − d3VREF

€

vRES(3) = G3vIN − G2d1 + G1d2 + G0d3[ ] VREF

(6)

(9)

(10) (11)

(9)

(29)

UPDATE

N CYCLES

AVG

x OUT

SAMPLE vIN

A, B PATHS

ESTIMATIONMATRIX

€

1 ˆ G A( )k

€

1 ˆ G B( )k

€

k 1 G( )k

SDKA, SDKB

COEFFS

CALIBRATION(OPERATES OVER SET OF 6 CONVERSIONS)

CONVERSION

UPDATE µe

€

ˆ ε A , ˆ ε B , ˆ ε g

€

ˆ ε A , ˆ ε B , ˆ ε g€

ˆ G A , ˆ G B

€

ˆ G A , ˆ G B

new

old

µG new

old

UPDATEDECISIONWEIGHTL.U.T.s

L.U.T.s

STATEESTIMATES

dkA,dkB DECISIONS

(8)

x

(22)

RADIX CORRECTION

xA,xB CODES

Table (1)

(12) DIFF

∆x

We areTPB

CREATIVE USEFUL

GOOD PAY

ENGINEER

PROFESSOR TEACHER

NURSE

ARTIST

POET

DOCTORADVERTISING

LAWYER

STOCKBROKER

µe

µG 2-7

2-3 2-5 2-7

This Has Only Been a Test

It's Time to Put Your Pencils Down

And Put Your Hands Together

This is

Professor

This is Only a Test

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